drivers/mtd/nand/davinci_nand.c

   1 /*
   2  * NAND driver for TI DaVinci based boards.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
   7  */
   8
   9 /*
  10  *
  11  * linux/drivers/mtd/nand/nand_davinci.c
  12  *
  13  * NAND Flash Driver
  14  *
  15  * Copyright (C) 2006 Texas Instruments.
  16  *
  17  * ----------------------------------------------------------------------------
  18  *
  19  * SPDX-License-Identifier:     GPL-2.0+
  20  *
  21  * ----------------------------------------------------------------------------
  22  *
  23  *  Overview:
  24  *   This is a device driver for the NAND flash device found on the
  25  *   DaVinci board which utilizes the Samsung k9k2g08 part.
  26  *
  27  Modifications:
  28  ver. 1.0: Feb 2005, Vinod/Sudhakar
  29  -
  30  */
  31
  32 #include <common.h>
  33 #include <asm/io.h>
  34 #include <nand.h>
  35 #include <asm/arch/nand_defs.h>
  36 #include <asm/arch/emif_defs.h>
  37
  38 /* Definitions for 4-bit hardware ECC */
  39 #define NAND_TIMEOUT                    10240
  40 #define NAND_ECC_BUSY                   0xC
  41 #define NAND_4BITECC_MASK               0x03FF03FF
  42 #define EMIF_NANDFSR_ECC_STATE_MASK     0x00000F00
  43 #define ECC_STATE_NO_ERR                0x0
  44 #define ECC_STATE_TOO_MANY_ERRS         0x1
  45 #define ECC_STATE_ERR_CORR_COMP_P       0x2
  46 #define ECC_STATE_ERR_CORR_COMP_N       0x3
  47
  48 /*
  49  * Exploit the little endianness of the ARM to do multi-byte transfers
  50  * per device read. This can perform over twice as quickly as individual
  51  * byte transfers when buffer alignment is conducive.
  52  *
  53  * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  54  * the address bus. On Davinci EVM platforms this has always been true.
  55  */
  56 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  57 {
  58         struct nand_chip *chip = mtd->priv;
  59         const u32 *nand = chip->IO_ADDR_R;
  60
  61         /* Make sure that buf is 32 bit aligned */
  62         if (((int)buf & 0x3) != 0) {
  63                 if (((int)buf & 0x1) != 0) {
  64                         if (len) {
  65                                 *buf = readb(nand);
  66                                 buf += 1;
  67                                 len--;
  68                         }
  69                 }
  70
  71                 if (((int)buf & 0x3) != 0) {
  72                         if (len >= 2) {
  73                                 *(u16 *)buf = readw(nand);
  74                                 buf += 2;
  75                                 len -= 2;
  76                         }
  77                 }
  78         }
  79
  80         /* copy aligned data */
  81         while (len >= 4) {
  82                 *(u32 *)buf = __raw_readl(nand);
  83                 buf += 4;
  84                 len -= 4;
  85         }
  86
  87         /* mop up any remaining bytes */
  88         if (len) {
  89                 if (len >= 2) {
  90                         *(u16 *)buf = readw(nand);
  91                         buf += 2;
  92                         len -= 2;
  93                 }
  94
  95                 if (len)
  96                         *buf = readb(nand);
  97         }
  98 }
  99
 100 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 101                                    int len)
 102 {
 103         struct nand_chip *chip = mtd->priv;
 104         const u32 *nand = chip->IO_ADDR_W;
 105
 106         /* Make sure that buf is 32 bit aligned */
 107         if (((int)buf & 0x3) != 0) {
 108                 if (((int)buf & 0x1) != 0) {
 109                         if (len) {
 110                                 writeb(*buf, nand);
 111                                 buf += 1;
 112                                 len--;
 113                         }
 114                 }
 115
 116                 if (((int)buf & 0x3) != 0) {
 117                         if (len >= 2) {
 118                                 writew(*(u16 *)buf, nand);
 119                                 buf += 2;
 120                                 len -= 2;
 121                         }
 122                 }
 123         }
 124
 125         /* copy aligned data */
 126         while (len >= 4) {
 127                 __raw_writel(*(u32 *)buf, nand);
 128                 buf += 4;
 129                 len -= 4;
 130         }
 131
 132         /* mop up any remaining bytes */
 133         if (len) {
 134                 if (len >= 2) {
 135                         writew(*(u16 *)buf, nand);
 136                         buf += 2;
 137                         len -= 2;
 138                 }
 139
 140                 if (len)
 141                         writeb(*buf, nand);
 142         }
 143 }
 144
 145 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 146                 unsigned int ctrl)
 147 {
 148         struct          nand_chip *this = mtd->priv;
 149         u_int32_t       IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
 150
 151         if (ctrl & NAND_CTRL_CHANGE) {
 152                 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
 153
 154                 if (ctrl & NAND_CLE)
 155                         IO_ADDR_W |= MASK_CLE;
 156                 if (ctrl & NAND_ALE)
 157                         IO_ADDR_W |= MASK_ALE;
 158                 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 159         }
 160
 161         if (cmd != NAND_CMD_NONE)
 162                 writeb(cmd, IO_ADDR_W);
 163 }
 164
 165 #ifdef CONFIG_SYS_NAND_HW_ECC
 166
 167 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
 168 {
 169         u_int32_t       ecc = 0;
 170
 171         ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
 172                                 CONFIG_SYS_NAND_CS - 2]));
 173
 174         return ecc;
 175 }
 176
 177 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 178 {
 179         u_int32_t       val;
 180
 181         /* reading the ECC result register resets the ECC calculation */
 182         nand_davinci_readecc(mtd);
 183
 184         val = __raw_readl(&davinci_emif_regs->nandfcr);
 185         val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 186         val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
 187         __raw_writel(val, &davinci_emif_regs->nandfcr);
 188 }
 189
 190 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 191                 u_char *ecc_code)
 192 {
 193         u_int32_t               tmp;
 194
 195         tmp = nand_davinci_readecc(mtd);
 196
 197         /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
 198          * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
 199         tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
 200
 201         /* Invert so that erased block ECC is correct */
 202         tmp = ~tmp;
 203
 204         *ecc_code++ = tmp;
 205         *ecc_code++ = tmp >>  8;
 206         *ecc_code++ = tmp >> 16;
 207
 208         /* NOTE:  the above code matches mainline Linux:
 209          *      .PQR.stu ==> ~PQRstu
 210          *
 211          * MontaVista/TI kernels encode those bytes differently, use
 212          * complicated (and allegedly sometimes-wrong) correction code,
 213          * and usually shipped with U-Boot that uses software ECC:
 214          *      .PQR.stu ==> PsQRtu
 215          *
 216          * If you need MV/TI compatible NAND I/O in U-Boot, it should
 217          * be possible to (a) change the mangling above, (b) reverse
 218          * that mangling in nand_davinci_correct_data() below.
 219          */
 220
 221         return 0;
 222 }
 223
 224 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 225                 u_char *read_ecc, u_char *calc_ecc)
 226 {
 227         struct nand_chip *this = mtd->priv;
 228         u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
 229                                           (read_ecc[2] << 16);
 230         u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
 231                                           (calc_ecc[2] << 16);
 232         u_int32_t diff = ecc_calc ^ ecc_nand;
 233
 234         if (diff) {
 235                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 236                         /* Correctable error */
 237                         if ((diff >> (12 + 3)) < this->ecc.size) {
 238                                 uint8_t find_bit = 1 << ((diff >> 12) & 7);
 239                                 uint32_t find_byte = diff >> (12 + 3);
 240
 241                                 dat[find_byte] ^= find_bit;
 242                                 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
 243                                          "bit ECC error at offset: %d, bit: "
 244                                          "%d\n", find_byte, find_bit);
 245                                 return 1;
 246                         } else {
 247                                 return -1;
 248                         }
 249                 } else if (!(diff & (diff - 1))) {
 250                         /* Single bit ECC error in the ECC itself,
 251                            nothing to fix */
 252                         MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
 253                                  "ECC.\n");
 254                         return 1;
 255                 } else {
 256                         /* Uncorrectable error */
 257                         MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 258                         return -1;
 259                 }
 260         }
 261         return 0;
 262 }
 263 #endif /* CONFIG_SYS_NAND_HW_ECC */
 264
 265 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 266 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 267 #if defined(CONFIG_SYS_NAND_PAGE_2K)
 268         .eccbytes = 40,
 269 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 270         .eccpos = {
 271                 6,   7,  8,  9, 10,     11, 12, 13, 14, 15,
 272                 22, 23, 24, 25, 26,     27, 28, 29, 30, 31,
 273                 38, 39, 40, 41, 42,     43, 44, 45, 46, 47,
 274                 54, 55, 56, 57, 58,     59, 60, 61, 62, 63,
 275         },
 276         .oobfree = {
 277                 {2, 4}, {16, 6}, {32, 6}, {48, 6},
 278         },
 279 #else
 280         .eccpos = {
 281                 24, 25, 26, 27, 28,
 282                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
 283                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
 284                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
 285                 59, 60, 61, 62, 63,
 286                 },
 287         .oobfree = {
 288                 {.offset = 2, .length = 22, },
 289         },
 290 #endif  /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
 291 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
 292         .eccbytes = 80,
 293         .eccpos = {
 294                 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
 295                 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
 296                 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
 297                 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
 298                 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
 299                 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
 300                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 301                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 302                 },
 303         .oobfree = {
 304                 {.offset = 2, .length = 46, },
 305         },
 306 #endif
 307 };
 308
 309 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 310 {
 311         u32 val;
 312
 313         switch (mode) {
 314         case NAND_ECC_WRITE:
 315         case NAND_ECC_READ:
 316                 /*
 317                  * Start a new ECC calculation for reading or writing 512 bytes
 318                  * of data.
 319                  */
 320                 val = __raw_readl(&davinci_emif_regs->nandfcr);
 321                 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
 322                 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 323                 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
 324                 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
 325                 __raw_writel(val, &davinci_emif_regs->nandfcr);
 326                 break;
 327         case NAND_ECC_READSYN:
 328                 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
 329                 break;
 330         default:
 331                 break;
 332         }
 333 }
 334
 335 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
 336 {
 337         int i;
 338
 339         for (i = 0; i < 4; i++) {
 340                 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
 341                         NAND_4BITECC_MASK;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
 348                                            const uint8_t *dat,
 349                                            uint8_t *ecc_code)
 350 {
 351         unsigned int hw_4ecc[4];
 352         unsigned int i;
 353
 354         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 355
 356         /*Convert 10 bit ecc value to 8 bit */
 357         for (i = 0; i < 2; i++) {
 358                 unsigned int hw_ecc_low = hw_4ecc[i * 2];
 359                 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
 360
 361                 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
 362                 *ecc_code++ = hw_ecc_low & 0xFF;
 363
 364                 /*
 365                  * Take 2 bits as LSB bits from val1 (count1=0) or val5
 366                  * (count1=1) and 6 bits from val2 (count1=0) or
 367                  * val5 (count1=1)
 368                  */
 369                 *ecc_code++ =
 370                     ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
 371
 372                 /*
 373                  * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
 374                  * 4 bits from val3 (count1=0) or val6 (count1=1)
 375                  */
 376                 *ecc_code++ =
 377                     ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
 378
 379                 /*
 380                  * Take 6 bits from val3(count1=0) or val6 (count1=1) and
 381                  * 2 bits from val4 (count1=0) or  val7 (count1=1)
 382                  */
 383                 *ecc_code++ =
 384                     ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
 385
 386                 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
 387                 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 394                                           uint8_t *read_ecc, uint8_t *calc_ecc)
 395 {
 396         int i;
 397         unsigned int hw_4ecc[4];
 398         unsigned int iserror;
 399         unsigned short *ecc16;
 400         unsigned int numerrors, erroraddress, errorvalue;
 401         u32 val;
 402
 403         /*
 404          * Check for an ECC where all bytes are 0xFF.  If this is the case, we
 405          * will assume we are looking at an erased page and we should ignore
 406          * the ECC.
 407          */
 408         for (i = 0; i < 10; i++) {
 409                 if (read_ecc[i] != 0xFF)
 410                         break;
 411         }
 412         if (i == 10)
 413                 return 0;
 414
 415         /* Convert 8 bit in to 10 bit */
 416         ecc16 = (unsigned short *)&read_ecc[0];
 417
 418         /*
 419          * Write the parity values in the NAND Flash 4-bit ECC Load register.
 420          * Write each parity value one at a time starting from 4bit_ecc_val8
 421          * to 4bit_ecc_val1.
 422          */
 423
 424         /*Take 2 bits from 8th byte and 8 bits from 9th byte */
 425         __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
 426                         &davinci_emif_regs->nand4biteccload);
 427
 428         /* Take 4 bits from 7th byte and 6 bits from 8th byte */
 429         __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
 430                         &davinci_emif_regs->nand4biteccload);
 431
 432         /* Take 6 bits from 6th byte and 4 bits from 7th byte */
 433         __raw_writel((ecc16[3] >> 2) & 0x3FF,
 434                         &davinci_emif_regs->nand4biteccload);
 435
 436         /* Take 8 bits from 5th byte and 2 bits from 6th byte */
 437         __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
 438                         &davinci_emif_regs->nand4biteccload);
 439
 440         /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
 441         __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
 442                         &davinci_emif_regs->nand4biteccload);
 443
 444         /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
 445         __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
 446                         &davinci_emif_regs->nand4biteccload);
 447
 448         /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
 449         __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
 450                         &davinci_emif_regs->nand4biteccload);
 451
 452         /* Take 10 bits from 0th and 1st bytes */
 453         __raw_writel((ecc16[0]) & 0x3FF,
 454                         &davinci_emif_regs->nand4biteccload);
 455
 456         /*
 457          * Perform a dummy read to the EMIF Revision Code and Status register.
 458          * This is required to ensure time for syndrome calculation after
 459          * writing the ECC values in previous step.
 460          */
 461
 462         val = __raw_readl(&davinci_emif_regs->nandfsr);
 463
 464         /*
 465          * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
 466          * A syndrome value of 0 means no bit errors. If the syndrome is
 467          * non-zero then go further otherwise return.
 468          */
 469         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 470
 471         if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
 472                 return 0;
 473
 474         /*
 475          * Clear any previous address calculation by doing a dummy read of an
 476          * error address register.
 477          */
 478         val = __raw_readl(&davinci_emif_regs->nanderradd1);
 479
 480         /*
 481          * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
 482          * register to 1.
 483          */
 484         __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
 485                         &davinci_emif_regs->nandfcr);
 486
 487         /*
 488          * Wait for the corr_state field (bits 8 to 11) in the
 489          * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
 490          * Otherwise ECC calculation has not even begun and the next loop might
 491          * fail because of a false positive!
 492          */
 493         i = NAND_TIMEOUT;
 494         do {
 495                 val = __raw_readl(&davinci_emif_regs->nandfsr);
 496                 val &= 0xc00;
 497                 i--;
 498         } while ((i > 0) && !val);
 499
 500         /*
 501          * Wait for the corr_state field (bits 8 to 11) in the
 502          * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
 503          */
 504         i = NAND_TIMEOUT;
 505         do {
 506                 val = __raw_readl(&davinci_emif_regs->nandfsr);
 507                 val &= 0xc00;
 508                 i--;
 509         } while ((i > 0) && val);
 510
 511         iserror = __raw_readl(&davinci_emif_regs->nandfsr);
 512         iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
 513         iserror = iserror >> 8;
 514
 515         /*
 516          * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
 517          * corrected (five or more errors).  The number of errors
 518          * calculated (err_num field) differs from the number of errors
 519          * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
 520          * correction complete (errors on bit 8 or 9).
 521          * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
 522          * complete (error exists).
 523          */
 524
 525         if (iserror == ECC_STATE_NO_ERR) {
 526                 val = __raw_readl(&davinci_emif_regs->nanderrval1);
 527                 return 0;
 528         } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
 529                 val = __raw_readl(&davinci_emif_regs->nanderrval1);
 530                 return -1;
 531         }
 532
 533         numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
 534                         & 0x3) + 1;
 535
 536         /* Read the error address, error value and correct */
 537         for (i = 0; i < numerrors; i++) {
 538                 if (i > 1) {
 539                         erroraddress =
 540                             ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
 541                               (16 * (i & 1))) & 0x3FF);
 542                         erroraddress = ((512 + 7) - erroraddress);
 543                         errorvalue =
 544                             ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
 545                               (16 * (i & 1))) & 0xFF);
 546                 } else {
 547                         erroraddress =
 548                             ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
 549                               (16 * (i & 1))) & 0x3FF);
 550                         erroraddress = ((512 + 7) - erroraddress);
 551                         errorvalue =
 552                             ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
 553                               (16 * (i & 1))) & 0xFF);
 554                 }
 555                 /* xor the corrupt data with error value */
 556                 if (erroraddress < 512)
 557                         dat[erroraddress] ^= errorvalue;
 558         }
 559
 560         return numerrors;
 561 }
 562 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
 563
 564 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 565 {
 566         return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
 567 }
 568
 569 static void nand_flash_init(void)
 570 {
 571         /* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
 572          * Instead, have your board_init() set EMIF timings, based on its
 573          * knowledge of the clocks and what devices are hooked up ... and
 574          * don't even do that unless no UBL handled it.
 575          */
 576 #ifdef CONFIG_SOC_DM644X
 577         u_int32_t       acfg1 = 0x3ffffffc;
 578
 579         /*------------------------------------------------------------------*
 580          *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
 581          *                                                                  *
 582          *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
 583          *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
 584          *                                                                  *
 585          *------------------------------------------------------------------*/
 586          acfg1 = 0
 587                 | (0 << 31)     /* selectStrobe */
 588                 | (0 << 30)     /* extWait */
 589                 | (1 << 26)     /* writeSetup   10 ns */
 590                 | (3 << 20)     /* writeStrobe  40 ns */
 591                 | (1 << 17)     /* writeHold    10 ns */
 592                 | (1 << 13)     /* readSetup    10 ns */
 593                 | (5 << 7)      /* readStrobe   60 ns */
 594                 | (1 << 4)      /* readHold     10 ns */
 595                 | (3 << 2)      /* turnAround   ?? ns */
 596                 | (0 << 0)      /* asyncSize    8-bit bus */
 597                 ;
 598
 599         __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
 600
 601         /* NAND flash on CS2 */
 602         __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
 603 #endif
 604 }
 605
 606 void davinci_nand_init(struct nand_chip *nand)
 607 {
 608         nand->chip_delay  = 0;
 609 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 610         nand->bbt_options         |= NAND_BBT_USE_FLASH;
 611 #endif
 612 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 613         nand->options     |= NAND_NO_SUBPAGE_WRITE;
 614 #endif
 615 #ifdef CONFIG_SYS_NAND_HW_ECC
 616         nand->ecc.mode = NAND_ECC_HW;
 617         nand->ecc.size = 512;
 618         nand->ecc.bytes = 3;
 619         nand->ecc.strength = 1;
 620         nand->ecc.calculate = nand_davinci_calculate_ecc;
 621         nand->ecc.correct  = nand_davinci_correct_data;
 622         nand->ecc.hwctl  = nand_davinci_enable_hwecc;
 623 #else
 624         nand->ecc.mode = NAND_ECC_SOFT;
 625 #endif /* CONFIG_SYS_NAND_HW_ECC */
 626 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 627         nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
 628         nand->ecc.size = 512;
 629         nand->ecc.bytes = 10;
 630         nand->ecc.strength = 4;
 631         nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
 632         nand->ecc.correct = nand_davinci_4bit_correct_data;
 633         nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
 634         nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
 635 #endif
 636         /* Set address of hardware control function */
 637         nand->cmd_ctrl = nand_davinci_hwcontrol;
 638
 639         nand->read_buf = nand_davinci_read_buf;
 640         nand->write_buf = nand_davinci_write_buf;
 641
 642         nand->dev_ready = nand_davinci_dev_ready;
 643
 644         nand_flash_init();
 645 }
 646
 647 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
 648
 649 int board_nand_init(struct nand_chip *chip)
 650 {
 651         davinci_nand_init(chip);
 652         return 0;
 653 }