drivers/mtd/nand/davinci_nand.c

   1 /*
   2  * NAND driver for TI DaVinci based boards.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
   7  */
   8
   9 /*
  10  *
  11  * linux/drivers/mtd/nand/nand_davinci.c
  12  *
  13  * NAND Flash Driver
  14  *
  15  * Copyright (C) 2006 Texas Instruments.
  16  *
  17  * ----------------------------------------------------------------------------
  18  *
  19  * SPDX-License-Identifier:     GPL-2.0+
  20  *
  21  * ----------------------------------------------------------------------------
  22  *
  23  *  Overview:
  24  *   This is a device driver for the NAND flash device found on the
  25  *   DaVinci board which utilizes the Samsung k9k2g08 part.
  26  *
  27  Modifications:
  28  ver. 1.0: Feb 2005, Vinod/Sudhakar
  29  -
  30  */
  31
  32 #include <common.h>
  33 #include <asm/io.h>
  34 #include <nand.h>
  35 #include <asm/ti-common/davinci_nand.h>
  36
  37 /* Definitions for 4-bit hardware ECC */
  38 #define NAND_TIMEOUT                    10240
  39 #define NAND_ECC_BUSY                   0xC
  40 #define NAND_4BITECC_MASK               0x03FF03FF
  41 #define EMIF_NANDFSR_ECC_STATE_MASK     0x00000F00
  42 #define ECC_STATE_NO_ERR                0x0
  43 #define ECC_STATE_TOO_MANY_ERRS         0x1
  44 #define ECC_STATE_ERR_CORR_COMP_P       0x2
  45 #define ECC_STATE_ERR_CORR_COMP_N       0x3
  46
  47 /*
  48  * Exploit the little endianness of the ARM to do multi-byte transfers
  49  * per device read. This can perform over twice as quickly as individual
  50  * byte transfers when buffer alignment is conducive.
  51  *
  52  * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  53  * the address bus. On Davinci EVM platforms this has always been true.
  54  */
  55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  56 {
  57         struct nand_chip *chip = mtd->priv;
  58         const u32 *nand = chip->IO_ADDR_R;
  59
  60         /* Make sure that buf is 32 bit aligned */
  61         if (((int)buf & 0x3) != 0) {
  62                 if (((int)buf & 0x1) != 0) {
  63                         if (len) {
  64                                 *buf = readb(nand);
  65                                 buf += 1;
  66                                 len--;
  67                         }
  68                 }
  69
  70                 if (((int)buf & 0x3) != 0) {
  71                         if (len >= 2) {
  72                                 *(u16 *)buf = readw(nand);
  73                                 buf += 2;
  74                                 len -= 2;
  75                         }
  76                 }
  77         }
  78
  79         /* copy aligned data */
  80         while (len >= 4) {
  81                 *(u32 *)buf = __raw_readl(nand);
  82                 buf += 4;
  83                 len -= 4;
  84         }
  85
  86         /* mop up any remaining bytes */
  87         if (len) {
  88                 if (len >= 2) {
  89                         *(u16 *)buf = readw(nand);
  90                         buf += 2;
  91                         len -= 2;
  92                 }
  93
  94                 if (len)
  95                         *buf = readb(nand);
  96         }
  97 }
  98
  99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 100                                    int len)
 101 {
 102         struct nand_chip *chip = mtd->priv;
 103         const u32 *nand = chip->IO_ADDR_W;
 104
 105         /* Make sure that buf is 32 bit aligned */
 106         if (((int)buf & 0x3) != 0) {
 107                 if (((int)buf & 0x1) != 0) {
 108                         if (len) {
 109                                 writeb(*buf, nand);
 110                                 buf += 1;
 111                                 len--;
 112                         }
 113                 }
 114
 115                 if (((int)buf & 0x3) != 0) {
 116                         if (len >= 2) {
 117                                 writew(*(u16 *)buf, nand);
 118                                 buf += 2;
 119                                 len -= 2;
 120                         }
 121                 }
 122         }
 123
 124         /* copy aligned data */
 125         while (len >= 4) {
 126                 __raw_writel(*(u32 *)buf, nand);
 127                 buf += 4;
 128                 len -= 4;
 129         }
 130
 131         /* mop up any remaining bytes */
 132         if (len) {
 133                 if (len >= 2) {
 134                         writew(*(u16 *)buf, nand);
 135                         buf += 2;
 136                         len -= 2;
 137                 }
 138
 139                 if (len)
 140                         writeb(*buf, nand);
 141         }
 142 }
 143
 144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 145                 unsigned int ctrl)
 146 {
 147         struct          nand_chip *this = mtd->priv;
 148         u_int32_t       IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
 149
 150         if (ctrl & NAND_CTRL_CHANGE) {
 151                 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
 152
 153                 if (ctrl & NAND_CLE)
 154                         IO_ADDR_W |= MASK_CLE;
 155                 if (ctrl & NAND_ALE)
 156                         IO_ADDR_W |= MASK_ALE;
 157                 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 158         }
 159
 160         if (cmd != NAND_CMD_NONE)
 161                 writeb(cmd, IO_ADDR_W);
 162 }
 163
 164 #ifdef CONFIG_SYS_NAND_HW_ECC
 165
 166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
 167 {
 168         u_int32_t       ecc = 0;
 169
 170         ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
 171                                 CONFIG_SYS_NAND_CS - 2]));
 172
 173         return ecc;
 174 }
 175
 176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 177 {
 178         u_int32_t       val;
 179
 180         /* reading the ECC result register resets the ECC calculation */
 181         nand_davinci_readecc(mtd);
 182
 183         val = __raw_readl(&davinci_emif_regs->nandfcr);
 184         val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 185         val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
 186         __raw_writel(val, &davinci_emif_regs->nandfcr);
 187 }
 188
 189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 190                 u_char *ecc_code)
 191 {
 192         u_int32_t               tmp;
 193
 194         tmp = nand_davinci_readecc(mtd);
 195
 196         /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
 197          * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
 198         tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
 199
 200         /* Invert so that erased block ECC is correct */
 201         tmp = ~tmp;
 202
 203         *ecc_code++ = tmp;
 204         *ecc_code++ = tmp >>  8;
 205         *ecc_code++ = tmp >> 16;
 206
 207         /* NOTE:  the above code matches mainline Linux:
 208          *      .PQR.stu ==> ~PQRstu
 209          *
 210          * MontaVista/TI kernels encode those bytes differently, use
 211          * complicated (and allegedly sometimes-wrong) correction code,
 212          * and usually shipped with U-Boot that uses software ECC:
 213          *      .PQR.stu ==> PsQRtu
 214          *
 215          * If you need MV/TI compatible NAND I/O in U-Boot, it should
 216          * be possible to (a) change the mangling above, (b) reverse
 217          * that mangling in nand_davinci_correct_data() below.
 218          */
 219
 220         return 0;
 221 }
 222
 223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 224                 u_char *read_ecc, u_char *calc_ecc)
 225 {
 226         struct nand_chip *this = mtd->priv;
 227         u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
 228                                           (read_ecc[2] << 16);
 229         u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
 230                                           (calc_ecc[2] << 16);
 231         u_int32_t diff = ecc_calc ^ ecc_nand;
 232
 233         if (diff) {
 234                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 235                         /* Correctable error */
 236                         if ((diff >> (12 + 3)) < this->ecc.size) {
 237                                 uint8_t find_bit = 1 << ((diff >> 12) & 7);
 238                                 uint32_t find_byte = diff >> (12 + 3);
 239
 240                                 dat[find_byte] ^= find_bit;
 241                                 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
 242                                          "bit ECC error at offset: %d, bit: "
 243                                          "%d\n", find_byte, find_bit);
 244                                 return 1;
 245                         } else {
 246                                 return -1;
 247                         }
 248                 } else if (!(diff & (diff - 1))) {
 249                         /* Single bit ECC error in the ECC itself,
 250                            nothing to fix */
 251                         MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
 252                                  "ECC.\n");
 253                         return 1;
 254                 } else {
 255                         /* Uncorrectable error */
 256                         MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 257                         return -1;
 258                 }
 259         }
 260         return 0;
 261 }
 262 #endif /* CONFIG_SYS_NAND_HW_ECC */
 263
 264 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 265 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 266 #if defined(CONFIG_SYS_NAND_PAGE_2K)
 267         .eccbytes = 40,
 268 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 269         .eccpos = {
 270                 6,   7,  8,  9, 10,     11, 12, 13, 14, 15,
 271                 22, 23, 24, 25, 26,     27, 28, 29, 30, 31,
 272                 38, 39, 40, 41, 42,     43, 44, 45, 46, 47,
 273                 54, 55, 56, 57, 58,     59, 60, 61, 62, 63,
 274         },
 275         .oobfree = {
 276                 {2, 4}, {16, 6}, {32, 6}, {48, 6},
 277         },
 278 #else
 279         .eccpos = {
 280                 24, 25, 26, 27, 28,
 281                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
 282                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
 283                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
 284                 59, 60, 61, 62, 63,
 285                 },
 286         .oobfree = {
 287                 {.offset = 2, .length = 22, },
 288         },
 289 #endif  /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
 290 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
 291         .eccbytes = 80,
 292         .eccpos = {
 293                 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
 294                 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
 295                 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
 296                 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
 297                 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
 298                 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
 299                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 300                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 301                 },
 302         .oobfree = {
 303                 {.offset = 2, .length = 46, },
 304         },
 305 #endif
 306 };
 307
 308 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 309 {
 310         u32 val;
 311
 312         switch (mode) {
 313         case NAND_ECC_WRITE:
 314         case NAND_ECC_READ:
 315                 /*
 316                  * Start a new ECC calculation for reading or writing 512 bytes
 317                  * of data.
 318                  */
 319                 val = __raw_readl(&davinci_emif_regs->nandfcr);
 320                 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
 321                 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 322                 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
 323                 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
 324                 __raw_writel(val, &davinci_emif_regs->nandfcr);
 325                 break;
 326         case NAND_ECC_READSYN:
 327                 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
 328                 break;
 329         default:
 330                 break;
 331         }
 332 }
 333
 334 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
 335 {
 336         int i;
 337
 338         for (i = 0; i < 4; i++) {
 339                 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
 340                         NAND_4BITECC_MASK;
 341         }
 342
 343         return 0;
 344 }
 345
 346 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
 347                                            const uint8_t *dat,
 348                                            uint8_t *ecc_code)
 349 {
 350         unsigned int hw_4ecc[4];
 351         unsigned int i;
 352
 353         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 354
 355         /*Convert 10 bit ecc value to 8 bit */
 356         for (i = 0; i < 2; i++) {
 357                 unsigned int hw_ecc_low = hw_4ecc[i * 2];
 358                 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
 359
 360                 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
 361                 *ecc_code++ = hw_ecc_low & 0xFF;
 362
 363                 /*
 364                  * Take 2 bits as LSB bits from val1 (count1=0) or val5
 365                  * (count1=1) and 6 bits from val2 (count1=0) or
 366                  * val5 (count1=1)
 367                  */
 368                 *ecc_code++ =
 369                     ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
 370
 371                 /*
 372                  * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
 373                  * 4 bits from val3 (count1=0) or val6 (count1=1)
 374                  */
 375                 *ecc_code++ =
 376                     ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
 377
 378                 /*
 379                  * Take 6 bits from val3(count1=0) or val6 (count1=1) and
 380                  * 2 bits from val4 (count1=0) or  val7 (count1=1)
 381                  */
 382                 *ecc_code++ =
 383                     ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
 384
 385                 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
 386                 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 393                                           uint8_t *read_ecc, uint8_t *calc_ecc)
 394 {
 395         int i;
 396         unsigned int hw_4ecc[4];
 397         unsigned int iserror;
 398         unsigned short *ecc16;
 399         unsigned int numerrors, erroraddress, errorvalue;
 400         u32 val;
 401
 402         /*
 403          * Check for an ECC where all bytes are 0xFF.  If this is the case, we
 404          * will assume we are looking at an erased page and we should ignore
 405          * the ECC.
 406          */
 407         for (i = 0; i < 10; i++) {
 408                 if (read_ecc[i] != 0xFF)
 409                         break;
 410         }
 411         if (i == 10)
 412                 return 0;
 413
 414         /* Convert 8 bit in to 10 bit */
 415         ecc16 = (unsigned short *)&read_ecc[0];
 416
 417         /*
 418          * Write the parity values in the NAND Flash 4-bit ECC Load register.
 419          * Write each parity value one at a time starting from 4bit_ecc_val8
 420          * to 4bit_ecc_val1.
 421          */
 422
 423         /*Take 2 bits from 8th byte and 8 bits from 9th byte */
 424         __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
 425                         &davinci_emif_regs->nand4biteccload);
 426
 427         /* Take 4 bits from 7th byte and 6 bits from 8th byte */
 428         __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
 429                         &davinci_emif_regs->nand4biteccload);
 430
 431         /* Take 6 bits from 6th byte and 4 bits from 7th byte */
 432         __raw_writel((ecc16[3] >> 2) & 0x3FF,
 433                         &davinci_emif_regs->nand4biteccload);
 434
 435         /* Take 8 bits from 5th byte and 2 bits from 6th byte */
 436         __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
 437                         &davinci_emif_regs->nand4biteccload);
 438
 439         /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
 440         __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
 441                         &davinci_emif_regs->nand4biteccload);
 442
 443         /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
 444         __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
 445                         &davinci_emif_regs->nand4biteccload);
 446
 447         /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
 448         __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
 449                         &davinci_emif_regs->nand4biteccload);
 450
 451         /* Take 10 bits from 0th and 1st bytes */
 452         __raw_writel((ecc16[0]) & 0x3FF,
 453                         &davinci_emif_regs->nand4biteccload);
 454
 455         /*
 456          * Perform a dummy read to the EMIF Revision Code and Status register.
 457          * This is required to ensure time for syndrome calculation after
 458          * writing the ECC values in previous step.
 459          */
 460
 461         val = __raw_readl(&davinci_emif_regs->nandfsr);
 462
 463         /*
 464          * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
 465          * A syndrome value of 0 means no bit errors. If the syndrome is
 466          * non-zero then go further otherwise return.
 467          */
 468         nand_davinci_4bit_readecc(mtd, hw_4ecc);
 469
 470         if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
 471                 return 0;
 472
 473         /*
 474          * Clear any previous address calculation by doing a dummy read of an
 475          * error address register.
 476          */
 477         val = __raw_readl(&davinci_emif_regs->nanderradd1);
 478
 479         /*
 480          * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
 481          * register to 1.
 482          */
 483         __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
 484                         &davinci_emif_regs->nandfcr);
 485
 486         /*
 487          * Wait for the corr_state field (bits 8 to 11) in the
 488          * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
 489          * Otherwise ECC calculation has not even begun and the next loop might
 490          * fail because of a false positive!
 491          */
 492         i = NAND_TIMEOUT;
 493         do {
 494                 val = __raw_readl(&davinci_emif_regs->nandfsr);
 495                 val &= 0xc00;
 496                 i--;
 497         } while ((i > 0) && !val);
 498
 499         /*
 500          * Wait for the corr_state field (bits 8 to 11) in the
 501          * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
 502          */
 503         i = NAND_TIMEOUT;
 504         do {
 505                 val = __raw_readl(&davinci_emif_regs->nandfsr);
 506                 val &= 0xc00;
 507                 i--;
 508         } while ((i > 0) && val);
 509
 510         iserror = __raw_readl(&davinci_emif_regs->nandfsr);
 511         iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
 512         iserror = iserror >> 8;
 513
 514         /*
 515          * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
 516          * corrected (five or more errors).  The number of errors
 517          * calculated (err_num field) differs from the number of errors
 518          * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
 519          * correction complete (errors on bit 8 or 9).
 520          * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
 521          * complete (error exists).
 522          */
 523
 524         if (iserror == ECC_STATE_NO_ERR) {
 525                 val = __raw_readl(&davinci_emif_regs->nanderrval1);
 526                 return 0;
 527         } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
 528                 val = __raw_readl(&davinci_emif_regs->nanderrval1);
 529                 return -1;
 530         }
 531
 532         numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
 533                         & 0x3) + 1;
 534
 535         /* Read the error address, error value and correct */
 536         for (i = 0; i < numerrors; i++) {
 537                 if (i > 1) {
 538                         erroraddress =
 539                             ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
 540                               (16 * (i & 1))) & 0x3FF);
 541                         erroraddress = ((512 + 7) - erroraddress);
 542                         errorvalue =
 543                             ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
 544                               (16 * (i & 1))) & 0xFF);
 545                 } else {
 546                         erroraddress =
 547                             ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
 548                               (16 * (i & 1))) & 0x3FF);
 549                         erroraddress = ((512 + 7) - erroraddress);
 550                         errorvalue =
 551                             ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
 552                               (16 * (i & 1))) & 0xFF);
 553                 }
 554                 /* xor the corrupt data with error value */
 555                 if (erroraddress < 512)
 556                         dat[erroraddress] ^= errorvalue;
 557         }
 558
 559         return numerrors;
 560 }
 561 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
 562
 563 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 564 {
 565         return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
 566 }
 567
 568 static void nand_flash_init(void)
 569 {
 570         /* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
 571          * Instead, have your board_init() set EMIF timings, based on its
 572          * knowledge of the clocks and what devices are hooked up ... and
 573          * don't even do that unless no UBL handled it.
 574          */
 575 #ifdef CONFIG_SOC_DM644X
 576         u_int32_t       acfg1 = 0x3ffffffc;
 577
 578         /*------------------------------------------------------------------*
 579          *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
 580          *                                                                  *
 581          *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
 582          *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
 583          *                                                                  *
 584          *------------------------------------------------------------------*/
 585          acfg1 = 0
 586                 | (0 << 31)     /* selectStrobe */
 587                 | (0 << 30)     /* extWait */
 588                 | (1 << 26)     /* writeSetup   10 ns */
 589                 | (3 << 20)     /* writeStrobe  40 ns */
 590                 | (1 << 17)     /* writeHold    10 ns */
 591                 | (1 << 13)     /* readSetup    10 ns */
 592                 | (5 << 7)      /* readStrobe   60 ns */
 593                 | (1 << 4)      /* readHold     10 ns */
 594                 | (3 << 2)      /* turnAround   ?? ns */
 595                 | (0 << 0)      /* asyncSize    8-bit bus */
 596                 ;
 597
 598         __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
 599
 600         /* NAND flash on CS2 */
 601         __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
 602 #endif
 603 }
 604
 605 void davinci_nand_init(struct nand_chip *nand)
 606 {
 607         nand->chip_delay  = 0;
 608 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 609         nand->bbt_options         |= NAND_BBT_USE_FLASH;
 610 #endif
 611 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 612         nand->options     |= NAND_NO_SUBPAGE_WRITE;
 613 #endif
 614 #ifdef CONFIG_SYS_NAND_HW_ECC
 615         nand->ecc.mode = NAND_ECC_HW;
 616         nand->ecc.size = 512;
 617         nand->ecc.bytes = 3;
 618         nand->ecc.strength = 1;
 619         nand->ecc.calculate = nand_davinci_calculate_ecc;
 620         nand->ecc.correct  = nand_davinci_correct_data;
 621         nand->ecc.hwctl  = nand_davinci_enable_hwecc;
 622 #else
 623         nand->ecc.mode = NAND_ECC_SOFT;
 624 #endif /* CONFIG_SYS_NAND_HW_ECC */
 625 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 626         nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
 627         nand->ecc.size = 512;
 628         nand->ecc.bytes = 10;
 629         nand->ecc.strength = 4;
 630         nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
 631         nand->ecc.correct = nand_davinci_4bit_correct_data;
 632         nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
 633         nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
 634 #endif
 635         /* Set address of hardware control function */
 636         nand->cmd_ctrl = nand_davinci_hwcontrol;
 637
 638         nand->read_buf = nand_davinci_read_buf;
 639         nand->write_buf = nand_davinci_write_buf;
 640
 641         nand->dev_ready = nand_davinci_dev_ready;
 642
 643         nand_flash_init();
 644 }
 645
 646 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
 647
 648 int board_nand_init(struct nand_chip *chip)
 649 {
 650         davinci_nand_init(chip);
 651         return 0;
 652 }