2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/bitfield.h>
12 #include <linux/dma-direction.h>
13 #include <linux/errno.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
20 static dma_addr_t
dma_map_single(void *dev
, void *ptr
, size_t size
,
21 enum dma_data_direction dir
)
23 unsigned long addr
= (unsigned long)ptr
;
25 if (dir
== DMA_FROM_DEVICE
)
26 invalidate_dcache_range(addr
, addr
+ size
);
28 flush_dcache_range(addr
, addr
+ size
);
33 static void dma_unmap_single(void *dev
, dma_addr_t addr
, size_t size
,
34 enum dma_data_direction dir
)
36 if (dir
!= DMA_TO_DEVICE
)
37 invalidate_dcache_range(addr
, addr
+ size
);
40 static int dma_mapping_error(void *dev
, dma_addr_t addr
)
45 #define DENALI_NAND_NAME "denali-nand"
47 /* for Indexed Addressing */
48 #define DENALI_INDEXED_CTRL 0x00
49 #define DENALI_INDEXED_DATA 0x10
51 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
52 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
53 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
54 #define DENALI_MAP11 (3 << 26) /* direct controller access */
56 /* MAP11 access cycle type */
57 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
58 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
59 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
62 #define DENALI_ERASE 0x01
64 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
66 #define DENALI_INVALID_BANK -1
67 #define DENALI_NR_BANKS 4
70 * The bus interface clock, clk_x, is phase aligned with the core clock. The
71 * clk_x is an integral multiple N of the core clk. The value N is configured
72 * at IP delivery time, and its available value is 4, 5, or 6. We need to align
73 * to the largest value to make it work with any possible configuration.
75 #define DENALI_CLK_X_MULT 6
77 static inline struct denali_nand_info
*mtd_to_denali(struct mtd_info
*mtd
)
79 return container_of(mtd_to_nand(mtd
), struct denali_nand_info
, nand
);
83 * Direct Addressing - the slave address forms the control information (command
84 * type, bank, block, and page address). The slave data is the actual data to
85 * be transferred. This mode requires 28 bits of address region allocated.
87 static u32
denali_direct_read(struct denali_nand_info
*denali
, u32 addr
)
89 return ioread32(denali
->host
+ addr
);
92 static void denali_direct_write(struct denali_nand_info
*denali
, u32 addr
,
95 iowrite32(data
, denali
->host
+ addr
);
99 * Indexed Addressing - address translation module intervenes in passing the
100 * control information. This mode reduces the required address range. The
101 * control information and transferred data are latched by the registers in
102 * the translation module.
104 static u32
denali_indexed_read(struct denali_nand_info
*denali
, u32 addr
)
106 iowrite32(addr
, denali
->host
+ DENALI_INDEXED_CTRL
);
107 return ioread32(denali
->host
+ DENALI_INDEXED_DATA
);
110 static void denali_indexed_write(struct denali_nand_info
*denali
, u32 addr
,
113 iowrite32(addr
, denali
->host
+ DENALI_INDEXED_CTRL
);
114 iowrite32(data
, denali
->host
+ DENALI_INDEXED_DATA
);
118 * Use the configuration feature register to determine the maximum number of
119 * banks that the hardware supports.
121 static void denali_detect_max_banks(struct denali_nand_info
*denali
)
123 uint32_t features
= ioread32(denali
->reg
+ FEATURES
);
125 denali
->max_banks
= 1 << FIELD_GET(FEATURES__N_BANKS
, features
);
127 /* the encoding changed from rev 5.0 to 5.1 */
128 if (denali
->revision
< 0x0501)
129 denali
->max_banks
<<= 1;
132 static void __maybe_unused
denali_enable_irq(struct denali_nand_info
*denali
)
136 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
137 iowrite32(U32_MAX
, denali
->reg
+ INTR_EN(i
));
138 iowrite32(GLOBAL_INT_EN_FLAG
, denali
->reg
+ GLOBAL_INT_ENABLE
);
141 static void __maybe_unused
denali_disable_irq(struct denali_nand_info
*denali
)
145 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
146 iowrite32(0, denali
->reg
+ INTR_EN(i
));
147 iowrite32(0, denali
->reg
+ GLOBAL_INT_ENABLE
);
150 static void denali_clear_irq(struct denali_nand_info
*denali
,
151 int bank
, uint32_t irq_status
)
153 /* write one to clear bits */
154 iowrite32(irq_status
, denali
->reg
+ INTR_STATUS(bank
));
157 static void denali_clear_irq_all(struct denali_nand_info
*denali
)
161 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
162 denali_clear_irq(denali
, i
, U32_MAX
);
165 static void __denali_check_irq(struct denali_nand_info
*denali
)
170 for (i
= 0; i
< DENALI_NR_BANKS
; i
++) {
171 irq_status
= ioread32(denali
->reg
+ INTR_STATUS(i
));
172 denali_clear_irq(denali
, i
, irq_status
);
174 if (i
!= denali
->active_bank
)
177 denali
->irq_status
|= irq_status
;
181 static void denali_reset_irq(struct denali_nand_info
*denali
)
183 denali
->irq_status
= 0;
184 denali
->irq_mask
= 0;
187 static uint32_t denali_wait_for_irq(struct denali_nand_info
*denali
,
190 unsigned long time_left
= 1000000;
193 __denali_check_irq(denali
);
195 if (irq_mask
& denali
->irq_status
)
196 return denali
->irq_status
;
202 dev_err(denali
->dev
, "timeout while waiting for irq 0x%x\n",
207 return denali
->irq_status
;
210 static uint32_t denali_check_irq(struct denali_nand_info
*denali
)
212 __denali_check_irq(denali
);
214 return denali
->irq_status
;
217 static void denali_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
219 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
220 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
223 for (i
= 0; i
< len
; i
++)
224 buf
[i
] = denali
->host_read(denali
, addr
);
227 static void denali_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
229 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
230 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
233 for (i
= 0; i
< len
; i
++)
234 denali
->host_write(denali
, addr
, buf
[i
]);
237 static void denali_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
239 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
240 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
241 uint16_t *buf16
= (uint16_t *)buf
;
244 for (i
= 0; i
< len
/ 2; i
++)
245 buf16
[i
] = denali
->host_read(denali
, addr
);
248 static void denali_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
,
251 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
252 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
253 const uint16_t *buf16
= (const uint16_t *)buf
;
256 for (i
= 0; i
< len
/ 2; i
++)
257 denali
->host_write(denali
, addr
, buf16
[i
]);
260 static uint8_t denali_read_byte(struct mtd_info
*mtd
)
264 denali_read_buf(mtd
, &byte
, 1);
269 static void denali_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
271 denali_write_buf(mtd
, &byte
, 1);
274 static uint16_t denali_read_word(struct mtd_info
*mtd
)
278 denali_read_buf16(mtd
, (uint8_t *)&word
, 2);
283 static void denali_cmd_ctrl(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
)
285 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
289 type
= DENALI_MAP11_CMD
;
290 else if (ctrl
& NAND_ALE
)
291 type
= DENALI_MAP11_ADDR
;
296 * Some commands are followed by chip->dev_ready or chip->waitfunc.
297 * irq_status must be cleared here to catch the R/B# interrupt later.
299 if (ctrl
& NAND_CTRL_CHANGE
)
300 denali_reset_irq(denali
);
302 denali
->host_write(denali
, DENALI_BANK(denali
) | type
, dat
);
305 static int denali_dev_ready(struct mtd_info
*mtd
)
307 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
309 return !!(denali_check_irq(denali
) & INTR__INT_ACT
);
312 static int denali_check_erased_page(struct mtd_info
*mtd
,
313 struct nand_chip
*chip
, uint8_t *buf
,
314 unsigned long uncor_ecc_flags
,
315 unsigned int max_bitflips
)
317 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
318 int ecc_steps
= chip
->ecc
.steps
;
319 int ecc_size
= chip
->ecc
.size
;
320 int ecc_bytes
= chip
->ecc
.bytes
;
323 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
328 for (i
= 0; i
< ecc_steps
; i
++) {
329 if (!(uncor_ecc_flags
& BIT(i
)))
332 stat
= nand_check_erased_ecc_chunk(buf
, ecc_size
,
337 mtd
->ecc_stats
.failed
++;
339 mtd
->ecc_stats
.corrected
+= stat
;
340 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
344 ecc_code
+= ecc_bytes
;
350 static int denali_hw_ecc_fixup(struct mtd_info
*mtd
,
351 struct denali_nand_info
*denali
,
352 unsigned long *uncor_ecc_flags
)
354 struct nand_chip
*chip
= mtd_to_nand(mtd
);
355 int bank
= denali
->active_bank
;
357 unsigned int max_bitflips
;
359 ecc_cor
= ioread32(denali
->reg
+ ECC_COR_INFO(bank
));
360 ecc_cor
>>= ECC_COR_INFO__SHIFT(bank
);
362 if (ecc_cor
& ECC_COR_INFO__UNCOR_ERR
) {
364 * This flag is set when uncorrectable error occurs at least in
365 * one ECC sector. We can not know "how many sectors", or
366 * "which sector(s)". We need erase-page check for all sectors.
368 *uncor_ecc_flags
= GENMASK(chip
->ecc
.steps
- 1, 0);
372 max_bitflips
= FIELD_GET(ECC_COR_INFO__MAX_ERRORS
, ecc_cor
);
375 * The register holds the maximum of per-sector corrected bitflips.
376 * This is suitable for the return value of the ->read_page() callback.
377 * Unfortunately, we can not know the total number of corrected bits in
378 * the page. Increase the stats by max_bitflips. (compromised solution)
380 mtd
->ecc_stats
.corrected
+= max_bitflips
;
385 static int denali_sw_ecc_fixup(struct mtd_info
*mtd
,
386 struct denali_nand_info
*denali
,
387 unsigned long *uncor_ecc_flags
, uint8_t *buf
)
389 unsigned int ecc_size
= denali
->nand
.ecc
.size
;
390 unsigned int bitflips
= 0;
391 unsigned int max_bitflips
= 0;
392 uint32_t err_addr
, err_cor_info
;
393 unsigned int err_byte
, err_sector
, err_device
;
394 uint8_t err_cor_value
;
395 unsigned int prev_sector
= 0;
398 denali_reset_irq(denali
);
401 err_addr
= ioread32(denali
->reg
+ ECC_ERROR_ADDRESS
);
402 err_sector
= FIELD_GET(ECC_ERROR_ADDRESS__SECTOR
, err_addr
);
403 err_byte
= FIELD_GET(ECC_ERROR_ADDRESS__OFFSET
, err_addr
);
405 err_cor_info
= ioread32(denali
->reg
+ ERR_CORRECTION_INFO
);
406 err_cor_value
= FIELD_GET(ERR_CORRECTION_INFO__BYTE
,
408 err_device
= FIELD_GET(ERR_CORRECTION_INFO__DEVICE
,
411 /* reset the bitflip counter when crossing ECC sector */
412 if (err_sector
!= prev_sector
)
415 if (err_cor_info
& ERR_CORRECTION_INFO__UNCOR
) {
417 * Check later if this is a real ECC error, or
420 *uncor_ecc_flags
|= BIT(err_sector
);
421 } else if (err_byte
< ecc_size
) {
423 * If err_byte is larger than ecc_size, means error
424 * happened in OOB, so we ignore it. It's no need for
425 * us to correct it err_device is represented the NAND
426 * error bits are happened in if there are more than
427 * one NAND connected.
430 unsigned int flips_in_byte
;
432 offset
= (err_sector
* ecc_size
+ err_byte
) *
433 denali
->devs_per_cs
+ err_device
;
435 /* correct the ECC error */
436 flips_in_byte
= hweight8(buf
[offset
] ^ err_cor_value
);
437 buf
[offset
] ^= err_cor_value
;
438 mtd
->ecc_stats
.corrected
+= flips_in_byte
;
439 bitflips
+= flips_in_byte
;
441 max_bitflips
= max(max_bitflips
, bitflips
);
444 prev_sector
= err_sector
;
445 } while (!(err_cor_info
& ERR_CORRECTION_INFO__LAST_ERR
));
448 * Once handle all ECC errors, controller will trigger an
449 * ECC_TRANSACTION_DONE interrupt.
451 irq_status
= denali_wait_for_irq(denali
, INTR__ECC_TRANSACTION_DONE
);
452 if (!(irq_status
& INTR__ECC_TRANSACTION_DONE
))
458 static void denali_setup_dma64(struct denali_nand_info
*denali
,
459 dma_addr_t dma_addr
, int page
, int write
)
462 const int page_count
= 1;
464 mode
= DENALI_MAP10
| DENALI_BANK(denali
) | page
;
466 /* DMA is a three step process */
469 * 1. setup transfer type, interrupt when complete,
470 * burst len = 64 bytes, the number of pages
472 denali
->host_write(denali
, mode
,
473 0x01002000 | (64 << 16) | (write
<< 8) | page_count
);
475 /* 2. set memory low address */
476 denali
->host_write(denali
, mode
, lower_32_bits(dma_addr
));
478 /* 3. set memory high address */
479 denali
->host_write(denali
, mode
, upper_32_bits(dma_addr
));
482 static void denali_setup_dma32(struct denali_nand_info
*denali
,
483 dma_addr_t dma_addr
, int page
, int write
)
486 const int page_count
= 1;
488 mode
= DENALI_MAP10
| DENALI_BANK(denali
);
490 /* DMA is a four step process */
492 /* 1. setup transfer type and # of pages */
493 denali
->host_write(denali
, mode
| page
,
494 0x2000 | (write
<< 8) | page_count
);
496 /* 2. set memory high address bits 23:8 */
497 denali
->host_write(denali
, mode
| ((dma_addr
>> 16) << 8), 0x2200);
499 /* 3. set memory low address bits 23:8 */
500 denali
->host_write(denali
, mode
| ((dma_addr
& 0xffff) << 8), 0x2300);
502 /* 4. interrupt when complete, burst len = 64 bytes */
503 denali
->host_write(denali
, mode
| 0x14000, 0x2400);
506 static int denali_pio_read(struct denali_nand_info
*denali
, void *buf
,
507 size_t size
, int page
, int raw
)
509 u32 addr
= DENALI_MAP01
| DENALI_BANK(denali
) | page
;
510 uint32_t *buf32
= (uint32_t *)buf
;
511 uint32_t irq_status
, ecc_err_mask
;
514 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
515 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
517 ecc_err_mask
= INTR__ECC_ERR
;
519 denali_reset_irq(denali
);
521 for (i
= 0; i
< size
/ 4; i
++)
522 *buf32
++ = denali
->host_read(denali
, addr
);
524 irq_status
= denali_wait_for_irq(denali
, INTR__PAGE_XFER_INC
);
525 if (!(irq_status
& INTR__PAGE_XFER_INC
))
528 if (irq_status
& INTR__ERASED_PAGE
)
529 memset(buf
, 0xff, size
);
531 return irq_status
& ecc_err_mask
? -EBADMSG
: 0;
534 static int denali_pio_write(struct denali_nand_info
*denali
,
535 const void *buf
, size_t size
, int page
, int raw
)
537 u32 addr
= DENALI_MAP01
| DENALI_BANK(denali
) | page
;
538 const uint32_t *buf32
= (uint32_t *)buf
;
542 denali_reset_irq(denali
);
544 for (i
= 0; i
< size
/ 4; i
++)
545 denali
->host_write(denali
, addr
, *buf32
++);
547 irq_status
= denali_wait_for_irq(denali
,
548 INTR__PROGRAM_COMP
| INTR__PROGRAM_FAIL
);
549 if (!(irq_status
& INTR__PROGRAM_COMP
))
555 static int denali_pio_xfer(struct denali_nand_info
*denali
, void *buf
,
556 size_t size
, int page
, int raw
, int write
)
559 return denali_pio_write(denali
, buf
, size
, page
, raw
);
561 return denali_pio_read(denali
, buf
, size
, page
, raw
);
564 static int denali_dma_xfer(struct denali_nand_info
*denali
, void *buf
,
565 size_t size
, int page
, int raw
, int write
)
568 uint32_t irq_mask
, irq_status
, ecc_err_mask
;
569 enum dma_data_direction dir
= write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
572 dma_addr
= dma_map_single(denali
->dev
, buf
, size
, dir
);
573 if (dma_mapping_error(denali
->dev
, dma_addr
)) {
574 dev_dbg(denali
->dev
, "Failed to DMA-map buffer. Trying PIO.\n");
575 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
580 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
581 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
582 * when the page program is completed.
584 irq_mask
= INTR__DMA_CMD_COMP
| INTR__PROGRAM_FAIL
;
586 } else if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
) {
587 irq_mask
= INTR__DMA_CMD_COMP
;
588 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
590 irq_mask
= INTR__DMA_CMD_COMP
;
591 ecc_err_mask
= INTR__ECC_ERR
;
594 iowrite32(DMA_ENABLE__FLAG
, denali
->reg
+ DMA_ENABLE
);
596 denali_reset_irq(denali
);
597 denali
->setup_dma(denali
, dma_addr
, page
, write
);
599 irq_status
= denali_wait_for_irq(denali
, irq_mask
);
600 if (!(irq_status
& INTR__DMA_CMD_COMP
))
602 else if (irq_status
& ecc_err_mask
)
605 iowrite32(0, denali
->reg
+ DMA_ENABLE
);
607 dma_unmap_single(denali
->dev
, dma_addr
, size
, dir
);
609 if (irq_status
& INTR__ERASED_PAGE
)
610 memset(buf
, 0xff, size
);
615 static int denali_data_xfer(struct denali_nand_info
*denali
, void *buf
,
616 size_t size
, int page
, int raw
, int write
)
618 iowrite32(raw
? 0 : ECC_ENABLE__FLAG
, denali
->reg
+ ECC_ENABLE
);
619 iowrite32(raw
? TRANSFER_SPARE_REG__FLAG
: 0,
620 denali
->reg
+ TRANSFER_SPARE_REG
);
622 if (denali
->dma_avail
)
623 return denali_dma_xfer(denali
, buf
, size
, page
, raw
, write
);
625 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
628 static void denali_oob_xfer(struct mtd_info
*mtd
, struct nand_chip
*chip
,
631 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
632 unsigned int start_cmd
= write
? NAND_CMD_SEQIN
: NAND_CMD_READ0
;
633 unsigned int rnd_cmd
= write
? NAND_CMD_RNDIN
: NAND_CMD_RNDOUT
;
634 int writesize
= mtd
->writesize
;
635 int oobsize
= mtd
->oobsize
;
636 uint8_t *bufpoi
= chip
->oob_poi
;
637 int ecc_steps
= chip
->ecc
.steps
;
638 int ecc_size
= chip
->ecc
.size
;
639 int ecc_bytes
= chip
->ecc
.bytes
;
640 int oob_skip
= denali
->oob_skip_bytes
;
641 size_t size
= writesize
+ oobsize
;
644 /* BBM at the beginning of the OOB area */
645 chip
->cmdfunc(mtd
, start_cmd
, writesize
, page
);
647 chip
->write_buf(mtd
, bufpoi
, oob_skip
);
649 chip
->read_buf(mtd
, bufpoi
, oob_skip
);
653 for (i
= 0; i
< ecc_steps
; i
++) {
654 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
657 if (pos
>= writesize
)
659 else if (pos
+ len
> writesize
)
660 len
= writesize
- pos
;
662 chip
->cmdfunc(mtd
, rnd_cmd
, pos
, -1);
664 chip
->write_buf(mtd
, bufpoi
, len
);
666 chip
->read_buf(mtd
, bufpoi
, len
);
668 if (len
< ecc_bytes
) {
669 len
= ecc_bytes
- len
;
670 chip
->cmdfunc(mtd
, rnd_cmd
, writesize
+ oob_skip
, -1);
672 chip
->write_buf(mtd
, bufpoi
, len
);
674 chip
->read_buf(mtd
, bufpoi
, len
);
680 len
= oobsize
- (bufpoi
- chip
->oob_poi
);
681 chip
->cmdfunc(mtd
, rnd_cmd
, size
- len
, -1);
683 chip
->write_buf(mtd
, bufpoi
, len
);
685 chip
->read_buf(mtd
, bufpoi
, len
);
688 static int denali_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
689 uint8_t *buf
, int oob_required
, int page
)
691 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
692 int writesize
= mtd
->writesize
;
693 int oobsize
= mtd
->oobsize
;
694 int ecc_steps
= chip
->ecc
.steps
;
695 int ecc_size
= chip
->ecc
.size
;
696 int ecc_bytes
= chip
->ecc
.bytes
;
697 void *tmp_buf
= denali
->buf
;
698 int oob_skip
= denali
->oob_skip_bytes
;
699 size_t size
= writesize
+ oobsize
;
700 int ret
, i
, pos
, len
;
702 ret
= denali_data_xfer(denali
, tmp_buf
, size
, page
, 1, 0);
706 /* Arrange the buffer for syndrome payload/ecc layout */
708 for (i
= 0; i
< ecc_steps
; i
++) {
709 pos
= i
* (ecc_size
+ ecc_bytes
);
712 if (pos
>= writesize
)
714 else if (pos
+ len
> writesize
)
715 len
= writesize
- pos
;
717 memcpy(buf
, tmp_buf
+ pos
, len
);
719 if (len
< ecc_size
) {
720 len
= ecc_size
- len
;
721 memcpy(buf
, tmp_buf
+ writesize
+ oob_skip
,
729 uint8_t *oob
= chip
->oob_poi
;
731 /* BBM at the beginning of the OOB area */
732 memcpy(oob
, tmp_buf
+ writesize
, oob_skip
);
736 for (i
= 0; i
< ecc_steps
; i
++) {
737 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
740 if (pos
>= writesize
)
742 else if (pos
+ len
> writesize
)
743 len
= writesize
- pos
;
745 memcpy(oob
, tmp_buf
+ pos
, len
);
747 if (len
< ecc_bytes
) {
748 len
= ecc_bytes
- len
;
749 memcpy(oob
, tmp_buf
+ writesize
+ oob_skip
,
756 len
= oobsize
- (oob
- chip
->oob_poi
);
757 memcpy(oob
, tmp_buf
+ size
- len
, len
);
763 static int denali_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
766 denali_oob_xfer(mtd
, chip
, page
, 0);
771 static int denali_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
774 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
777 denali_reset_irq(denali
);
779 denali_oob_xfer(mtd
, chip
, page
, 1);
781 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
782 status
= chip
->waitfunc(mtd
, chip
);
784 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
787 static int denali_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
788 uint8_t *buf
, int oob_required
, int page
)
790 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
791 unsigned long uncor_ecc_flags
= 0;
795 ret
= denali_data_xfer(denali
, buf
, mtd
->writesize
, page
, 0, 0);
796 if (ret
&& ret
!= -EBADMSG
)
799 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
800 stat
= denali_hw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
);
801 else if (ret
== -EBADMSG
)
802 stat
= denali_sw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
, buf
);
807 if (uncor_ecc_flags
) {
808 ret
= denali_read_oob(mtd
, chip
, page
);
812 stat
= denali_check_erased_page(mtd
, chip
, buf
,
813 uncor_ecc_flags
, stat
);
819 static int denali_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
820 const uint8_t *buf
, int oob_required
, int page
)
822 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
823 int writesize
= mtd
->writesize
;
824 int oobsize
= mtd
->oobsize
;
825 int ecc_steps
= chip
->ecc
.steps
;
826 int ecc_size
= chip
->ecc
.size
;
827 int ecc_bytes
= chip
->ecc
.bytes
;
828 void *tmp_buf
= denali
->buf
;
829 int oob_skip
= denali
->oob_skip_bytes
;
830 size_t size
= writesize
+ oobsize
;
834 * Fill the buffer with 0xff first except the full page transfer.
835 * This simplifies the logic.
837 if (!buf
|| !oob_required
)
838 memset(tmp_buf
, 0xff, size
);
840 /* Arrange the buffer for syndrome payload/ecc layout */
842 for (i
= 0; i
< ecc_steps
; i
++) {
843 pos
= i
* (ecc_size
+ ecc_bytes
);
846 if (pos
>= writesize
)
848 else if (pos
+ len
> writesize
)
849 len
= writesize
- pos
;
851 memcpy(tmp_buf
+ pos
, buf
, len
);
853 if (len
< ecc_size
) {
854 len
= ecc_size
- len
;
855 memcpy(tmp_buf
+ writesize
+ oob_skip
, buf
,
863 const uint8_t *oob
= chip
->oob_poi
;
865 /* BBM at the beginning of the OOB area */
866 memcpy(tmp_buf
+ writesize
, oob
, oob_skip
);
870 for (i
= 0; i
< ecc_steps
; i
++) {
871 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
874 if (pos
>= writesize
)
876 else if (pos
+ len
> writesize
)
877 len
= writesize
- pos
;
879 memcpy(tmp_buf
+ pos
, oob
, len
);
881 if (len
< ecc_bytes
) {
882 len
= ecc_bytes
- len
;
883 memcpy(tmp_buf
+ writesize
+ oob_skip
, oob
,
890 len
= oobsize
- (oob
- chip
->oob_poi
);
891 memcpy(tmp_buf
+ size
- len
, oob
, len
);
894 return denali_data_xfer(denali
, tmp_buf
, size
, page
, 1, 1);
897 static int denali_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
898 const uint8_t *buf
, int oob_required
, int page
)
900 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
902 return denali_data_xfer(denali
, (void *)buf
, mtd
->writesize
,
906 static void denali_select_chip(struct mtd_info
*mtd
, int chip
)
908 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
910 denali
->active_bank
= chip
;
913 static int denali_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*chip
)
915 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
918 /* R/B# pin transitioned from low to high? */
919 irq_status
= denali_wait_for_irq(denali
, INTR__INT_ACT
);
921 return irq_status
& INTR__INT_ACT
? 0 : NAND_STATUS_FAIL
;
924 static int denali_erase(struct mtd_info
*mtd
, int page
)
926 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
929 denali_reset_irq(denali
);
931 denali
->host_write(denali
, DENALI_MAP10
| DENALI_BANK(denali
) | page
,
934 /* wait for erase to complete or failure to occur */
935 irq_status
= denali_wait_for_irq(denali
,
936 INTR__ERASE_COMP
| INTR__ERASE_FAIL
);
938 return irq_status
& INTR__ERASE_COMP
? 0 : NAND_STATUS_FAIL
;
941 static int denali_setup_data_interface(struct mtd_info
*mtd
, int chipnr
,
942 const struct nand_data_interface
*conf
)
944 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
945 const struct nand_sdr_timings
*timings
;
947 int acc_clks
, re_2_we
, re_2_re
, we_2_re
, addr_2_data
;
948 int rdwr_en_lo
, rdwr_en_hi
, rdwr_en_lo_hi
, cs_setup
;
949 int addr_2_data_mask
;
952 timings
= nand_get_sdr_timings(conf
);
954 return PTR_ERR(timings
);
956 /* clk_x period in picoseconds */
957 t_clk
= DIV_ROUND_DOWN_ULL(1000000000000ULL, denali
->clk_x_rate
);
961 if (chipnr
== NAND_DATA_IFACE_CHECK_ONLY
)
964 /* tREA -> ACC_CLKS */
965 acc_clks
= DIV_ROUND_UP(timings
->tREA_max
, t_clk
);
966 acc_clks
= min_t(int, acc_clks
, ACC_CLKS__VALUE
);
968 tmp
= ioread32(denali
->reg
+ ACC_CLKS
);
969 tmp
&= ~ACC_CLKS__VALUE
;
970 tmp
|= FIELD_PREP(ACC_CLKS__VALUE
, acc_clks
);
971 iowrite32(tmp
, denali
->reg
+ ACC_CLKS
);
973 /* tRWH -> RE_2_WE */
974 re_2_we
= DIV_ROUND_UP(timings
->tRHW_min
, t_clk
);
975 re_2_we
= min_t(int, re_2_we
, RE_2_WE__VALUE
);
977 tmp
= ioread32(denali
->reg
+ RE_2_WE
);
978 tmp
&= ~RE_2_WE__VALUE
;
979 tmp
|= FIELD_PREP(RE_2_WE__VALUE
, re_2_we
);
980 iowrite32(tmp
, denali
->reg
+ RE_2_WE
);
982 /* tRHZ -> RE_2_RE */
983 re_2_re
= DIV_ROUND_UP(timings
->tRHZ_max
, t_clk
);
984 re_2_re
= min_t(int, re_2_re
, RE_2_RE__VALUE
);
986 tmp
= ioread32(denali
->reg
+ RE_2_RE
);
987 tmp
&= ~RE_2_RE__VALUE
;
988 tmp
|= FIELD_PREP(RE_2_RE__VALUE
, re_2_re
);
989 iowrite32(tmp
, denali
->reg
+ RE_2_RE
);
992 * tCCS, tWHR -> WE_2_RE
994 * With WE_2_RE properly set, the Denali controller automatically takes
995 * care of the delay; the driver need not set NAND_WAIT_TCCS.
997 we_2_re
= DIV_ROUND_UP(max(timings
->tCCS_min
, timings
->tWHR_min
),
999 we_2_re
= min_t(int, we_2_re
, TWHR2_AND_WE_2_RE__WE_2_RE
);
1001 tmp
= ioread32(denali
->reg
+ TWHR2_AND_WE_2_RE
);
1002 tmp
&= ~TWHR2_AND_WE_2_RE__WE_2_RE
;
1003 tmp
|= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE
, we_2_re
);
1004 iowrite32(tmp
, denali
->reg
+ TWHR2_AND_WE_2_RE
);
1006 /* tADL -> ADDR_2_DATA */
1008 /* for older versions, ADDR_2_DATA is only 6 bit wide */
1009 addr_2_data_mask
= TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
;
1010 if (denali
->revision
< 0x0501)
1011 addr_2_data_mask
>>= 1;
1013 addr_2_data
= DIV_ROUND_UP(timings
->tADL_min
, t_clk
);
1014 addr_2_data
= min_t(int, addr_2_data
, addr_2_data_mask
);
1016 tmp
= ioread32(denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1017 tmp
&= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
;
1018 tmp
|= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
, addr_2_data
);
1019 iowrite32(tmp
, denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1021 /* tREH, tWH -> RDWR_EN_HI_CNT */
1022 rdwr_en_hi
= DIV_ROUND_UP(max(timings
->tREH_min
, timings
->tWH_min
),
1024 rdwr_en_hi
= min_t(int, rdwr_en_hi
, RDWR_EN_HI_CNT__VALUE
);
1026 tmp
= ioread32(denali
->reg
+ RDWR_EN_HI_CNT
);
1027 tmp
&= ~RDWR_EN_HI_CNT__VALUE
;
1028 tmp
|= FIELD_PREP(RDWR_EN_HI_CNT__VALUE
, rdwr_en_hi
);
1029 iowrite32(tmp
, denali
->reg
+ RDWR_EN_HI_CNT
);
1031 /* tRP, tWP -> RDWR_EN_LO_CNT */
1032 rdwr_en_lo
= DIV_ROUND_UP(max(timings
->tRP_min
, timings
->tWP_min
),
1034 rdwr_en_lo_hi
= DIV_ROUND_UP(max(timings
->tRC_min
, timings
->tWC_min
),
1036 rdwr_en_lo_hi
= max(rdwr_en_lo_hi
, DENALI_CLK_X_MULT
);
1037 rdwr_en_lo
= max(rdwr_en_lo
, rdwr_en_lo_hi
- rdwr_en_hi
);
1038 rdwr_en_lo
= min_t(int, rdwr_en_lo
, RDWR_EN_LO_CNT__VALUE
);
1040 tmp
= ioread32(denali
->reg
+ RDWR_EN_LO_CNT
);
1041 tmp
&= ~RDWR_EN_LO_CNT__VALUE
;
1042 tmp
|= FIELD_PREP(RDWR_EN_LO_CNT__VALUE
, rdwr_en_lo
);
1043 iowrite32(tmp
, denali
->reg
+ RDWR_EN_LO_CNT
);
1045 /* tCS, tCEA -> CS_SETUP_CNT */
1046 cs_setup
= max3((int)DIV_ROUND_UP(timings
->tCS_min
, t_clk
) - rdwr_en_lo
,
1047 (int)DIV_ROUND_UP(timings
->tCEA_max
, t_clk
) - acc_clks
,
1049 cs_setup
= min_t(int, cs_setup
, CS_SETUP_CNT__VALUE
);
1051 tmp
= ioread32(denali
->reg
+ CS_SETUP_CNT
);
1052 tmp
&= ~CS_SETUP_CNT__VALUE
;
1053 tmp
|= FIELD_PREP(CS_SETUP_CNT__VALUE
, cs_setup
);
1054 iowrite32(tmp
, denali
->reg
+ CS_SETUP_CNT
);
1059 static void denali_reset_banks(struct denali_nand_info
*denali
)
1064 for (i
= 0; i
< denali
->max_banks
; i
++) {
1065 denali
->active_bank
= i
;
1067 denali_reset_irq(denali
);
1069 iowrite32(DEVICE_RESET__BANK(i
),
1070 denali
->reg
+ DEVICE_RESET
);
1072 irq_status
= denali_wait_for_irq(denali
,
1073 INTR__RST_COMP
| INTR__INT_ACT
| INTR__TIME_OUT
);
1074 if (!(irq_status
& INTR__INT_ACT
))
1078 dev_dbg(denali
->dev
, "%d chips connected\n", i
);
1079 denali
->max_banks
= i
;
1082 static void denali_hw_init(struct denali_nand_info
*denali
)
1085 * The REVISION register may not be reliable. Platforms are allowed to
1088 if (!denali
->revision
)
1089 denali
->revision
= swab16(ioread32(denali
->reg
+ REVISION
));
1092 * tell driver how many bit controller will skip before writing
1093 * ECC code in OOB. This is normally used for bad block marker
1095 denali
->oob_skip_bytes
= CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES
;
1096 iowrite32(denali
->oob_skip_bytes
, denali
->reg
+ SPARE_AREA_SKIP_BYTES
);
1097 denali_detect_max_banks(denali
);
1098 iowrite32(0x0F, denali
->reg
+ RB_PIN_ENABLED
);
1099 iowrite32(CHIP_EN_DONT_CARE__FLAG
, denali
->reg
+ CHIP_ENABLE_DONT_CARE
);
1101 iowrite32(0xffff, denali
->reg
+ SPARE_AREA_MARKER
);
1104 int denali_calc_ecc_bytes(int step_size
, int strength
)
1106 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1107 return DIV_ROUND_UP(strength
* fls(step_size
* 8), 16) * 2;
1109 EXPORT_SYMBOL(denali_calc_ecc_bytes
);
1111 static int denali_ecc_setup(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1112 struct denali_nand_info
*denali
)
1114 int oobavail
= mtd
->oobsize
- denali
->oob_skip_bytes
;
1118 * If .size and .strength are already set (usually by DT),
1119 * check if they are supported by this controller.
1121 if (chip
->ecc
.size
&& chip
->ecc
.strength
)
1122 return nand_check_ecc_caps(chip
, denali
->ecc_caps
, oobavail
);
1125 * We want .size and .strength closest to the chip's requirement
1126 * unless NAND_ECC_MAXIMIZE is requested.
1128 if (!(chip
->ecc
.options
& NAND_ECC_MAXIMIZE
)) {
1129 ret
= nand_match_ecc_req(chip
, denali
->ecc_caps
, oobavail
);
1134 /* Max ECC strength is the last thing we can do */
1135 return nand_maximize_ecc(chip
, denali
->ecc_caps
, oobavail
);
1138 static struct nand_ecclayout nand_oob
;
1140 static int denali_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1141 struct mtd_oob_region
*oobregion
)
1143 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1144 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1149 oobregion
->offset
= denali
->oob_skip_bytes
;
1150 oobregion
->length
= chip
->ecc
.total
;
1155 static int denali_ooblayout_free(struct mtd_info
*mtd
, int section
,
1156 struct mtd_oob_region
*oobregion
)
1158 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1159 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1164 oobregion
->offset
= chip
->ecc
.total
+ denali
->oob_skip_bytes
;
1165 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
1170 static const struct mtd_ooblayout_ops denali_ooblayout_ops
= {
1171 .ecc
= denali_ooblayout_ecc
,
1172 .free
= denali_ooblayout_free
,
1175 static int denali_multidev_fixup(struct denali_nand_info
*denali
)
1177 struct nand_chip
*chip
= &denali
->nand
;
1178 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1181 * Support for multi device:
1182 * When the IP configuration is x16 capable and two x8 chips are
1183 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1184 * In this case, the core framework knows nothing about this fact,
1185 * so we should tell it the _logical_ pagesize and anything necessary.
1187 denali
->devs_per_cs
= ioread32(denali
->reg
+ DEVICES_CONNECTED
);
1190 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1191 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1193 if (denali
->devs_per_cs
== 0) {
1194 denali
->devs_per_cs
= 1;
1195 iowrite32(1, denali
->reg
+ DEVICES_CONNECTED
);
1198 if (denali
->devs_per_cs
== 1)
1201 if (denali
->devs_per_cs
!= 2) {
1202 dev_err(denali
->dev
, "unsupported number of devices %d\n",
1203 denali
->devs_per_cs
);
1207 /* 2 chips in parallel */
1209 mtd
->erasesize
<<= 1;
1210 mtd
->writesize
<<= 1;
1212 chip
->chipsize
<<= 1;
1213 chip
->page_shift
+= 1;
1214 chip
->phys_erase_shift
+= 1;
1215 chip
->bbt_erase_shift
+= 1;
1216 chip
->chip_shift
+= 1;
1217 chip
->pagemask
<<= 1;
1218 chip
->ecc
.size
<<= 1;
1219 chip
->ecc
.bytes
<<= 1;
1220 chip
->ecc
.strength
<<= 1;
1221 denali
->oob_skip_bytes
<<= 1;
1226 int denali_init(struct denali_nand_info
*denali
)
1228 struct nand_chip
*chip
= &denali
->nand
;
1229 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1230 u32 features
= ioread32(denali
->reg
+ FEATURES
);
1233 denali_hw_init(denali
);
1235 denali_clear_irq_all(denali
);
1237 denali_reset_banks(denali
);
1239 denali
->active_bank
= DENALI_INVALID_BANK
;
1241 chip
->flash_node
= dev_of_offset(denali
->dev
);
1242 /* Fallback to the default name if DT did not give "label" property */
1244 mtd
->name
= "denali-nand";
1246 chip
->select_chip
= denali_select_chip
;
1247 chip
->read_byte
= denali_read_byte
;
1248 chip
->write_byte
= denali_write_byte
;
1249 chip
->read_word
= denali_read_word
;
1250 chip
->cmd_ctrl
= denali_cmd_ctrl
;
1251 chip
->dev_ready
= denali_dev_ready
;
1252 chip
->waitfunc
= denali_waitfunc
;
1254 if (features
& FEATURES__INDEX_ADDR
) {
1255 denali
->host_read
= denali_indexed_read
;
1256 denali
->host_write
= denali_indexed_write
;
1258 denali
->host_read
= denali_direct_read
;
1259 denali
->host_write
= denali_direct_write
;
1262 /* clk rate info is needed for setup_data_interface */
1263 if (denali
->clk_x_rate
)
1264 chip
->setup_data_interface
= denali_setup_data_interface
;
1266 ret
= nand_scan_ident(mtd
, denali
->max_banks
, NULL
);
1270 if (ioread32(denali
->reg
+ FEATURES
) & FEATURES__DMA
)
1271 denali
->dma_avail
= 1;
1273 if (denali
->dma_avail
) {
1274 chip
->buf_align
= 16;
1275 if (denali
->caps
& DENALI_CAP_DMA_64BIT
)
1276 denali
->setup_dma
= denali_setup_dma64
;
1278 denali
->setup_dma
= denali_setup_dma32
;
1280 chip
->buf_align
= 4;
1283 chip
->options
|= NAND_USE_BOUNCE_BUFFER
;
1284 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1285 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
1286 denali
->nand
.ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1288 /* no subpage writes on denali */
1289 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1291 ret
= denali_ecc_setup(mtd
, chip
, denali
);
1293 dev_err(denali
->dev
, "Failed to setup ECC settings.\n");
1297 dev_dbg(denali
->dev
,
1298 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1299 chip
->ecc
.size
, chip
->ecc
.strength
, chip
->ecc
.bytes
);
1301 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD
, 1) |
1302 FIELD_PREP(ECC_CORRECTION__VALUE
, chip
->ecc
.strength
),
1303 denali
->reg
+ ECC_CORRECTION
);
1304 iowrite32(mtd
->erasesize
/ mtd
->writesize
,
1305 denali
->reg
+ PAGES_PER_BLOCK
);
1306 iowrite32(chip
->options
& NAND_BUSWIDTH_16
? 1 : 0,
1307 denali
->reg
+ DEVICE_WIDTH
);
1308 iowrite32(chip
->options
& NAND_ROW_ADDR_3
? 0 : TWO_ROW_ADDR_CYCLES__FLAG
,
1309 denali
->reg
+ TWO_ROW_ADDR_CYCLES
);
1310 iowrite32(mtd
->writesize
, denali
->reg
+ DEVICE_MAIN_AREA_SIZE
);
1311 iowrite32(mtd
->oobsize
, denali
->reg
+ DEVICE_SPARE_AREA_SIZE
);
1313 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_DATA_BLOCK_SIZE
);
1314 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_LAST_DATA_BLOCK_SIZE
);
1315 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1316 iowrite32(mtd
->writesize
/ chip
->ecc
.size
,
1317 denali
->reg
+ CFG_NUM_DATA_BLOCKS
);
1319 mtd_set_ooblayout(mtd
, &denali_ooblayout_ops
);
1321 nand_oob
.eccbytes
= denali
->nand
.ecc
.bytes
;
1322 denali
->nand
.ecc
.layout
= &nand_oob
;
1324 if (chip
->options
& NAND_BUSWIDTH_16
) {
1325 chip
->read_buf
= denali_read_buf16
;
1326 chip
->write_buf
= denali_write_buf16
;
1328 chip
->read_buf
= denali_read_buf
;
1329 chip
->write_buf
= denali_write_buf
;
1331 chip
->ecc
.options
|= NAND_ECC_CUSTOM_PAGE_ACCESS
;
1332 chip
->ecc
.read_page
= denali_read_page
;
1333 chip
->ecc
.read_page_raw
= denali_read_page_raw
;
1334 chip
->ecc
.write_page
= denali_write_page
;
1335 chip
->ecc
.write_page_raw
= denali_write_page_raw
;
1336 chip
->ecc
.read_oob
= denali_read_oob
;
1337 chip
->ecc
.write_oob
= denali_write_oob
;
1338 chip
->erase
= denali_erase
;
1340 ret
= denali_multidev_fixup(denali
);
1345 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1346 * use devm_kmalloc() because the memory allocated by devm_ does not
1347 * guarantee DMA-safe alignment.
1349 denali
->buf
= kmalloc(mtd
->writesize
+ mtd
->oobsize
, GFP_KERNEL
);
1353 ret
= nand_scan_tail(mtd
);
1357 ret
= nand_register(0, mtd
);
1359 dev_err(denali
->dev
, "Failed to register MTD: %d\n", ret
);