drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   2  *
   3  * Copyright (c) 2006-2008 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <nand.h>
  14
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/nand_ecc.h>
  18
  19 #include <asm/io.h>
  20 #include <asm/errno.h>
  21
  22 #ifdef VERBOSE_DEBUG
  23 #define DEBUG_ELBC
  24 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  25 #else
  26 #define vdbg(format, arg...) do {} while (0)
  27 #endif
  28
  29 /* Can't use plain old DEBUG because the linux mtd
  30  * headers define it as a macro.
  31  */
  32 #ifdef DEBUG_ELBC
  33 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  34 #else
  35 #define dbg(format, arg...) do {} while (0)
  36 #endif
  37
  38 #define MAX_BANKS 8
  39 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  40 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
  41
  42 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  43
  44 struct fsl_elbc_ctrl;
  45
  46 /* mtd information per set */
  47
  48 struct fsl_elbc_mtd {
  49         struct nand_chip chip;
  50         struct fsl_elbc_ctrl *ctrl;
  51
  52         struct device *dev;
  53         int bank;               /* Chip select bank number           */
  54         u8 __iomem *vbase;      /* Chip select base virtual address  */
  55         int page_size;          /* NAND page size (0=512, 1=2048)    */
  56         unsigned int fmr;       /* FCM Flash Mode Register value     */
  57 };
  58
  59 /* overview of the fsl elbc controller */
  60
  61 struct fsl_elbc_ctrl {
  62         struct nand_hw_control controller;
  63         struct fsl_elbc_mtd *chips[MAX_BANKS];
  64
  65         /* device info */
  66         fsl_lbc_t *regs;
  67         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  68         unsigned int page;       /* Last page written to / read from      */
  69         unsigned int read_bytes; /* Number of bytes read during command   */
  70         unsigned int column;     /* Saved column from SEQIN               */
  71         unsigned int index;      /* Pointer to next byte to 'read'        */
  72         unsigned int status;     /* status read from LTESR after last op  */
  73         unsigned int mdr;        /* UPM/FCM Data Register value           */
  74         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  75         unsigned int oob;        /* Non zero if operating on OOB data     */
  76 };
  77
  78 /* These map to the positions used by the FCM hardware ECC generator */
  79
  80 /* Small Page FLASH with FMR[ECCM] = 0 */
  81 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  82         .eccbytes = 3,
  83         .eccpos = {6, 7, 8},
  84         .oobfree = { {0, 5}, {9, 7} },
  85 };
  86
  87 /* Small Page FLASH with FMR[ECCM] = 1 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  89         .eccbytes = 3,
  90         .eccpos = {8, 9, 10},
  91         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  92 };
  93
  94 /* Large Page FLASH with FMR[ECCM] = 0 */
  95 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  96         .eccbytes = 12,
  97         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
  98         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
  99 };
 100
 101 /* Large Page FLASH with FMR[ECCM] = 1 */
 102 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 103         .eccbytes = 12,
 104         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 105         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 106 };
 107
 108 /*
 109  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 110  * 1, so we have to adjust bad block pattern. This pattern should be used for
 111  * x8 chips only. So far hardware does not support x16 chips anyway.
 112  */
 113 static u8 scan_ff_pattern[] = { 0xff, };
 114
 115 static struct nand_bbt_descr largepage_memorybased = {
 116         .options = 0,
 117         .offs = 0,
 118         .len = 1,
 119         .pattern = scan_ff_pattern,
 120 };
 121
 122 /*
 123  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 124  * interfere with ECC positions, that's why we implement our own descriptors.
 125  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 126  */
 127 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 128 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 129
 130 static struct nand_bbt_descr bbt_main_descr = {
 131         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 132                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 133         .offs = 11,
 134         .len = 4,
 135         .veroffs = 15,
 136         .maxblocks = 4,
 137         .pattern = bbt_pattern,
 138 };
 139
 140 static struct nand_bbt_descr bbt_mirror_descr = {
 141         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 142                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 143         .offs = 11,
 144         .len = 4,
 145         .veroffs = 15,
 146         .maxblocks = 4,
 147         .pattern = mirror_pattern,
 148 };
 149
 150 /*=================================*/
 151
 152 /*
 153  * Set up the FCM hardware block and page address fields, and the fcm
 154  * structure addr field to point to the correct FCM buffer in memory
 155  */
 156 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 157 {
 158         struct nand_chip *chip = mtd->priv;
 159         struct fsl_elbc_mtd *priv = chip->priv;
 160         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 161         fsl_lbc_t *lbc = ctrl->regs;
 162         int buf_num;
 163
 164         ctrl->page = page_addr;
 165
 166         if (priv->page_size) {
 167                 out_be32(&lbc->fbar, page_addr >> 6);
 168                 out_be32(&lbc->fpar,
 169                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 170                          (oob ? FPAR_LP_MS : 0) | column);
 171                 buf_num = (page_addr & 1) << 2;
 172         } else {
 173                 out_be32(&lbc->fbar, page_addr >> 5);
 174                 out_be32(&lbc->fpar,
 175                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 176                          (oob ? FPAR_SP_MS : 0) | column);
 177                 buf_num = page_addr & 7;
 178         }
 179
 180         ctrl->addr = priv->vbase + buf_num * 1024;
 181         ctrl->index = column;
 182
 183         /* for OOB data point to the second half of the buffer */
 184         if (oob)
 185                 ctrl->index += priv->page_size ? 2048 : 512;
 186
 187         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 188              "index %x, pes %d ps %d\n",
 189              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 190              chip->phys_erase_shift, chip->page_shift);
 191 }
 192
 193 /*
 194  * execute FCM command and wait for it to complete
 195  */
 196 static int fsl_elbc_run_command(struct mtd_info *mtd)
 197 {
 198         struct nand_chip *chip = mtd->priv;
 199         struct fsl_elbc_mtd *priv = chip->priv;
 200         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 201         fsl_lbc_t *lbc = ctrl->regs;
 202         long long end_tick;
 203         u32 ltesr;
 204
 205         /* Setup the FMR[OP] to execute without write protection */
 206         out_be32(&lbc->fmr, priv->fmr | 3);
 207         if (ctrl->use_mdr)
 208                 out_be32(&lbc->mdr, ctrl->mdr);
 209
 210         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 211              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 212         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 213              "fbcr=%08x bank=%d\n",
 214              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 215              in_be32(&lbc->fbcr), priv->bank);
 216
 217         /* execute special operation */
 218         out_be32(&lbc->lsor, priv->bank);
 219
 220         /* wait for FCM complete flag or timeout */
 221         end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
 222
 223         ltesr = 0;
 224         while (end_tick > get_ticks()) {
 225                 ltesr = in_be32(&lbc->ltesr);
 226                 if (ltesr & LTESR_CC)
 227                         break;
 228         }
 229
 230         ctrl->status = ltesr & LTESR_NAND_MASK;
 231         out_be32(&lbc->ltesr, ctrl->status);
 232         out_be32(&lbc->lteatr, 0);
 233
 234         /* store mdr value in case it was needed */
 235         if (ctrl->use_mdr)
 236                 ctrl->mdr = in_be32(&lbc->mdr);
 237
 238         ctrl->use_mdr = 0;
 239
 240         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 241              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 242
 243         /* returns 0 on success otherwise non-zero) */
 244         return ctrl->status == LTESR_CC ? 0 : -EIO;
 245 }
 246
 247 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 248 {
 249         struct fsl_elbc_mtd *priv = chip->priv;
 250         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 251         fsl_lbc_t *lbc = ctrl->regs;
 252
 253         if (priv->page_size) {
 254                 out_be32(&lbc->fir,
 255                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 256                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 257                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 258                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 259                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 260
 261                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 262                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 263         } else {
 264                 out_be32(&lbc->fir,
 265                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 266                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 267                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 268                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 269
 270                 if (oob)
 271                         out_be32(&lbc->fcr,
 272                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 273                 else
 274                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 275         }
 276 }
 277
 278 /* cmdfunc send commands to the FCM */
 279 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 280                              int column, int page_addr)
 281 {
 282         struct nand_chip *chip = mtd->priv;
 283         struct fsl_elbc_mtd *priv = chip->priv;
 284         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 285         fsl_lbc_t *lbc = ctrl->regs;
 286
 287         ctrl->use_mdr = 0;
 288
 289         /* clear the read buffer */
 290         ctrl->read_bytes = 0;
 291         if (command != NAND_CMD_PAGEPROG)
 292                 ctrl->index = 0;
 293
 294         switch (command) {
 295         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 296         case NAND_CMD_READ1:
 297                 column += 256;
 298
 299         /* fall-through */
 300         case NAND_CMD_READ0:
 301                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 302                      " 0x%x, column: 0x%x.\n", page_addr, column);
 303
 304                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 305                 set_addr(mtd, 0, page_addr, 0);
 306
 307                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 308                 ctrl->index += column;
 309
 310                 fsl_elbc_do_read(chip, 0);
 311                 fsl_elbc_run_command(mtd);
 312                 return;
 313
 314         /* READOOB reads only the OOB because no ECC is performed. */
 315         case NAND_CMD_READOOB:
 316                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 317                      " 0x%x, column: 0x%x.\n", page_addr, column);
 318
 319                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 320                 set_addr(mtd, column, page_addr, 1);
 321
 322                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 323
 324                 fsl_elbc_do_read(chip, 1);
 325                 fsl_elbc_run_command(mtd);
 326
 327                 return;
 328
 329         /* READID must read all 5 possible bytes while CEB is active */
 330         case NAND_CMD_READID:
 331         case NAND_CMD_PARAM:
 332                 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
 333
 334                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 335                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 336                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 337                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
 338                 /*
 339                  * although currently it's 8 bytes for READID, we always read
 340                  * the maximum 256 bytes(for PARAM)
 341                  */
 342                 out_be32(&lbc->fbcr, 256);
 343                 ctrl->read_bytes = 256;
 344                 ctrl->use_mdr = 1;
 345                 ctrl->mdr = column;
 346                 set_addr(mtd, 0, 0, 0);
 347                 fsl_elbc_run_command(mtd);
 348                 return;
 349
 350         /* ERASE1 stores the block and page address */
 351         case NAND_CMD_ERASE1:
 352                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 353                      "page_addr: 0x%x.\n", page_addr);
 354                 set_addr(mtd, 0, page_addr, 0);
 355                 return;
 356
 357         /* ERASE2 uses the block and page address from ERASE1 */
 358         case NAND_CMD_ERASE2:
 359                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 360
 361                 out_be32(&lbc->fir,
 362                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 363                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 364                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 365
 366                 out_be32(&lbc->fcr,
 367                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 368                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 369
 370                 out_be32(&lbc->fbcr, 0);
 371                 ctrl->read_bytes = 0;
 372
 373                 fsl_elbc_run_command(mtd);
 374                 return;
 375
 376         /* SEQIN sets up the addr buffer and all registers except the length */
 377         case NAND_CMD_SEQIN: {
 378                 u32 fcr;
 379                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 380                      "page_addr: 0x%x, column: 0x%x.\n",
 381                      page_addr, column);
 382
 383                 ctrl->column = column;
 384                 ctrl->oob = 0;
 385
 386                 if (priv->page_size) {
 387                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 388                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 389
 390                         out_be32(&lbc->fir,
 391                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 392                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 393                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 394                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 395                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 396                 } else {
 397                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 398                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 399
 400                         out_be32(&lbc->fir,
 401                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 402                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 403                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 404                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 405                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 406                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 407
 408                         if (column >= mtd->writesize) {
 409                                 /* OOB area --> READOOB */
 410                                 column -= mtd->writesize;
 411                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 412                                 ctrl->oob = 1;
 413                         } else if (column < 256) {
 414                                 /* First 256 bytes --> READ0 */
 415                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 416                         } else {
 417                                 /* Second 256 bytes --> READ1 */
 418                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 419                         }
 420                 }
 421
 422                 out_be32(&lbc->fcr, fcr);
 423                 set_addr(mtd, column, page_addr, ctrl->oob);
 424                 return;
 425         }
 426
 427         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 428         case NAND_CMD_PAGEPROG: {
 429                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 430                      "writing %d bytes.\n", ctrl->index);
 431
 432                 /* if the write did not start at 0 or is not a full page
 433                  * then set the exact length, otherwise use a full page
 434                  * write so the HW generates the ECC.
 435                  */
 436                 if (ctrl->oob || ctrl->column != 0 ||
 437                     ctrl->index != mtd->writesize + mtd->oobsize)
 438                         out_be32(&lbc->fbcr, ctrl->index);
 439                 else
 440                         out_be32(&lbc->fbcr, 0);
 441
 442                 fsl_elbc_run_command(mtd);
 443
 444                 return;
 445         }
 446
 447         /* CMD_STATUS must read the status byte while CEB is active */
 448         /* Note - it does not wait for the ready line */
 449         case NAND_CMD_STATUS:
 450                 out_be32(&lbc->fir,
 451                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 452                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 453                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 454                 out_be32(&lbc->fbcr, 1);
 455                 set_addr(mtd, 0, 0, 0);
 456                 ctrl->read_bytes = 1;
 457
 458                 fsl_elbc_run_command(mtd);
 459
 460                 /* The chip always seems to report that it is
 461                  * write-protected, even when it is not.
 462                  */
 463                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 464                 return;
 465
 466         /* RESET without waiting for the ready line */
 467         case NAND_CMD_RESET:
 468                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 469                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 470                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 471                 fsl_elbc_run_command(mtd);
 472                 return;
 473
 474         default:
 475                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 476                         command);
 477         }
 478 }
 479
 480 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 481 {
 482         /* The hardware does not seem to support multiple
 483          * chips per bank.
 484          */
 485 }
 486
 487 /*
 488  * Write buf to the FCM Controller Data Buffer
 489  */
 490 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         struct fsl_elbc_mtd *priv = chip->priv;
 494         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 495         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 496
 497         if (len <= 0) {
 498                 printf("write_buf of %d bytes", len);
 499                 ctrl->status = 0;
 500                 return;
 501         }
 502
 503         if ((unsigned int)len > bufsize - ctrl->index) {
 504                 printf("write_buf beyond end of buffer "
 505                        "(%d requested, %u available)\n",
 506                        len, bufsize - ctrl->index);
 507                 len = bufsize - ctrl->index;
 508         }
 509
 510         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 511         /*
 512          * This is workaround for the weird elbc hangs during nand write,
 513          * Scott Wood says: "...perhaps difference in how long it takes a
 514          * write to make it through the localbus compared to a write to IMMR
 515          * is causing problems, and sync isn't helping for some reason."
 516          * Reading back the last byte helps though.
 517          */
 518         in_8(&ctrl->addr[ctrl->index] + len - 1);
 519
 520         ctrl->index += len;
 521 }
 522
 523 /*
 524  * read a byte from either the FCM hardware buffer if it has any data left
 525  * otherwise issue a command to read a single byte.
 526  */
 527 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 528 {
 529         struct nand_chip *chip = mtd->priv;
 530         struct fsl_elbc_mtd *priv = chip->priv;
 531         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 532
 533         /* If there are still bytes in the FCM, then use the next byte. */
 534         if (ctrl->index < ctrl->read_bytes)
 535                 return in_8(&ctrl->addr[ctrl->index++]);
 536
 537         printf("read_byte beyond end of buffer\n");
 538         return ERR_BYTE;
 539 }
 540
 541 /*
 542  * Read from the FCM Controller Data Buffer
 543  */
 544 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 545 {
 546         struct nand_chip *chip = mtd->priv;
 547         struct fsl_elbc_mtd *priv = chip->priv;
 548         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 549         int avail;
 550
 551         if (len < 0)
 552                 return;
 553
 554         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 555         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 556         ctrl->index += avail;
 557
 558         if (len > avail)
 559                 printf("read_buf beyond end of buffer "
 560                        "(%d requested, %d available)\n",
 561                        len, avail);
 562 }
 563
 564 /*
 565  * Verify buffer against the FCM Controller Data Buffer
 566  */
 567 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
 568                                const u_char *buf, int len)
 569 {
 570         struct nand_chip *chip = mtd->priv;
 571         struct fsl_elbc_mtd *priv = chip->priv;
 572         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 573         int i;
 574
 575         if (len < 0) {
 576                 printf("write_buf of %d bytes", len);
 577                 return -EINVAL;
 578         }
 579
 580         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 581                 printf("verify_buf beyond end of buffer "
 582                        "(%d requested, %u available)\n",
 583                        len, ctrl->read_bytes - ctrl->index);
 584
 585                 ctrl->index = ctrl->read_bytes;
 586                 return -EINVAL;
 587         }
 588
 589         for (i = 0; i < len; i++)
 590                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 591                         break;
 592
 593         ctrl->index += len;
 594         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 595 }
 596
 597 /* This function is called after Program and Erase Operations to
 598  * check for success or failure.
 599  */
 600 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 601 {
 602         struct fsl_elbc_mtd *priv = chip->priv;
 603         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 604         fsl_lbc_t *lbc = ctrl->regs;
 605
 606         if (ctrl->status != LTESR_CC)
 607                 return NAND_STATUS_FAIL;
 608
 609         /* Use READ_STATUS command, but wait for the device to be ready */
 610         ctrl->use_mdr = 0;
 611         out_be32(&lbc->fir,
 612                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 613                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 614         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 615         out_be32(&lbc->fbcr, 1);
 616         set_addr(mtd, 0, 0, 0);
 617         ctrl->read_bytes = 1;
 618
 619         fsl_elbc_run_command(mtd);
 620
 621         if (ctrl->status != LTESR_CC)
 622                 return NAND_STATUS_FAIL;
 623
 624         /* The chip always seems to report that it is
 625          * write-protected, even when it is not.
 626          */
 627         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 628         return fsl_elbc_read_byte(mtd);
 629 }
 630
 631 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 632                               uint8_t *buf, int oob_required, int page)
 633 {
 634         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 635         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 636
 637         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 638                 mtd->ecc_stats.failed++;
 639
 640         return 0;
 641 }
 642
 643 /* ECC will be calculated automatically, and errors will be detected in
 644  * waitfunc.
 645  */
 646 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 647                                 const uint8_t *buf, int oob_required)
 648 {
 649         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 650         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 651
 652         return 0;
 653 }
 654
 655 static struct fsl_elbc_ctrl *elbc_ctrl;
 656
 657 static void fsl_elbc_ctrl_init(void)
 658 {
 659         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 660         if (!elbc_ctrl)
 661                 return;
 662
 663         elbc_ctrl->regs = LBC_BASE_ADDR;
 664
 665         /* clear event registers */
 666         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 667         out_be32(&elbc_ctrl->regs->lteatr, 0);
 668
 669         /* Enable interrupts for any detected events */
 670         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 671
 672         elbc_ctrl->read_bytes = 0;
 673         elbc_ctrl->index = 0;
 674         elbc_ctrl->addr = NULL;
 675 }
 676
 677 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 678 {
 679         struct mtd_info *mtd = &nand_info[devnum];
 680         struct nand_chip *nand;
 681         struct fsl_elbc_mtd *priv;
 682         uint32_t br = 0, or = 0;
 683         int ret;
 684
 685         if (!elbc_ctrl) {
 686                 fsl_elbc_ctrl_init();
 687                 if (!elbc_ctrl)
 688                         return -1;
 689         }
 690
 691         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 692         if (!priv)
 693                 return -ENOMEM;
 694
 695         priv->ctrl = elbc_ctrl;
 696         priv->vbase = addr;
 697
 698         /* Find which chip select it is connected to.  It'd be nice
 699          * if we could pass more than one datum to the NAND driver...
 700          */
 701         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 702                 phys_addr_t phys_addr = virt_to_phys(addr);
 703
 704                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 705                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 706
 707                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 708                     (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
 709                         break;
 710         }
 711
 712         if (priv->bank >= MAX_BANKS) {
 713                 printf("fsl_elbc_nand: address did not match any "
 714                        "chip selects\n");
 715                 return -ENODEV;
 716         }
 717
 718         nand = &priv->chip;
 719         mtd->priv = nand;
 720
 721         elbc_ctrl->chips[priv->bank] = priv;
 722
 723         /* fill in nand_chip structure */
 724         /* set up function call table */
 725         nand->read_byte = fsl_elbc_read_byte;
 726         nand->write_buf = fsl_elbc_write_buf;
 727         nand->read_buf = fsl_elbc_read_buf;
 728         nand->verify_buf = fsl_elbc_verify_buf;
 729         nand->select_chip = fsl_elbc_select_chip;
 730         nand->cmdfunc = fsl_elbc_cmdfunc;
 731         nand->waitfunc = fsl_elbc_wait;
 732
 733         /* set up nand options */
 734         nand->bbt_td = &bbt_main_descr;
 735         nand->bbt_md = &bbt_mirror_descr;
 736
 737         /* set up nand options */
 738         nand->options = NAND_NO_SUBPAGE_WRITE;
 739         nand->bbt_options = NAND_BBT_USE_FLASH;
 740
 741         nand->controller = &elbc_ctrl->controller;
 742         nand->priv = priv;
 743
 744         nand->ecc.read_page = fsl_elbc_read_page;
 745         nand->ecc.write_page = fsl_elbc_write_page;
 746
 747         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 748
 749         /* If CS Base Register selects full hardware ECC then use it */
 750         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 751                 nand->ecc.mode = NAND_ECC_HW;
 752
 753                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 754                                    &fsl_elbc_oob_sp_eccm1 :
 755                                    &fsl_elbc_oob_sp_eccm0;
 756
 757                 nand->ecc.size = 512;
 758                 nand->ecc.bytes = 3;
 759                 nand->ecc.steps = 1;
 760                 nand->ecc.strength = 1;
 761         } else {
 762                 /* otherwise fall back to default software ECC */
 763                 nand->ecc.mode = NAND_ECC_SOFT;
 764         }
 765
 766         ret = nand_scan_ident(mtd, 1, NULL);
 767         if (ret)
 768                 return ret;
 769
 770         /* Large-page-specific setup */
 771         if (mtd->writesize == 2048) {
 772                 setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 773                              OR_FCM_PGS);
 774                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 775
 776                 priv->page_size = 1;
 777                 nand->badblock_pattern = &largepage_memorybased;
 778
 779                 /*
 780                  * Hardware expects small page has ECCM0, large page has
 781                  * ECCM1 when booting from NAND, and we follow that even
 782                  * when not booting from NAND.
 783                  */
 784                 priv->fmr |= FMR_ECCM;
 785
 786                 /* adjust ecc setup if needed */
 787                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 788                         nand->ecc.steps = 4;
 789                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 790                                            &fsl_elbc_oob_lp_eccm1 :
 791                                            &fsl_elbc_oob_lp_eccm0;
 792                 }
 793         } else if (mtd->writesize == 512) {
 794                 clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 795                              OR_FCM_PGS);
 796                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 797         } else {
 798                 return -ENODEV;
 799         }
 800
 801         ret = nand_scan_tail(mtd);
 802         if (ret)
 803                 return ret;
 804
 805         ret = nand_register(devnum);
 806         if (ret)
 807                 return ret;
 808
 809         return 0;
 810 }
 811
 812 #ifndef CONFIG_SYS_NAND_BASE_LIST
 813 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 814 #endif
 815
 816 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
 817         CONFIG_SYS_NAND_BASE_LIST;
 818
 819 void board_nand_init(void)
 820 {
 821         int i;
 822
 823         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 824                 fsl_elbc_chip_init(i, (u8 *)base_address[i]);
 825 }