drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   2  *
   3  * Copyright (c) 2006-2008 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25 #include <nand.h>
  26
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/nand.h>
  29 #include <linux/mtd/nand_ecc.h>
  30
  31 #include <asm/io.h>
  32 #include <asm/errno.h>
  33
  34 #ifdef VERBOSE_DEBUG
  35 #define DEBUG_ELBC
  36 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  37 #else
  38 #define vdbg(format, arg...) do {} while (0)
  39 #endif
  40
  41 /* Can't use plain old DEBUG because the linux mtd
  42  * headers define it as a macro.
  43  */
  44 #ifdef DEBUG_ELBC
  45 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  46 #else
  47 #define dbg(format, arg...) do {} while (0)
  48 #endif
  49
  50 #define MAX_BANKS 8
  51 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  52 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
  53
  54 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  55
  56 struct fsl_elbc_ctrl;
  57
  58 /* mtd information per set */
  59
  60 struct fsl_elbc_mtd {
  61         struct nand_chip chip;
  62         struct fsl_elbc_ctrl *ctrl;
  63
  64         struct device *dev;
  65         int bank;               /* Chip select bank number           */
  66         u8 __iomem *vbase;      /* Chip select base virtual address  */
  67         int page_size;          /* NAND page size (0=512, 1=2048)    */
  68         unsigned int fmr;       /* FCM Flash Mode Register value     */
  69 };
  70
  71 /* overview of the fsl elbc controller */
  72
  73 struct fsl_elbc_ctrl {
  74         struct nand_hw_control controller;
  75         struct fsl_elbc_mtd *chips[MAX_BANKS];
  76
  77         /* device info */
  78         fsl_lbc_t *regs;
  79         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  80         unsigned int page;       /* Last page written to / read from      */
  81         unsigned int read_bytes; /* Number of bytes read during command   */
  82         unsigned int column;     /* Saved column from SEQIN               */
  83         unsigned int index;      /* Pointer to next byte to 'read'        */
  84         unsigned int status;     /* status read from LTESR after last op  */
  85         unsigned int mdr;        /* UPM/FCM Data Register value           */
  86         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  87         unsigned int oob;        /* Non zero if operating on OOB data     */
  88 };
  89
  90 /* These map to the positions used by the FCM hardware ECC generator */
  91
  92 /* Small Page FLASH with FMR[ECCM] = 0 */
  93 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  94         .eccbytes = 3,
  95         .eccpos = {6, 7, 8},
  96         .oobfree = { {0, 5}, {9, 7} },
  97 };
  98
  99 /* Small Page FLASH with FMR[ECCM] = 1 */
 100 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
 101         .eccbytes = 3,
 102         .eccpos = {8, 9, 10},
 103         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 104 };
 105
 106 /* Large Page FLASH with FMR[ECCM] = 0 */
 107 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 108         .eccbytes = 12,
 109         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 110         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 111 };
 112
 113 /* Large Page FLASH with FMR[ECCM] = 1 */
 114 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 115         .eccbytes = 12,
 116         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 117         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 118 };
 119
 120 /*
 121  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 122  * 1, so we have to adjust bad block pattern. This pattern should be used for
 123  * x8 chips only. So far hardware does not support x16 chips anyway.
 124  */
 125 static u8 scan_ff_pattern[] = { 0xff, };
 126
 127 static struct nand_bbt_descr largepage_memorybased = {
 128         .options = 0,
 129         .offs = 0,
 130         .len = 1,
 131         .pattern = scan_ff_pattern,
 132 };
 133
 134 /*
 135  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 136  * interfere with ECC positions, that's why we implement our own descriptors.
 137  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 138  */
 139 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 140 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 141
 142 static struct nand_bbt_descr bbt_main_descr = {
 143         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 144                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 145         .offs = 11,
 146         .len = 4,
 147         .veroffs = 15,
 148         .maxblocks = 4,
 149         .pattern = bbt_pattern,
 150 };
 151
 152 static struct nand_bbt_descr bbt_mirror_descr = {
 153         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 154                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 155         .offs = 11,
 156         .len = 4,
 157         .veroffs = 15,
 158         .maxblocks = 4,
 159         .pattern = mirror_pattern,
 160 };
 161
 162 /*=================================*/
 163
 164 /*
 165  * Set up the FCM hardware block and page address fields, and the fcm
 166  * structure addr field to point to the correct FCM buffer in memory
 167  */
 168 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 169 {
 170         struct nand_chip *chip = mtd->priv;
 171         struct fsl_elbc_mtd *priv = chip->priv;
 172         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 173         fsl_lbc_t *lbc = ctrl->regs;
 174         int buf_num;
 175
 176         ctrl->page = page_addr;
 177
 178         if (priv->page_size) {
 179                 out_be32(&lbc->fbar, page_addr >> 6);
 180                 out_be32(&lbc->fpar,
 181                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 182                          (oob ? FPAR_LP_MS : 0) | column);
 183                 buf_num = (page_addr & 1) << 2;
 184         } else {
 185                 out_be32(&lbc->fbar, page_addr >> 5);
 186                 out_be32(&lbc->fpar,
 187                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 188                          (oob ? FPAR_SP_MS : 0) | column);
 189                 buf_num = page_addr & 7;
 190         }
 191
 192         ctrl->addr = priv->vbase + buf_num * 1024;
 193         ctrl->index = column;
 194
 195         /* for OOB data point to the second half of the buffer */
 196         if (oob)
 197                 ctrl->index += priv->page_size ? 2048 : 512;
 198
 199         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 200              "index %x, pes %d ps %d\n",
 201              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 202              chip->phys_erase_shift, chip->page_shift);
 203 }
 204
 205 /*
 206  * execute FCM command and wait for it to complete
 207  */
 208 static int fsl_elbc_run_command(struct mtd_info *mtd)
 209 {
 210         struct nand_chip *chip = mtd->priv;
 211         struct fsl_elbc_mtd *priv = chip->priv;
 212         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 213         fsl_lbc_t *lbc = ctrl->regs;
 214         long long end_tick;
 215         u32 ltesr;
 216
 217         /* Setup the FMR[OP] to execute without write protection */
 218         out_be32(&lbc->fmr, priv->fmr | 3);
 219         if (ctrl->use_mdr)
 220                 out_be32(&lbc->mdr, ctrl->mdr);
 221
 222         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 223              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 224         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 225              "fbcr=%08x bank=%d\n",
 226              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 227              in_be32(&lbc->fbcr), priv->bank);
 228
 229         /* execute special operation */
 230         out_be32(&lbc->lsor, priv->bank);
 231
 232         /* wait for FCM complete flag or timeout */
 233         end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
 234
 235         ltesr = 0;
 236         while (end_tick > get_ticks()) {
 237                 ltesr = in_be32(&lbc->ltesr);
 238                 if (ltesr & LTESR_CC)
 239                         break;
 240         }
 241
 242         ctrl->status = ltesr & LTESR_NAND_MASK;
 243         out_be32(&lbc->ltesr, ctrl->status);
 244         out_be32(&lbc->lteatr, 0);
 245
 246         /* store mdr value in case it was needed */
 247         if (ctrl->use_mdr)
 248                 ctrl->mdr = in_be32(&lbc->mdr);
 249
 250         ctrl->use_mdr = 0;
 251
 252         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 253              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 254
 255         /* returns 0 on success otherwise non-zero) */
 256         return ctrl->status == LTESR_CC ? 0 : -EIO;
 257 }
 258
 259 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 260 {
 261         struct fsl_elbc_mtd *priv = chip->priv;
 262         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 263         fsl_lbc_t *lbc = ctrl->regs;
 264
 265         if (priv->page_size) {
 266                 out_be32(&lbc->fir,
 267                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 268                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 269                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 270                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 271                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 272
 273                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 274                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 275         } else {
 276                 out_be32(&lbc->fir,
 277                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 278                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 279                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 280                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 281
 282                 if (oob)
 283                         out_be32(&lbc->fcr,
 284                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 285                 else
 286                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 287         }
 288 }
 289
 290 /* cmdfunc send commands to the FCM */
 291 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 292                              int column, int page_addr)
 293 {
 294         struct nand_chip *chip = mtd->priv;
 295         struct fsl_elbc_mtd *priv = chip->priv;
 296         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 297         fsl_lbc_t *lbc = ctrl->regs;
 298
 299         ctrl->use_mdr = 0;
 300
 301         /* clear the read buffer */
 302         ctrl->read_bytes = 0;
 303         if (command != NAND_CMD_PAGEPROG)
 304                 ctrl->index = 0;
 305
 306         switch (command) {
 307         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 308         case NAND_CMD_READ1:
 309                 column += 256;
 310
 311         /* fall-through */
 312         case NAND_CMD_READ0:
 313                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 314                      " 0x%x, column: 0x%x.\n", page_addr, column);
 315
 316                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 317                 set_addr(mtd, 0, page_addr, 0);
 318
 319                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 320                 ctrl->index += column;
 321
 322                 fsl_elbc_do_read(chip, 0);
 323                 fsl_elbc_run_command(mtd);
 324                 return;
 325
 326         /* READOOB reads only the OOB because no ECC is performed. */
 327         case NAND_CMD_READOOB:
 328                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 329                      " 0x%x, column: 0x%x.\n", page_addr, column);
 330
 331                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 332                 set_addr(mtd, column, page_addr, 1);
 333
 334                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 335
 336                 fsl_elbc_do_read(chip, 1);
 337                 fsl_elbc_run_command(mtd);
 338
 339                 return;
 340
 341         /* READID must read all 5 possible bytes while CEB is active */
 342         case NAND_CMD_READID:
 343         case NAND_CMD_PARAM:
 344                 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
 345
 346                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 347                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 348                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 349                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
 350                 /*
 351                  * although currently it's 8 bytes for READID, we always read
 352                  * the maximum 256 bytes(for PARAM)
 353                  */
 354                 out_be32(&lbc->fbcr, 256);
 355                 ctrl->read_bytes = 256;
 356                 ctrl->use_mdr = 1;
 357                 ctrl->mdr = column;
 358                 set_addr(mtd, 0, 0, 0);
 359                 fsl_elbc_run_command(mtd);
 360                 return;
 361
 362         /* ERASE1 stores the block and page address */
 363         case NAND_CMD_ERASE1:
 364                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 365                      "page_addr: 0x%x.\n", page_addr);
 366                 set_addr(mtd, 0, page_addr, 0);
 367                 return;
 368
 369         /* ERASE2 uses the block and page address from ERASE1 */
 370         case NAND_CMD_ERASE2:
 371                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 372
 373                 out_be32(&lbc->fir,
 374                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 375                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 376                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 377
 378                 out_be32(&lbc->fcr,
 379                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 380                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 381
 382                 out_be32(&lbc->fbcr, 0);
 383                 ctrl->read_bytes = 0;
 384
 385                 fsl_elbc_run_command(mtd);
 386                 return;
 387
 388         /* SEQIN sets up the addr buffer and all registers except the length */
 389         case NAND_CMD_SEQIN: {
 390                 u32 fcr;
 391                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 392                      "page_addr: 0x%x, column: 0x%x.\n",
 393                      page_addr, column);
 394
 395                 ctrl->column = column;
 396                 ctrl->oob = 0;
 397
 398                 if (priv->page_size) {
 399                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 400                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 401
 402                         out_be32(&lbc->fir,
 403                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 404                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 405                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 406                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 407                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 408                 } else {
 409                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 410                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 411
 412                         out_be32(&lbc->fir,
 413                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 414                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 415                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 416                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 417                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 418                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 419
 420                         if (column >= mtd->writesize) {
 421                                 /* OOB area --> READOOB */
 422                                 column -= mtd->writesize;
 423                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 424                                 ctrl->oob = 1;
 425                         } else if (column < 256) {
 426                                 /* First 256 bytes --> READ0 */
 427                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 428                         } else {
 429                                 /* Second 256 bytes --> READ1 */
 430                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 431                         }
 432                 }
 433
 434                 out_be32(&lbc->fcr, fcr);
 435                 set_addr(mtd, column, page_addr, ctrl->oob);
 436                 return;
 437         }
 438
 439         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 440         case NAND_CMD_PAGEPROG: {
 441                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 442                      "writing %d bytes.\n", ctrl->index);
 443
 444                 /* if the write did not start at 0 or is not a full page
 445                  * then set the exact length, otherwise use a full page
 446                  * write so the HW generates the ECC.
 447                  */
 448                 if (ctrl->oob || ctrl->column != 0 ||
 449                     ctrl->index != mtd->writesize + mtd->oobsize)
 450                         out_be32(&lbc->fbcr, ctrl->index);
 451                 else
 452                         out_be32(&lbc->fbcr, 0);
 453
 454                 fsl_elbc_run_command(mtd);
 455
 456                 return;
 457         }
 458
 459         /* CMD_STATUS must read the status byte while CEB is active */
 460         /* Note - it does not wait for the ready line */
 461         case NAND_CMD_STATUS:
 462                 out_be32(&lbc->fir,
 463                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 464                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 465                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 466                 out_be32(&lbc->fbcr, 1);
 467                 set_addr(mtd, 0, 0, 0);
 468                 ctrl->read_bytes = 1;
 469
 470                 fsl_elbc_run_command(mtd);
 471
 472                 /* The chip always seems to report that it is
 473                  * write-protected, even when it is not.
 474                  */
 475                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 476                 return;
 477
 478         /* RESET without waiting for the ready line */
 479         case NAND_CMD_RESET:
 480                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 481                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 482                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 483                 fsl_elbc_run_command(mtd);
 484                 return;
 485
 486         default:
 487                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 488                         command);
 489         }
 490 }
 491
 492 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 493 {
 494         /* The hardware does not seem to support multiple
 495          * chips per bank.
 496          */
 497 }
 498
 499 /*
 500  * Write buf to the FCM Controller Data Buffer
 501  */
 502 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 503 {
 504         struct nand_chip *chip = mtd->priv;
 505         struct fsl_elbc_mtd *priv = chip->priv;
 506         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 507         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 508
 509         if (len <= 0) {
 510                 printf("write_buf of %d bytes", len);
 511                 ctrl->status = 0;
 512                 return;
 513         }
 514
 515         if ((unsigned int)len > bufsize - ctrl->index) {
 516                 printf("write_buf beyond end of buffer "
 517                        "(%d requested, %u available)\n",
 518                        len, bufsize - ctrl->index);
 519                 len = bufsize - ctrl->index;
 520         }
 521
 522         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 523         /*
 524          * This is workaround for the weird elbc hangs during nand write,
 525          * Scott Wood says: "...perhaps difference in how long it takes a
 526          * write to make it through the localbus compared to a write to IMMR
 527          * is causing problems, and sync isn't helping for some reason."
 528          * Reading back the last byte helps though.
 529          */
 530         in_8(&ctrl->addr[ctrl->index] + len - 1);
 531
 532         ctrl->index += len;
 533 }
 534
 535 /*
 536  * read a byte from either the FCM hardware buffer if it has any data left
 537  * otherwise issue a command to read a single byte.
 538  */
 539 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 540 {
 541         struct nand_chip *chip = mtd->priv;
 542         struct fsl_elbc_mtd *priv = chip->priv;
 543         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 544
 545         /* If there are still bytes in the FCM, then use the next byte. */
 546         if (ctrl->index < ctrl->read_bytes)
 547                 return in_8(&ctrl->addr[ctrl->index++]);
 548
 549         printf("read_byte beyond end of buffer\n");
 550         return ERR_BYTE;
 551 }
 552
 553 /*
 554  * Read from the FCM Controller Data Buffer
 555  */
 556 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 557 {
 558         struct nand_chip *chip = mtd->priv;
 559         struct fsl_elbc_mtd *priv = chip->priv;
 560         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 561         int avail;
 562
 563         if (len < 0)
 564                 return;
 565
 566         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 567         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 568         ctrl->index += avail;
 569
 570         if (len > avail)
 571                 printf("read_buf beyond end of buffer "
 572                        "(%d requested, %d available)\n",
 573                        len, avail);
 574 }
 575
 576 /*
 577  * Verify buffer against the FCM Controller Data Buffer
 578  */
 579 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
 580                                const u_char *buf, int len)
 581 {
 582         struct nand_chip *chip = mtd->priv;
 583         struct fsl_elbc_mtd *priv = chip->priv;
 584         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 585         int i;
 586
 587         if (len < 0) {
 588                 printf("write_buf of %d bytes", len);
 589                 return -EINVAL;
 590         }
 591
 592         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 593                 printf("verify_buf beyond end of buffer "
 594                        "(%d requested, %u available)\n",
 595                        len, ctrl->read_bytes - ctrl->index);
 596
 597                 ctrl->index = ctrl->read_bytes;
 598                 return -EINVAL;
 599         }
 600
 601         for (i = 0; i < len; i++)
 602                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 603                         break;
 604
 605         ctrl->index += len;
 606         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 607 }
 608
 609 /* This function is called after Program and Erase Operations to
 610  * check for success or failure.
 611  */
 612 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 613 {
 614         struct fsl_elbc_mtd *priv = chip->priv;
 615         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 616         fsl_lbc_t *lbc = ctrl->regs;
 617
 618         if (ctrl->status != LTESR_CC)
 619                 return NAND_STATUS_FAIL;
 620
 621         /* Use READ_STATUS command, but wait for the device to be ready */
 622         ctrl->use_mdr = 0;
 623         out_be32(&lbc->fir,
 624                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 625                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 626         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 627         out_be32(&lbc->fbcr, 1);
 628         set_addr(mtd, 0, 0, 0);
 629         ctrl->read_bytes = 1;
 630
 631         fsl_elbc_run_command(mtd);
 632
 633         if (ctrl->status != LTESR_CC)
 634                 return NAND_STATUS_FAIL;
 635
 636         /* The chip always seems to report that it is
 637          * write-protected, even when it is not.
 638          */
 639         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 640         return fsl_elbc_read_byte(mtd);
 641 }
 642
 643 static int fsl_elbc_read_page(struct mtd_info *mtd,
 644                               struct nand_chip *chip,
 645                               uint8_t *buf, int page)
 646 {
 647         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 648         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 649
 650         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 651                 mtd->ecc_stats.failed++;
 652
 653         return 0;
 654 }
 655
 656 /* ECC will be calculated automatically, and errors will be detected in
 657  * waitfunc.
 658  */
 659 static void fsl_elbc_write_page(struct mtd_info *mtd,
 660                                 struct nand_chip *chip,
 661                                 const uint8_t *buf)
 662 {
 663         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 664         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 665 }
 666
 667 static struct fsl_elbc_ctrl *elbc_ctrl;
 668
 669 static void fsl_elbc_ctrl_init(void)
 670 {
 671         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 672         if (!elbc_ctrl)
 673                 return;
 674
 675         elbc_ctrl->regs = LBC_BASE_ADDR;
 676
 677         /* clear event registers */
 678         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 679         out_be32(&elbc_ctrl->regs->lteatr, 0);
 680
 681         /* Enable interrupts for any detected events */
 682         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 683
 684         elbc_ctrl->read_bytes = 0;
 685         elbc_ctrl->index = 0;
 686         elbc_ctrl->addr = NULL;
 687 }
 688
 689 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 690 {
 691         struct mtd_info *mtd = &nand_info[devnum];
 692         struct nand_chip *nand;
 693         struct fsl_elbc_mtd *priv;
 694         uint32_t br = 0, or = 0;
 695         int ret;
 696
 697         if (!elbc_ctrl) {
 698                 fsl_elbc_ctrl_init();
 699                 if (!elbc_ctrl)
 700                         return -1;
 701         }
 702
 703         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 704         if (!priv)
 705                 return -ENOMEM;
 706
 707         priv->ctrl = elbc_ctrl;
 708         priv->vbase = addr;
 709
 710         /* Find which chip select it is connected to.  It'd be nice
 711          * if we could pass more than one datum to the NAND driver...
 712          */
 713         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 714                 phys_addr_t phys_addr = virt_to_phys(addr);
 715
 716                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 717                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 718
 719                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 720                     (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
 721                         break;
 722         }
 723
 724         if (priv->bank >= MAX_BANKS) {
 725                 printf("fsl_elbc_nand: address did not match any "
 726                        "chip selects\n");
 727                 return -ENODEV;
 728         }
 729
 730         nand = &priv->chip;
 731         mtd->priv = nand;
 732
 733         elbc_ctrl->chips[priv->bank] = priv;
 734
 735         /* fill in nand_chip structure */
 736         /* set up function call table */
 737         nand->read_byte = fsl_elbc_read_byte;
 738         nand->write_buf = fsl_elbc_write_buf;
 739         nand->read_buf = fsl_elbc_read_buf;
 740         nand->verify_buf = fsl_elbc_verify_buf;
 741         nand->select_chip = fsl_elbc_select_chip;
 742         nand->cmdfunc = fsl_elbc_cmdfunc;
 743         nand->waitfunc = fsl_elbc_wait;
 744
 745         /* set up nand options */
 746         nand->bbt_td = &bbt_main_descr;
 747         nand->bbt_md = &bbt_mirror_descr;
 748
 749         /* set up nand options */
 750         nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
 751                         NAND_USE_FLASH_BBT;
 752
 753         nand->controller = &elbc_ctrl->controller;
 754         nand->priv = priv;
 755
 756         nand->ecc.read_page = fsl_elbc_read_page;
 757         nand->ecc.write_page = fsl_elbc_write_page;
 758
 759 #ifdef CONFIG_FSL_ELBC_FMR
 760         priv->fmr = CONFIG_FSL_ELBC_FMR;
 761 #else
 762         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 763
 764         /*
 765          * Hardware expects small page has ECCM0, large page has ECCM1
 766          * when booting from NAND.  Board config can override if not
 767          * booting from NAND.
 768          */
 769         if (or & OR_FCM_PGS)
 770                 priv->fmr |= FMR_ECCM;
 771 #endif
 772
 773         /* If CS Base Register selects full hardware ECC then use it */
 774         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 775                 nand->ecc.mode = NAND_ECC_HW;
 776
 777                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 778                                    &fsl_elbc_oob_sp_eccm1 :
 779                                    &fsl_elbc_oob_sp_eccm0;
 780
 781                 nand->ecc.size = 512;
 782                 nand->ecc.bytes = 3;
 783                 nand->ecc.steps = 1;
 784         } else {
 785                 /* otherwise fall back to default software ECC */
 786                 nand->ecc.mode = NAND_ECC_SOFT;
 787         }
 788
 789         /* Large-page-specific setup */
 790         if (or & OR_FCM_PGS) {
 791                 priv->page_size = 1;
 792                 nand->badblock_pattern = &largepage_memorybased;
 793
 794                 /* adjust ecc setup if needed */
 795                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 796                         nand->ecc.steps = 4;
 797                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 798                                            &fsl_elbc_oob_lp_eccm1 :
 799                                            &fsl_elbc_oob_lp_eccm0;
 800                 }
 801         }
 802
 803         ret = nand_scan_ident(mtd, 1, NULL);
 804         if (ret)
 805                 return ret;
 806
 807         ret = nand_scan_tail(mtd);
 808         if (ret)
 809                 return ret;
 810
 811         ret = nand_register(devnum);
 812         if (ret)
 813                 return ret;
 814
 815         return 0;
 816 }
 817
 818 #ifndef CONFIG_SYS_NAND_BASE_LIST
 819 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 820 #endif
 821
 822 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
 823         CONFIG_SYS_NAND_BASE_LIST;
 824
 825 void board_nand_init(void)
 826 {
 827         int i;
 828
 829         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 830                 fsl_elbc_chip_init(i, (u8 *)base_address[i]);
 831 }