2 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mtd/nand.h>
15 static inline int is_blank(uchar
*addr
, int page_size
)
19 for (i
= 0; i
< page_size
; i
++) {
20 if (__raw_readb(&addr
[i
]) != 0xff)
25 * For the SPL, don't worry about uncorrectable errors
26 * where the main area is all FFs but shouldn't be.
31 /* returns nonzero if entire page is blank */
32 static inline int check_read_ecc(uchar
*buf
, u32
*eccstat
,
33 unsigned int bufnum
, int page_size
)
35 u32 reg
= eccstat
[bufnum
/ 4];
36 int errors
= (reg
>> ((3 - bufnum
% 4) * 8)) & 0xf;
38 if (errors
== 0xf) { /* uncorrectable */
39 /* Blank pages fail hw ECC checks */
40 if (is_blank(buf
, page_size
))
51 static inline struct fsl_ifc_runtime
*runtime_regs_address(void)
53 struct fsl_ifc regs
= {(void *)CONFIG_SYS_IFC_ADDR
, NULL
};
56 ver
= ifc_in32(®s
.gregs
->ifc_rev
);
57 if (ver
>= FSL_IFC_V2_0_0
)
58 regs
.rregs
= (void *)CONFIG_SYS_IFC_ADDR
+ IFC_RREGS_64KOFFSET
;
60 regs
.rregs
= (void *)CONFIG_SYS_IFC_ADDR
+ IFC_RREGS_4KOFFSET
;
65 static inline void nand_wait(uchar
*buf
, int bufnum
, int page_size
)
67 struct fsl_ifc_runtime
*ifc
= runtime_regs_address();
70 int bufperpage
= page_size
/ 512;
74 bufnum_end
= bufnum
+ bufperpage
- 1;
77 status
= ifc_in32(&ifc
->ifc_nand
.nand_evter_stat
);
78 } while (!(status
& IFC_NAND_EVTER_STAT_OPC
));
80 if (status
& IFC_NAND_EVTER_STAT_FTOER
) {
81 puts("flash time out error\n");
86 for (i
= bufnum
/ 4; i
<= bufnum_end
/ 4; i
++)
87 eccstat
[i
] = ifc_in32(&ifc
->ifc_nand
.nand_eccstat
[i
]);
89 for (i
= bufnum
; i
<= bufnum_end
; i
++) {
90 if (check_read_ecc(buf
, eccstat
, i
, page_size
))
94 ifc_out32(&ifc
->ifc_nand
.nand_evter_stat
, status
);
97 static inline int bad_block(uchar
*marker
, int port_size
)
100 return __raw_readb(marker
) != 0xff;
102 return __raw_readw((u16
*)marker
) != 0xffff;
105 int nand_spl_load_image(uint32_t offs
, unsigned int uboot_size
, void *vdst
)
107 struct fsl_ifc_fcm
*gregs
= (void *)CONFIG_SYS_IFC_ADDR
;
108 struct fsl_ifc_runtime
*ifc
= NULL
;
109 uchar
*buf
= (uchar
*)CONFIG_SYS_NAND_BASE
;
115 int bufnum_mask
, bufnum
, ver
= 0;
125 ifc
= runtime_regs_address();
127 /* Get NAND Flash configuration */
128 csor
= CONFIG_SYS_NAND_CSOR
;
129 cspr
= CONFIG_SYS_NAND_CSPR
;
131 port_size
= (cspr
& CSPR_PORT_SIZE_16
) ? 16 : 8;
133 if ((csor
& CSOR_NAND_PGS_MASK
) == CSOR_NAND_PGS_8K
) {
136 } else if ((csor
& CSOR_NAND_PGS_MASK
) == CSOR_NAND_PGS_4K
) {
139 } else if ((csor
& CSOR_NAND_PGS_MASK
) == CSOR_NAND_PGS_2K
) {
150 ver
= ifc_in32(&gregs
->ifc_rev
);
151 if (ver
>= FSL_IFC_V2_0_0
)
152 bufnum_mask
= (bufnum_mask
* 2) + 1;
155 32 << ((csor
& CSOR_NAND_PB_MASK
) >> CSOR_NAND_PB_SHIFT
);
157 blk_size
= pages_per_blk
* page_size
;
159 /* Open Full SRAM mapping for spare are access */
160 ifc_out32(&ifc
->ifc_nand
.ncfgr
, 0x0);
162 /* Clear Boot events */
163 ifc_out32(&ifc
->ifc_nand
.nand_evter_stat
, 0xffffffff);
165 /* Program FIR/FCR for Large/Small page */
166 if (page_size
> 512) {
167 ifc_out32(&ifc
->ifc_nand
.nand_fir0
,
168 (IFC_FIR_OP_CW0
<< IFC_NAND_FIR0_OP0_SHIFT
) |
169 (IFC_FIR_OP_CA0
<< IFC_NAND_FIR0_OP1_SHIFT
) |
170 (IFC_FIR_OP_RA0
<< IFC_NAND_FIR0_OP2_SHIFT
) |
171 (IFC_FIR_OP_CMD1
<< IFC_NAND_FIR0_OP3_SHIFT
) |
172 (IFC_FIR_OP_BTRD
<< IFC_NAND_FIR0_OP4_SHIFT
));
173 ifc_out32(&ifc
->ifc_nand
.nand_fir1
, 0x0);
175 ifc_out32(&ifc
->ifc_nand
.nand_fcr0
,
176 (NAND_CMD_READ0
<< IFC_NAND_FCR0_CMD0_SHIFT
) |
177 (NAND_CMD_READSTART
<< IFC_NAND_FCR0_CMD1_SHIFT
));
179 ifc_out32(&ifc
->ifc_nand
.nand_fir0
,
180 (IFC_FIR_OP_CW0
<< IFC_NAND_FIR0_OP0_SHIFT
) |
181 (IFC_FIR_OP_CA0
<< IFC_NAND_FIR0_OP1_SHIFT
) |
182 (IFC_FIR_OP_RA0
<< IFC_NAND_FIR0_OP2_SHIFT
) |
183 (IFC_FIR_OP_BTRD
<< IFC_NAND_FIR0_OP3_SHIFT
));
184 ifc_out32(&ifc
->ifc_nand
.nand_fir1
, 0x0);
186 ifc_out32(&ifc
->ifc_nand
.nand_fcr0
,
187 NAND_CMD_READ0
<< IFC_NAND_FCR0_CMD0_SHIFT
);
190 /* Program FBCR = 0 for full page read */
191 ifc_out32(&ifc
->ifc_nand
.nand_fbcr
, 0);
193 /* Read and copy u-boot on SDRAM from NAND device, In parallel
194 * check for Bad block if found skip it and read continue to
197 while (pos
< uboot_size
) {
200 pg_no
= offs
/ page_size
;
201 bufnum
= pg_no
& bufnum_mask
;
202 sram_addr
= bufnum
* page_size
* 2;
204 ifc_out32(&ifc
->ifc_nand
.row0
, pg_no
);
205 ifc_out32(&ifc
->ifc_nand
.col0
, 0);
207 ifc_out32(&ifc
->ifc_nand
.nandseq_strt
,
208 IFC_NAND_SEQ_STRT_FIR_STRT
);
210 /* wait for read to complete */
211 nand_wait(&buf
[sram_addr
], bufnum
, page_size
);
214 * If either of the first two pages are marked bad,
215 * continue to the next block.
218 bad_block(&buf
[sram_addr
+ page_size
+ bad_marker
],
221 offs
= (offs
+ blk_size
) & ~(blk_size
- 1);
222 pos
&= ~(blk_size
- 1);
226 for (j
= 0; j
< page_size
; j
++)
227 dst
[pos
+ j
] = __raw_readb(&buf
[sram_addr
+ j
]);
231 } while ((offs
& (blk_size
- 1)) && (pos
< uboot_size
));
238 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
239 * configured and available since this code loads the main U-Boot image
240 * from NAND into SDRAM and starts from there.
244 __attribute__((noreturn
)) void (*uboot
)(void);
246 * Load U-Boot image from NAND into RAM
248 nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS
,
249 CONFIG_SYS_NAND_U_BOOT_SIZE
,
250 (uchar
*)CONFIG_SYS_NAND_U_BOOT_DST
);
252 #ifdef CONFIG_NAND_ENV_DST
253 nand_spl_load_image(CONFIG_ENV_OFFSET
, CONFIG_ENV_SIZE
,
254 (uchar
*)CONFIG_NAND_ENV_DST
);
256 #ifdef CONFIG_ENV_OFFSET_REDUND
257 nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND
, CONFIG_ENV_SIZE
,
258 (uchar
*)CONFIG_NAND_ENV_DST
+ CONFIG_ENV_SIZE
);
262 * Jump to U-Boot image
264 #ifdef CONFIG_SPL_FLUSH_IMAGE
266 * Clean d-cache and invalidate i-cache, to
267 * make sure that no stale data is executed.
269 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST
, CONFIG_SYS_NAND_U_BOOT_SIZE
);
271 uboot
= (void *)CONFIG_SYS_NAND_U_BOOT_START
;
275 #ifndef CONFIG_SPL_NAND_INIT
280 void nand_deselect(void)