drivers/mtd/nand/fsl_upm.c

   1 /*
   2  * FSL UPM NAND driver
   3  *
   4  * Copyright (C) 2007 MontaVista Software, Inc.
   5  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <config.h>
  14 #include <common.h>
  15 #include <asm/io.h>
  16 #include <asm/errno.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/fsl_upm.h>
  19 #include <nand.h>
  20
  21 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  22 {
  23         clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  24         (void)in_be32(upm->mxmr);
  25 }
  26
  27 static void fsl_upm_end_pattern(struct fsl_upm *upm)
  28 {
  29         clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  30
  31         while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  32                 eieio();
  33 }
  34
  35 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  36                                 void __iomem *io_addr, u32 mar)
  37 {
  38         out_be32(upm->mar, mar);
  39         (void)in_be32(upm->mar);
  40         switch (width) {
  41         case 8:
  42                 out_8(io_addr, 0x0);
  43                 break;
  44         case 16:
  45                 out_be16(io_addr, 0x0);
  46                 break;
  47         case 32:
  48                 out_be32(io_addr, 0x0);
  49                 break;
  50         }
  51 }
  52
  53 static void fun_wait(struct fsl_upm_nand *fun)
  54 {
  55         if (fun->dev_ready) {
  56                 while (!fun->dev_ready(fun->chip_nr))
  57                         debug("unexpected busy state\n");
  58         } else {
  59                 /*
  60                  * If the R/B pin is not connected, like on the TQM8548,
  61                  * a short delay is necessary.
  62                  */
  63                 udelay(1);
  64         }
  65 }
  66
  67 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  68 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  69 {
  70         struct nand_chip *chip = mtd->priv;
  71         struct fsl_upm_nand *fun = chip->priv;
  72
  73         if (chip_nr >= 0) {
  74                 fun->chip_nr = chip_nr;
  75                 chip->IO_ADDR_R = chip->IO_ADDR_W =
  76                         fun->upm.io_addr + fun->chip_offset * chip_nr;
  77         } else if (chip_nr == -1) {
  78                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  79         }
  80 }
  81 #endif
  82
  83 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  84 {
  85         struct nand_chip *chip = mtd->priv;
  86         struct fsl_upm_nand *fun = chip->priv;
  87         void __iomem *io_addr;
  88         u32 mar;
  89
  90         if (!(ctrl & fun->last_ctrl)) {
  91                 fsl_upm_end_pattern(&fun->upm);
  92
  93                 if (cmd == NAND_CMD_NONE)
  94                         return;
  95
  96                 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  97         }
  98
  99         if (ctrl & NAND_CTRL_CHANGE) {
 100                 if (ctrl & NAND_ALE)
 101                         fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
 102                 else if (ctrl & NAND_CLE)
 103                         fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
 104         }
 105
 106         mar = cmd << (32 - fun->width);
 107         io_addr = fun->upm.io_addr;
 108 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 109         if (fun->chip_nr > 0) {
 110                 io_addr += fun->chip_offset * fun->chip_nr;
 111                 if (fun->upm_mar_chip_offset)
 112                         mar |= fun->upm_mar_chip_offset * fun->chip_nr;
 113         }
 114 #endif
 115         fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
 116
 117         /*
 118          * Some boards/chips needs this. At least the MPC8360E-RDK and
 119          * TQM8548 need it. Probably weird chip, because I don't see
 120          * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
 121          * here are 0-2 unexpected busy states per block read.
 122          */
 123         if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
 124                 fun_wait(fun);
 125 }
 126
 127 static u8 nand_read_byte(struct mtd_info *mtd)
 128 {
 129         struct nand_chip *chip = mtd->priv;
 130
 131         return in_8(chip->IO_ADDR_R);
 132 }
 133
 134 static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 135 {
 136         int i;
 137         struct nand_chip *chip = mtd->priv;
 138         struct fsl_upm_nand *fun = chip->priv;
 139
 140         for (i = 0; i < len; i++) {
 141                 out_8(chip->IO_ADDR_W, buf[i]);
 142                 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
 143                         fun_wait(fun);
 144         }
 145
 146         if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
 147                 fun_wait(fun);
 148 }
 149
 150 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 151 {
 152         int i;
 153         struct nand_chip *chip = mtd->priv;
 154
 155         for (i = 0; i < len; i++)
 156                 buf[i] = in_8(chip->IO_ADDR_R);
 157 }
 158
 159 static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 160 {
 161         int i;
 162         struct nand_chip *chip = mtd->priv;
 163
 164         for (i = 0; i < len; i++) {
 165                 if (buf[i] != in_8(chip->IO_ADDR_R))
 166                         return -EFAULT;
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int nand_dev_ready(struct mtd_info *mtd)
 173 {
 174         struct nand_chip *chip = mtd->priv;
 175         struct fsl_upm_nand *fun = chip->priv;
 176
 177         return fun->dev_ready(fun->chip_nr);
 178 }
 179
 180 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 181 {
 182         if (fun->width != 8 && fun->width != 16 && fun->width != 32)
 183                 return -ENOSYS;
 184
 185         fun->last_ctrl = NAND_CLE;
 186
 187         chip->priv = fun;
 188         chip->chip_delay = fun->chip_delay;
 189         chip->ecc.mode = NAND_ECC_SOFT;
 190         chip->cmd_ctrl = fun_cmd_ctrl;
 191 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 192         chip->select_chip = fun_select_chip;
 193 #endif
 194         chip->read_byte = nand_read_byte;
 195         chip->read_buf = nand_read_buf;
 196         chip->write_buf = nand_write_buf;
 197         chip->verify_buf = nand_verify_buf;
 198         if (fun->dev_ready)
 199                 chip->dev_ready = nand_dev_ready;
 200
 201         return 0;
 202 }