2 * MTK ECC controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/module.h>
22 #include <linux/iopoll.h>
24 #include <linux/of_platform.h>
25 #include <linux/mutex.h>
29 #define ECC_IDLE_MASK BIT(0)
30 #define ECC_IRQ_EN BIT(0)
31 #define ECC_OP_ENABLE (1)
32 #define ECC_OP_DISABLE (0)
34 #define ECC_ENCCON (0x00)
35 #define ECC_ENCCNFG (0x04)
36 #define ECC_CNFG_4BIT (0)
37 #define ECC_CNFG_6BIT (1)
38 #define ECC_CNFG_8BIT (2)
39 #define ECC_CNFG_10BIT (3)
40 #define ECC_CNFG_12BIT (4)
41 #define ECC_CNFG_14BIT (5)
42 #define ECC_CNFG_16BIT (6)
43 #define ECC_CNFG_18BIT (7)
44 #define ECC_CNFG_20BIT (8)
45 #define ECC_CNFG_22BIT (9)
46 #define ECC_CNFG_24BIT (0xa)
47 #define ECC_CNFG_28BIT (0xb)
48 #define ECC_CNFG_32BIT (0xc)
49 #define ECC_CNFG_36BIT (0xd)
50 #define ECC_CNFG_40BIT (0xe)
51 #define ECC_CNFG_44BIT (0xf)
52 #define ECC_CNFG_48BIT (0x10)
53 #define ECC_CNFG_52BIT (0x11)
54 #define ECC_CNFG_56BIT (0x12)
55 #define ECC_CNFG_60BIT (0x13)
56 #define ECC_MODE_SHIFT (5)
57 #define ECC_MS_SHIFT (16)
58 #define ECC_ENCDIADDR (0x08)
59 #define ECC_ENCIDLE (0x0C)
60 #define ECC_ENCPAR(x) (0x10 + (x) * sizeof(u32))
61 #define ECC_ENCIRQ_EN (0x80)
62 #define ECC_ENCIRQ_STA (0x84)
63 #define ECC_DECCON (0x100)
64 #define ECC_DECCNFG (0x104)
65 #define DEC_EMPTY_EN BIT(31)
66 #define DEC_CNFG_CORRECT (0x3 << 12)
67 #define ECC_DECIDLE (0x10C)
68 #define ECC_DECENUM0 (0x114)
69 #define ERR_MASK (0x3f)
70 #define ECC_DECDONE (0x124)
71 #define ECC_DECIRQ_EN (0x200)
72 #define ECC_DECIRQ_STA (0x204)
74 #define ECC_TIMEOUT (500000)
76 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
77 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
78 #define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
79 ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
86 struct completion done
;
91 static inline void mtk_ecc_wait_idle(struct mtk_ecc
*ecc
,
92 enum mtk_ecc_operation op
)
94 struct device
*dev
= ecc
->dev
;
98 ret
= readl_poll_timeout_atomic(ecc
->regs
+ ECC_IDLE_REG(op
), val
,
102 dev_warn(dev
, "%s NOT idle\n",
103 op
== ECC_ENCODE
? "encoder" : "decoder");
106 static irqreturn_t
mtk_ecc_irq(int irq
, void *id
)
108 struct mtk_ecc
*ecc
= id
;
109 enum mtk_ecc_operation op
;
112 dec
= readw(ecc
->regs
+ ECC_DECIRQ_STA
) & ECC_IRQ_EN
;
115 dec
= readw(ecc
->regs
+ ECC_DECDONE
);
116 if (dec
& ecc
->sectors
) {
118 complete(&ecc
->done
);
123 enc
= readl(ecc
->regs
+ ECC_ENCIRQ_STA
) & ECC_IRQ_EN
;
126 complete(&ecc
->done
);
132 writel(0, ecc
->regs
+ ECC_IRQ_REG(op
));
137 static void mtk_ecc_config(struct mtk_ecc
*ecc
, struct mtk_ecc_config
*config
)
139 u32 ecc_bit
= ECC_CNFG_4BIT
, dec_sz
, enc_sz
;
142 switch (config
->strength
) {
144 ecc_bit
= ECC_CNFG_4BIT
;
147 ecc_bit
= ECC_CNFG_6BIT
;
150 ecc_bit
= ECC_CNFG_8BIT
;
153 ecc_bit
= ECC_CNFG_10BIT
;
156 ecc_bit
= ECC_CNFG_12BIT
;
159 ecc_bit
= ECC_CNFG_14BIT
;
162 ecc_bit
= ECC_CNFG_16BIT
;
165 ecc_bit
= ECC_CNFG_18BIT
;
168 ecc_bit
= ECC_CNFG_20BIT
;
171 ecc_bit
= ECC_CNFG_22BIT
;
174 ecc_bit
= ECC_CNFG_24BIT
;
177 ecc_bit
= ECC_CNFG_28BIT
;
180 ecc_bit
= ECC_CNFG_32BIT
;
183 ecc_bit
= ECC_CNFG_36BIT
;
186 ecc_bit
= ECC_CNFG_40BIT
;
189 ecc_bit
= ECC_CNFG_44BIT
;
192 ecc_bit
= ECC_CNFG_48BIT
;
195 ecc_bit
= ECC_CNFG_52BIT
;
198 ecc_bit
= ECC_CNFG_56BIT
;
201 ecc_bit
= ECC_CNFG_60BIT
;
204 dev_err(ecc
->dev
, "invalid strength %d, default to 4 bits\n",
208 if (config
->op
== ECC_ENCODE
) {
209 /* configure ECC encoder (in bits) */
210 enc_sz
= config
->len
<< 3;
212 reg
= ecc_bit
| (config
->mode
<< ECC_MODE_SHIFT
);
213 reg
|= (enc_sz
<< ECC_MS_SHIFT
);
214 writel(reg
, ecc
->regs
+ ECC_ENCCNFG
);
216 if (config
->mode
!= ECC_NFI_MODE
)
217 writel(lower_32_bits(config
->addr
),
218 ecc
->regs
+ ECC_ENCDIADDR
);
221 /* configure ECC decoder (in bits) */
222 dec_sz
= (config
->len
<< 3) +
223 config
->strength
* ECC_PARITY_BITS
;
225 reg
= ecc_bit
| (config
->mode
<< ECC_MODE_SHIFT
);
226 reg
|= (dec_sz
<< ECC_MS_SHIFT
) | DEC_CNFG_CORRECT
;
228 writel(reg
, ecc
->regs
+ ECC_DECCNFG
);
231 ecc
->sectors
= 1 << (config
->sectors
- 1);
235 void mtk_ecc_get_stats(struct mtk_ecc
*ecc
, struct mtk_ecc_stats
*stats
,
241 stats
->corrected
= 0;
244 for (i
= 0; i
< sectors
; i
++) {
245 offset
= (i
>> 2) << 2;
246 err
= readl(ecc
->regs
+ ECC_DECENUM0
+ offset
);
247 err
= err
>> ((i
% 4) * 8);
249 if (err
== ERR_MASK
) {
250 /* uncorrectable errors */
255 stats
->corrected
+= err
;
256 bitflips
= max_t(u32
, bitflips
, err
);
259 stats
->bitflips
= bitflips
;
261 EXPORT_SYMBOL(mtk_ecc_get_stats
);
263 void mtk_ecc_release(struct mtk_ecc
*ecc
)
265 clk_disable_unprepare(ecc
->clk
);
266 put_device(ecc
->dev
);
268 EXPORT_SYMBOL(mtk_ecc_release
);
270 static void mtk_ecc_hw_init(struct mtk_ecc
*ecc
)
272 mtk_ecc_wait_idle(ecc
, ECC_ENCODE
);
273 writew(ECC_OP_DISABLE
, ecc
->regs
+ ECC_ENCCON
);
275 mtk_ecc_wait_idle(ecc
, ECC_DECODE
);
276 writel(ECC_OP_DISABLE
, ecc
->regs
+ ECC_DECCON
);
279 static struct mtk_ecc
*mtk_ecc_get(struct device_node
*np
)
281 struct platform_device
*pdev
;
284 pdev
= of_find_device_by_node(np
);
285 if (!pdev
|| !platform_get_drvdata(pdev
))
286 return ERR_PTR(-EPROBE_DEFER
);
288 get_device(&pdev
->dev
);
289 ecc
= platform_get_drvdata(pdev
);
290 clk_prepare_enable(ecc
->clk
);
291 mtk_ecc_hw_init(ecc
);
296 struct mtk_ecc
*of_mtk_ecc_get(struct device_node
*of_node
)
298 struct mtk_ecc
*ecc
= NULL
;
299 struct device_node
*np
;
301 np
= of_parse_phandle(of_node
, "ecc-engine", 0);
303 ecc
= mtk_ecc_get(np
);
309 EXPORT_SYMBOL(of_mtk_ecc_get
);
311 int mtk_ecc_enable(struct mtk_ecc
*ecc
, struct mtk_ecc_config
*config
)
313 enum mtk_ecc_operation op
= config
->op
;
316 ret
= mutex_lock_interruptible(&ecc
->lock
);
318 dev_err(ecc
->dev
, "interrupted when attempting to lock\n");
322 mtk_ecc_wait_idle(ecc
, op
);
323 mtk_ecc_config(ecc
, config
);
324 writew(ECC_OP_ENABLE
, ecc
->regs
+ ECC_CTL_REG(op
));
326 init_completion(&ecc
->done
);
327 writew(ECC_IRQ_EN
, ecc
->regs
+ ECC_IRQ_REG(op
));
331 EXPORT_SYMBOL(mtk_ecc_enable
);
333 void mtk_ecc_disable(struct mtk_ecc
*ecc
)
335 enum mtk_ecc_operation op
= ECC_ENCODE
;
337 /* find out the running operation */
338 if (readw(ecc
->regs
+ ECC_CTL_REG(op
)) != ECC_OP_ENABLE
)
342 mtk_ecc_wait_idle(ecc
, op
);
343 writew(0, ecc
->regs
+ ECC_IRQ_REG(op
));
344 writew(ECC_OP_DISABLE
, ecc
->regs
+ ECC_CTL_REG(op
));
346 mutex_unlock(&ecc
->lock
);
348 EXPORT_SYMBOL(mtk_ecc_disable
);
350 int mtk_ecc_wait_done(struct mtk_ecc
*ecc
, enum mtk_ecc_operation op
)
354 ret
= wait_for_completion_timeout(&ecc
->done
, msecs_to_jiffies(500));
356 dev_err(ecc
->dev
, "%s timeout - interrupt did not arrive)\n",
357 (op
== ECC_ENCODE
) ? "encoder" : "decoder");
363 EXPORT_SYMBOL(mtk_ecc_wait_done
);
365 int mtk_ecc_encode(struct mtk_ecc
*ecc
, struct mtk_ecc_config
*config
,
373 addr
= dma_map_single(ecc
->dev
, data
, bytes
, DMA_TO_DEVICE
);
374 ret
= dma_mapping_error(ecc
->dev
, addr
);
376 dev_err(ecc
->dev
, "dma mapping error\n");
380 config
->op
= ECC_ENCODE
;
382 ret
= mtk_ecc_enable(ecc
, config
);
384 dma_unmap_single(ecc
->dev
, addr
, bytes
, DMA_TO_DEVICE
);
388 ret
= mtk_ecc_wait_done(ecc
, ECC_ENCODE
);
392 mtk_ecc_wait_idle(ecc
, ECC_ENCODE
);
394 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
395 len
= (config
->strength
* ECC_PARITY_BITS
+ 7) >> 3;
398 /* write the parity bytes generated by the ECC back to the OOB region */
399 for (i
= 0; i
< len
; i
++) {
401 val
= readl(ecc
->regs
+ ECC_ENCPAR(i
/ 4));
402 p
[i
] = (val
>> ((i
% 4) * 8)) & 0xff;
406 dma_unmap_single(ecc
->dev
, addr
, bytes
, DMA_TO_DEVICE
);
407 mtk_ecc_disable(ecc
);
411 EXPORT_SYMBOL(mtk_ecc_encode
);
413 void mtk_ecc_adjust_strength(u32
*p
)
415 u32 ecc
[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
416 40, 44, 48, 52, 56, 60};
419 for (i
= 0; i
< ARRAY_SIZE(ecc
); i
++) {
423 else if (*p
!= ecc
[i
])
429 *p
= ecc
[ARRAY_SIZE(ecc
) - 1];
431 EXPORT_SYMBOL(mtk_ecc_adjust_strength
);
433 static int mtk_ecc_probe(struct platform_device
*pdev
)
435 struct device
*dev
= &pdev
->dev
;
437 struct resource
*res
;
440 ecc
= devm_kzalloc(dev
, sizeof(*ecc
), GFP_KERNEL
);
444 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
445 ecc
->regs
= devm_ioremap_resource(dev
, res
);
446 if (IS_ERR(ecc
->regs
)) {
447 dev_err(dev
, "failed to map regs: %ld\n", PTR_ERR(ecc
->regs
));
448 return PTR_ERR(ecc
->regs
);
451 ecc
->clk
= devm_clk_get(dev
, NULL
);
452 if (IS_ERR(ecc
->clk
)) {
453 dev_err(dev
, "failed to get clock: %ld\n", PTR_ERR(ecc
->clk
));
454 return PTR_ERR(ecc
->clk
);
457 irq
= platform_get_irq(pdev
, 0);
459 dev_err(dev
, "failed to get irq\n");
463 ret
= dma_set_mask(dev
, DMA_BIT_MASK(32));
465 dev_err(dev
, "failed to set DMA mask\n");
469 ret
= devm_request_irq(dev
, irq
, mtk_ecc_irq
, 0x0, "mtk-ecc", ecc
);
471 dev_err(dev
, "failed to request irq\n");
476 mutex_init(&ecc
->lock
);
477 platform_set_drvdata(pdev
, ecc
);
478 dev_info(dev
, "probed\n");
483 #ifdef CONFIG_PM_SLEEP
484 static int mtk_ecc_suspend(struct device
*dev
)
486 struct mtk_ecc
*ecc
= dev_get_drvdata(dev
);
488 clk_disable_unprepare(ecc
->clk
);
493 static int mtk_ecc_resume(struct device
*dev
)
495 struct mtk_ecc
*ecc
= dev_get_drvdata(dev
);
498 ret
= clk_prepare_enable(ecc
->clk
);
500 dev_err(dev
, "failed to enable clk\n");
504 mtk_ecc_hw_init(ecc
);
509 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops
, mtk_ecc_suspend
, mtk_ecc_resume
);
512 static const struct of_device_id mtk_ecc_dt_match
[] = {
513 { .compatible
= "mediatek,mt2701-ecc" },
517 MODULE_DEVICE_TABLE(of
, mtk_ecc_dt_match
);
519 static struct platform_driver mtk_ecc_driver
= {
520 .probe
= mtk_ecc_probe
,
523 .of_match_table
= of_match_ptr(mtk_ecc_dt_match
),
524 #ifdef CONFIG_PM_SLEEP
525 .pm
= &mtk_ecc_pm_ops
,
530 module_platform_driver(mtk_ecc_driver
);
532 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
533 MODULE_DESCRIPTION("MTK Nand ECC Driver");
534 MODULE_LICENSE("GPL");