2 * MTK NAND Flash controller driver.
3 * Copyright (C) 2016 MediaTek Inc.
4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/module.h>
25 #include <linux/iopoll.h>
29 /* NAND controller register definition */
30 #define NFI_CNFG (0x00)
31 #define CNFG_AHB BIT(0)
32 #define CNFG_READ_EN BIT(1)
33 #define CNFG_DMA_BURST_EN BIT(2)
34 #define CNFG_BYTE_RW BIT(6)
35 #define CNFG_HW_ECC_EN BIT(8)
36 #define CNFG_AUTO_FMT_EN BIT(9)
37 #define CNFG_OP_CUST (6 << 12)
38 #define NFI_PAGEFMT (0x04)
39 #define PAGEFMT_FDM_ECC_SHIFT (12)
40 #define PAGEFMT_FDM_SHIFT (8)
41 #define PAGEFMT_SPARE_16 (0)
42 #define PAGEFMT_SPARE_26 (1)
43 #define PAGEFMT_SPARE_27 (2)
44 #define PAGEFMT_SPARE_28 (3)
45 #define PAGEFMT_SPARE_32 (4)
46 #define PAGEFMT_SPARE_36 (5)
47 #define PAGEFMT_SPARE_40 (6)
48 #define PAGEFMT_SPARE_44 (7)
49 #define PAGEFMT_SPARE_48 (8)
50 #define PAGEFMT_SPARE_49 (9)
51 #define PAGEFMT_SPARE_50 (0xa)
52 #define PAGEFMT_SPARE_51 (0xb)
53 #define PAGEFMT_SPARE_52 (0xc)
54 #define PAGEFMT_SPARE_62 (0xd)
55 #define PAGEFMT_SPARE_63 (0xe)
56 #define PAGEFMT_SPARE_64 (0xf)
57 #define PAGEFMT_SPARE_SHIFT (4)
58 #define PAGEFMT_SEC_SEL_512 BIT(2)
59 #define PAGEFMT_512_2K (0)
60 #define PAGEFMT_2K_4K (1)
61 #define PAGEFMT_4K_8K (2)
62 #define PAGEFMT_8K_16K (3)
64 #define NFI_CON (0x08)
65 #define CON_FIFO_FLUSH BIT(0)
66 #define CON_NFI_RST BIT(1)
67 #define CON_BRD BIT(8) /* burst read */
68 #define CON_BWR BIT(9) /* burst write */
69 #define CON_SEC_SHIFT (12)
70 /* Timming control register */
71 #define NFI_ACCCON (0x0C)
72 #define NFI_INTR_EN (0x10)
73 #define INTR_AHB_DONE_EN BIT(6)
74 #define NFI_INTR_STA (0x14)
75 #define NFI_CMD (0x20)
76 #define NFI_ADDRNOB (0x30)
77 #define NFI_COLADDR (0x34)
78 #define NFI_ROWADDR (0x38)
79 #define NFI_STRDATA (0x40)
82 #define NFI_CNRNB (0x44)
83 #define NFI_DATAW (0x50)
84 #define NFI_DATAR (0x54)
85 #define NFI_PIO_DIRDY (0x58)
86 #define PIO_DI_RDY (0x01)
87 #define NFI_STA (0x60)
88 #define STA_CMD BIT(0)
89 #define STA_ADDR BIT(1)
90 #define STA_BUSY BIT(8)
91 #define STA_EMP_PAGE BIT(12)
92 #define NFI_FSM_CUSTDATA (0xe << 16)
93 #define NFI_FSM_MASK (0xf << 16)
94 #define NFI_ADDRCNTR (0x70)
95 #define CNTR_MASK GENMASK(16, 12)
96 #define ADDRCNTR_SEC_SHIFT (12)
97 #define ADDRCNTR_SEC(val) \
98 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT)
99 #define NFI_STRADDR (0x80)
100 #define NFI_BYTELEN (0x84)
101 #define NFI_CSEL (0x90)
102 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2)
103 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2)
104 #define NFI_FDM_MAX_SIZE (8)
105 #define NFI_FDM_MIN_SIZE (1)
106 #define NFI_MASTER_STA (0x224)
107 #define MASTER_STA_MASK (0x0FFF)
108 #define NFI_EMPTY_THRESH (0x23C)
110 #define MTK_NAME "mtk-nand"
111 #define KB(x) ((x) * 1024UL)
112 #define MB(x) (KB(x) * 1024UL)
114 #define MTK_TIMEOUT (500000)
115 #define MTK_RESET_TIMEOUT (1000000)
116 #define MTK_MAX_SECTOR (16)
117 #define MTK_NAND_MAX_NSELS (2)
119 struct mtk_nfc_bad_mark_ctl
{
120 void (*bm_swap
)(struct mtd_info
*, u8
*buf
, int raw
);
126 * FDM: region used to store free OOB data
133 struct mtk_nfc_nand_chip
{
134 struct list_head node
;
135 struct nand_chip nand
;
137 struct mtk_nfc_bad_mark_ctl bad_mark
;
138 struct mtk_nfc_fdm fdm
;
139 u32 spare_per_sector
;
143 /* nothing after this field */
152 struct nand_hw_control controller
;
153 struct mtk_ecc_config ecc_cfg
;
154 struct mtk_nfc_clk clk
;
160 struct completion done
;
161 struct list_head chips
;
166 static inline struct mtk_nfc_nand_chip
*to_mtk_nand(struct nand_chip
*nand
)
168 return container_of(nand
, struct mtk_nfc_nand_chip
, nand
);
171 static inline u8
*data_ptr(struct nand_chip
*chip
, const u8
*p
, int i
)
173 return (u8
*)p
+ i
* chip
->ecc
.size
;
176 static inline u8
*oob_ptr(struct nand_chip
*chip
, int i
)
178 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
181 /* map the sector's FDM data to free oob:
182 * the beginning of the oob area stores the FDM data of bad mark sectors
185 if (i
< mtk_nand
->bad_mark
.sec
)
186 poi
= chip
->oob_poi
+ (i
+ 1) * mtk_nand
->fdm
.reg_size
;
187 else if (i
== mtk_nand
->bad_mark
.sec
)
190 poi
= chip
->oob_poi
+ i
* mtk_nand
->fdm
.reg_size
;
195 static inline int mtk_data_len(struct nand_chip
*chip
)
197 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
199 return chip
->ecc
.size
+ mtk_nand
->spare_per_sector
;
202 static inline u8
*mtk_data_ptr(struct nand_chip
*chip
, int i
)
204 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
206 return nfc
->buffer
+ i
* mtk_data_len(chip
);
209 static inline u8
*mtk_oob_ptr(struct nand_chip
*chip
, int i
)
211 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
213 return nfc
->buffer
+ i
* mtk_data_len(chip
) + chip
->ecc
.size
;
216 static inline void nfi_writel(struct mtk_nfc
*nfc
, u32 val
, u32 reg
)
218 writel(val
, nfc
->regs
+ reg
);
221 static inline void nfi_writew(struct mtk_nfc
*nfc
, u16 val
, u32 reg
)
223 writew(val
, nfc
->regs
+ reg
);
226 static inline void nfi_writeb(struct mtk_nfc
*nfc
, u8 val
, u32 reg
)
228 writeb(val
, nfc
->regs
+ reg
);
231 static inline u32
nfi_readl(struct mtk_nfc
*nfc
, u32 reg
)
233 return readl_relaxed(nfc
->regs
+ reg
);
236 static inline u16
nfi_readw(struct mtk_nfc
*nfc
, u32 reg
)
238 return readw_relaxed(nfc
->regs
+ reg
);
241 static inline u8
nfi_readb(struct mtk_nfc
*nfc
, u32 reg
)
243 return readb_relaxed(nfc
->regs
+ reg
);
246 static void mtk_nfc_hw_reset(struct mtk_nfc
*nfc
)
248 struct device
*dev
= nfc
->dev
;
252 /* reset all registers and force the NFI master to terminate */
253 nfi_writel(nfc
, CON_FIFO_FLUSH
| CON_NFI_RST
, NFI_CON
);
255 /* wait for the master to finish the last transaction */
256 ret
= readl_poll_timeout(nfc
->regs
+ NFI_MASTER_STA
, val
,
257 !(val
& MASTER_STA_MASK
), 50,
260 dev_warn(dev
, "master active in reset [0x%x] = 0x%x\n",
261 NFI_MASTER_STA
, val
);
263 /* ensure any status register affected by the NFI master is reset */
264 nfi_writel(nfc
, CON_FIFO_FLUSH
| CON_NFI_RST
, NFI_CON
);
265 nfi_writew(nfc
, STAR_DE
, NFI_STRDATA
);
268 static int mtk_nfc_send_command(struct mtk_nfc
*nfc
, u8 command
)
270 struct device
*dev
= nfc
->dev
;
274 nfi_writel(nfc
, command
, NFI_CMD
);
276 ret
= readl_poll_timeout_atomic(nfc
->regs
+ NFI_STA
, val
,
277 !(val
& STA_CMD
), 10, MTK_TIMEOUT
);
279 dev_warn(dev
, "nfi core timed out entering command mode\n");
286 static int mtk_nfc_send_address(struct mtk_nfc
*nfc
, int addr
)
288 struct device
*dev
= nfc
->dev
;
292 nfi_writel(nfc
, addr
, NFI_COLADDR
);
293 nfi_writel(nfc
, 0, NFI_ROWADDR
);
294 nfi_writew(nfc
, 1, NFI_ADDRNOB
);
296 ret
= readl_poll_timeout_atomic(nfc
->regs
+ NFI_STA
, val
,
297 !(val
& STA_ADDR
), 10, MTK_TIMEOUT
);
299 dev_warn(dev
, "nfi core timed out entering address mode\n");
306 static int mtk_nfc_hw_runtime_config(struct mtd_info
*mtd
)
308 struct nand_chip
*chip
= mtd_to_nand(mtd
);
309 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
310 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
316 spare
= mtk_nand
->spare_per_sector
;
318 switch (mtd
->writesize
) {
320 fmt
= PAGEFMT_512_2K
| PAGEFMT_SEC_SEL_512
;
323 if (chip
->ecc
.size
== 512)
324 fmt
= PAGEFMT_2K_4K
| PAGEFMT_SEC_SEL_512
;
326 fmt
= PAGEFMT_512_2K
;
329 if (chip
->ecc
.size
== 512)
330 fmt
= PAGEFMT_4K_8K
| PAGEFMT_SEC_SEL_512
;
335 if (chip
->ecc
.size
== 512)
336 fmt
= PAGEFMT_8K_16K
| PAGEFMT_SEC_SEL_512
;
341 fmt
= PAGEFMT_8K_16K
;
344 dev_err(nfc
->dev
, "invalid page len: %d\n", mtd
->writesize
);
349 * the hardware will double the value for this eccsize, so we need to
352 if (chip
->ecc
.size
== 1024)
357 fmt
|= (PAGEFMT_SPARE_16
<< PAGEFMT_SPARE_SHIFT
);
360 fmt
|= (PAGEFMT_SPARE_26
<< PAGEFMT_SPARE_SHIFT
);
363 fmt
|= (PAGEFMT_SPARE_27
<< PAGEFMT_SPARE_SHIFT
);
366 fmt
|= (PAGEFMT_SPARE_28
<< PAGEFMT_SPARE_SHIFT
);
369 fmt
|= (PAGEFMT_SPARE_32
<< PAGEFMT_SPARE_SHIFT
);
372 fmt
|= (PAGEFMT_SPARE_36
<< PAGEFMT_SPARE_SHIFT
);
375 fmt
|= (PAGEFMT_SPARE_40
<< PAGEFMT_SPARE_SHIFT
);
378 fmt
|= (PAGEFMT_SPARE_44
<< PAGEFMT_SPARE_SHIFT
);
381 fmt
|= (PAGEFMT_SPARE_48
<< PAGEFMT_SPARE_SHIFT
);
384 fmt
|= (PAGEFMT_SPARE_49
<< PAGEFMT_SPARE_SHIFT
);
387 fmt
|= (PAGEFMT_SPARE_50
<< PAGEFMT_SPARE_SHIFT
);
390 fmt
|= (PAGEFMT_SPARE_51
<< PAGEFMT_SPARE_SHIFT
);
393 fmt
|= (PAGEFMT_SPARE_52
<< PAGEFMT_SPARE_SHIFT
);
396 fmt
|= (PAGEFMT_SPARE_62
<< PAGEFMT_SPARE_SHIFT
);
399 fmt
|= (PAGEFMT_SPARE_63
<< PAGEFMT_SPARE_SHIFT
);
402 fmt
|= (PAGEFMT_SPARE_64
<< PAGEFMT_SPARE_SHIFT
);
405 dev_err(nfc
->dev
, "invalid spare per sector %d\n", spare
);
409 fmt
|= mtk_nand
->fdm
.reg_size
<< PAGEFMT_FDM_SHIFT
;
410 fmt
|= mtk_nand
->fdm
.ecc_size
<< PAGEFMT_FDM_ECC_SHIFT
;
411 nfi_writew(nfc
, fmt
, NFI_PAGEFMT
);
413 nfc
->ecc_cfg
.strength
= chip
->ecc
.strength
;
414 nfc
->ecc_cfg
.len
= chip
->ecc
.size
+ mtk_nand
->fdm
.ecc_size
;
419 static void mtk_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
421 struct nand_chip
*nand
= mtd_to_nand(mtd
);
422 struct mtk_nfc
*nfc
= nand_get_controller_data(nand
);
423 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(nand
);
428 mtk_nfc_hw_runtime_config(mtd
);
430 nfi_writel(nfc
, mtk_nand
->sels
[chip
], NFI_CSEL
);
433 static int mtk_nfc_dev_ready(struct mtd_info
*mtd
)
435 struct mtk_nfc
*nfc
= nand_get_controller_data(mtd_to_nand(mtd
));
437 if (nfi_readl(nfc
, NFI_STA
) & STA_BUSY
)
443 static void mtk_nfc_cmd_ctrl(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
)
445 struct mtk_nfc
*nfc
= nand_get_controller_data(mtd_to_nand(mtd
));
447 if (ctrl
& NAND_ALE
) {
448 mtk_nfc_send_address(nfc
, dat
);
449 } else if (ctrl
& NAND_CLE
) {
450 mtk_nfc_hw_reset(nfc
);
452 nfi_writew(nfc
, CNFG_OP_CUST
, NFI_CNFG
);
453 mtk_nfc_send_command(nfc
, dat
);
457 static inline void mtk_nfc_wait_ioready(struct mtk_nfc
*nfc
)
462 rc
= readb_poll_timeout_atomic(nfc
->regs
+ NFI_PIO_DIRDY
, val
,
463 val
& PIO_DI_RDY
, 10, MTK_TIMEOUT
);
465 dev_err(nfc
->dev
, "data not ready\n");
468 static inline u8
mtk_nfc_read_byte(struct mtd_info
*mtd
)
470 struct nand_chip
*chip
= mtd_to_nand(mtd
);
471 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
474 /* after each byte read, the NFI_STA reg is reset by the hardware */
475 reg
= nfi_readl(nfc
, NFI_STA
) & NFI_FSM_MASK
;
476 if (reg
!= NFI_FSM_CUSTDATA
) {
477 reg
= nfi_readw(nfc
, NFI_CNFG
);
478 reg
|= CNFG_BYTE_RW
| CNFG_READ_EN
;
479 nfi_writew(nfc
, reg
, NFI_CNFG
);
482 * set to max sector to allow the HW to continue reading over
485 reg
= (MTK_MAX_SECTOR
<< CON_SEC_SHIFT
) | CON_BRD
;
486 nfi_writel(nfc
, reg
, NFI_CON
);
488 /* trigger to fetch data */
489 nfi_writew(nfc
, STAR_EN
, NFI_STRDATA
);
492 mtk_nfc_wait_ioready(nfc
);
494 return nfi_readb(nfc
, NFI_DATAR
);
497 static void mtk_nfc_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
501 for (i
= 0; i
< len
; i
++)
502 buf
[i
] = mtk_nfc_read_byte(mtd
);
505 static void mtk_nfc_write_byte(struct mtd_info
*mtd
, u8 byte
)
507 struct mtk_nfc
*nfc
= nand_get_controller_data(mtd_to_nand(mtd
));
510 reg
= nfi_readl(nfc
, NFI_STA
) & NFI_FSM_MASK
;
512 if (reg
!= NFI_FSM_CUSTDATA
) {
513 reg
= nfi_readw(nfc
, NFI_CNFG
) | CNFG_BYTE_RW
;
514 nfi_writew(nfc
, reg
, NFI_CNFG
);
516 reg
= MTK_MAX_SECTOR
<< CON_SEC_SHIFT
| CON_BWR
;
517 nfi_writel(nfc
, reg
, NFI_CON
);
519 nfi_writew(nfc
, STAR_EN
, NFI_STRDATA
);
522 mtk_nfc_wait_ioready(nfc
);
523 nfi_writeb(nfc
, byte
, NFI_DATAW
);
526 static void mtk_nfc_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
530 for (i
= 0; i
< len
; i
++)
531 mtk_nfc_write_byte(mtd
, buf
[i
]);
534 static int mtk_nfc_sector_encode(struct nand_chip
*chip
, u8
*data
)
536 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
537 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
538 int size
= chip
->ecc
.size
+ mtk_nand
->fdm
.reg_size
;
540 nfc
->ecc_cfg
.mode
= ECC_DMA_MODE
;
541 nfc
->ecc_cfg
.op
= ECC_ENCODE
;
543 return mtk_ecc_encode(nfc
->ecc
, &nfc
->ecc_cfg
, data
, size
);
546 static void mtk_nfc_no_bad_mark_swap(struct mtd_info
*a
, u8
*b
, int c
)
551 static void mtk_nfc_bad_mark_swap(struct mtd_info
*mtd
, u8
*buf
, int raw
)
553 struct nand_chip
*chip
= mtd_to_nand(mtd
);
554 struct mtk_nfc_nand_chip
*nand
= to_mtk_nand(chip
);
555 u32 bad_pos
= nand
->bad_mark
.pos
;
558 bad_pos
+= nand
->bad_mark
.sec
* mtk_data_len(chip
);
560 bad_pos
+= nand
->bad_mark
.sec
* chip
->ecc
.size
;
562 swap(chip
->oob_poi
[0], buf
[bad_pos
]);
565 static int mtk_nfc_format_subpage(struct mtd_info
*mtd
, u32 offset
,
566 u32 len
, const u8
*buf
)
568 struct nand_chip
*chip
= mtd_to_nand(mtd
);
569 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
570 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
571 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
575 start
= offset
/ chip
->ecc
.size
;
576 end
= DIV_ROUND_UP(offset
+ len
, chip
->ecc
.size
);
578 memset(nfc
->buffer
, 0xff, mtd
->writesize
+ mtd
->oobsize
);
579 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
580 memcpy(mtk_data_ptr(chip
, i
), data_ptr(chip
, buf
, i
),
583 if (start
> i
|| i
>= end
)
586 if (i
== mtk_nand
->bad_mark
.sec
)
587 mtk_nand
->bad_mark
.bm_swap(mtd
, nfc
->buffer
, 1);
589 memcpy(mtk_oob_ptr(chip
, i
), oob_ptr(chip
, i
), fdm
->reg_size
);
591 /* program the CRC back to the OOB */
592 ret
= mtk_nfc_sector_encode(chip
, mtk_data_ptr(chip
, i
));
600 static void mtk_nfc_format_page(struct mtd_info
*mtd
, const u8
*buf
)
602 struct nand_chip
*chip
= mtd_to_nand(mtd
);
603 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
604 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
605 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
608 memset(nfc
->buffer
, 0xff, mtd
->writesize
+ mtd
->oobsize
);
609 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
611 memcpy(mtk_data_ptr(chip
, i
), data_ptr(chip
, buf
, i
),
614 if (i
== mtk_nand
->bad_mark
.sec
)
615 mtk_nand
->bad_mark
.bm_swap(mtd
, nfc
->buffer
, 1);
617 memcpy(mtk_oob_ptr(chip
, i
), oob_ptr(chip
, i
), fdm
->reg_size
);
621 static inline void mtk_nfc_read_fdm(struct nand_chip
*chip
, u32 start
,
624 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
625 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
626 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
631 for (i
= 0; i
< sectors
; i
++) {
632 oobptr
= oob_ptr(chip
, start
+ i
);
633 vall
= nfi_readl(nfc
, NFI_FDML(i
));
634 valm
= nfi_readl(nfc
, NFI_FDMM(i
));
636 for (j
= 0; j
< fdm
->reg_size
; j
++)
637 oobptr
[j
] = (j
>= 4 ? valm
: vall
) >> ((j
% 4) * 8);
641 static inline void mtk_nfc_write_fdm(struct nand_chip
*chip
)
643 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
644 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
645 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
650 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
651 oobptr
= oob_ptr(chip
, i
);
654 for (j
= 0; j
< 8; j
++) {
656 vall
|= (j
< fdm
->reg_size
? oobptr
[j
] : 0xff)
659 valm
|= (j
< fdm
->reg_size
? oobptr
[j
] : 0xff)
662 nfi_writel(nfc
, vall
, NFI_FDML(i
));
663 nfi_writel(nfc
, valm
, NFI_FDMM(i
));
667 static int mtk_nfc_do_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
668 const u8
*buf
, int page
, int len
)
670 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
671 struct device
*dev
= nfc
->dev
;
676 addr
= dma_map_single(dev
, (void *)buf
, len
, DMA_TO_DEVICE
);
677 ret
= dma_mapping_error(nfc
->dev
, addr
);
679 dev_err(nfc
->dev
, "dma mapping error\n");
683 reg
= nfi_readw(nfc
, NFI_CNFG
) | CNFG_AHB
| CNFG_DMA_BURST_EN
;
684 nfi_writew(nfc
, reg
, NFI_CNFG
);
686 nfi_writel(nfc
, chip
->ecc
.steps
<< CON_SEC_SHIFT
, NFI_CON
);
687 nfi_writel(nfc
, lower_32_bits(addr
), NFI_STRADDR
);
688 nfi_writew(nfc
, INTR_AHB_DONE_EN
, NFI_INTR_EN
);
690 init_completion(&nfc
->done
);
692 reg
= nfi_readl(nfc
, NFI_CON
) | CON_BWR
;
693 nfi_writel(nfc
, reg
, NFI_CON
);
694 nfi_writew(nfc
, STAR_EN
, NFI_STRDATA
);
696 ret
= wait_for_completion_timeout(&nfc
->done
, msecs_to_jiffies(500));
698 dev_err(dev
, "program ahb done timeout\n");
699 nfi_writew(nfc
, 0, NFI_INTR_EN
);
704 ret
= readl_poll_timeout_atomic(nfc
->regs
+ NFI_ADDRCNTR
, reg
,
705 ADDRCNTR_SEC(reg
) >= chip
->ecc
.steps
,
708 dev_err(dev
, "hwecc write timeout\n");
712 dma_unmap_single(nfc
->dev
, addr
, len
, DMA_TO_DEVICE
);
713 nfi_writel(nfc
, 0, NFI_CON
);
718 static int mtk_nfc_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
719 const u8
*buf
, int page
, int raw
)
721 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
722 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
729 /* OOB => FDM: from register, ECC: from HW */
730 reg
= nfi_readw(nfc
, NFI_CNFG
) | CNFG_AUTO_FMT_EN
;
731 nfi_writew(nfc
, reg
| CNFG_HW_ECC_EN
, NFI_CNFG
);
733 nfc
->ecc_cfg
.op
= ECC_ENCODE
;
734 nfc
->ecc_cfg
.mode
= ECC_NFI_MODE
;
735 ret
= mtk_ecc_enable(nfc
->ecc
, &nfc
->ecc_cfg
);
737 /* clear NFI config */
738 reg
= nfi_readw(nfc
, NFI_CNFG
);
739 reg
&= ~(CNFG_AUTO_FMT_EN
| CNFG_HW_ECC_EN
);
740 nfi_writew(nfc
, reg
, NFI_CNFG
);
745 memcpy(nfc
->buffer
, buf
, mtd
->writesize
);
746 mtk_nand
->bad_mark
.bm_swap(mtd
, nfc
->buffer
, raw
);
747 bufpoi
= nfc
->buffer
;
749 /* write OOB into the FDM registers (OOB area in MTK NAND) */
750 mtk_nfc_write_fdm(chip
);
755 len
= mtd
->writesize
+ (raw
? mtd
->oobsize
: 0);
756 ret
= mtk_nfc_do_write_page(mtd
, chip
, bufpoi
, page
, len
);
759 mtk_ecc_disable(nfc
->ecc
);
764 static int mtk_nfc_write_page_hwecc(struct mtd_info
*mtd
,
765 struct nand_chip
*chip
, const u8
*buf
,
766 int oob_on
, int page
)
768 return mtk_nfc_write_page(mtd
, chip
, buf
, page
, 0);
771 static int mtk_nfc_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
772 const u8
*buf
, int oob_on
, int pg
)
774 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
776 mtk_nfc_format_page(mtd
, buf
);
777 return mtk_nfc_write_page(mtd
, chip
, nfc
->buffer
, pg
, 1);
780 static int mtk_nfc_write_subpage_hwecc(struct mtd_info
*mtd
,
781 struct nand_chip
*chip
, u32 offset
,
782 u32 data_len
, const u8
*buf
,
783 int oob_on
, int page
)
785 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
788 ret
= mtk_nfc_format_subpage(mtd
, offset
, data_len
, buf
);
792 /* use the data in the private buffer (now with FDM and CRC) */
793 return mtk_nfc_write_page(mtd
, chip
, nfc
->buffer
, page
, 1);
796 static int mtk_nfc_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
801 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
803 ret
= mtk_nfc_write_page_raw(mtd
, chip
, NULL
, 1, page
);
807 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
808 ret
= chip
->waitfunc(mtd
, chip
);
810 return ret
& NAND_STATUS_FAIL
? -EIO
: 0;
813 static int mtk_nfc_update_ecc_stats(struct mtd_info
*mtd
, u8
*buf
, u32 sectors
)
815 struct nand_chip
*chip
= mtd_to_nand(mtd
);
816 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
817 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
818 struct mtk_ecc_stats stats
;
821 rc
= nfi_readl(nfc
, NFI_STA
) & STA_EMP_PAGE
;
823 memset(buf
, 0xff, sectors
* chip
->ecc
.size
);
824 for (i
= 0; i
< sectors
; i
++)
825 memset(oob_ptr(chip
, i
), 0xff, mtk_nand
->fdm
.reg_size
);
829 mtk_ecc_get_stats(nfc
->ecc
, &stats
, sectors
);
830 mtd
->ecc_stats
.corrected
+= stats
.corrected
;
831 mtd
->ecc_stats
.failed
+= stats
.failed
;
833 return stats
.bitflips
;
836 static int mtk_nfc_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
837 u32 data_offs
, u32 readlen
,
838 u8
*bufpoi
, int page
, int raw
)
840 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
841 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
842 u32 spare
= mtk_nand
->spare_per_sector
;
843 u32 column
, sectors
, start
, end
, reg
;
850 start
= data_offs
/ chip
->ecc
.size
;
851 end
= DIV_ROUND_UP(data_offs
+ readlen
, chip
->ecc
.size
);
853 sectors
= end
- start
;
854 column
= start
* (chip
->ecc
.size
+ spare
);
856 len
= sectors
* chip
->ecc
.size
+ (raw
? sectors
* spare
: 0);
857 buf
= bufpoi
+ start
* chip
->ecc
.size
;
860 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, column
, -1);
862 addr
= dma_map_single(nfc
->dev
, buf
, len
, DMA_FROM_DEVICE
);
863 rc
= dma_mapping_error(nfc
->dev
, addr
);
865 dev_err(nfc
->dev
, "dma mapping error\n");
870 reg
= nfi_readw(nfc
, NFI_CNFG
);
871 reg
|= CNFG_READ_EN
| CNFG_DMA_BURST_EN
| CNFG_AHB
;
873 reg
|= CNFG_AUTO_FMT_EN
| CNFG_HW_ECC_EN
;
874 nfi_writew(nfc
, reg
, NFI_CNFG
);
876 nfc
->ecc_cfg
.mode
= ECC_NFI_MODE
;
877 nfc
->ecc_cfg
.sectors
= sectors
;
878 nfc
->ecc_cfg
.op
= ECC_DECODE
;
879 rc
= mtk_ecc_enable(nfc
->ecc
, &nfc
->ecc_cfg
);
881 dev_err(nfc
->dev
, "ecc enable\n");
883 reg
&= ~(CNFG_DMA_BURST_EN
| CNFG_AHB
| CNFG_READ_EN
|
884 CNFG_AUTO_FMT_EN
| CNFG_HW_ECC_EN
);
885 nfi_writew(nfc
, reg
, NFI_CNFG
);
886 dma_unmap_single(nfc
->dev
, addr
, len
, DMA_FROM_DEVICE
);
891 nfi_writew(nfc
, reg
, NFI_CNFG
);
894 nfi_writel(nfc
, sectors
<< CON_SEC_SHIFT
, NFI_CON
);
895 nfi_writew(nfc
, INTR_AHB_DONE_EN
, NFI_INTR_EN
);
896 nfi_writel(nfc
, lower_32_bits(addr
), NFI_STRADDR
);
898 init_completion(&nfc
->done
);
899 reg
= nfi_readl(nfc
, NFI_CON
) | CON_BRD
;
900 nfi_writel(nfc
, reg
, NFI_CON
);
901 nfi_writew(nfc
, STAR_EN
, NFI_STRDATA
);
903 rc
= wait_for_completion_timeout(&nfc
->done
, msecs_to_jiffies(500));
905 dev_warn(nfc
->dev
, "read ahb/dma done timeout\n");
907 rc
= readl_poll_timeout_atomic(nfc
->regs
+ NFI_BYTELEN
, reg
,
908 ADDRCNTR_SEC(reg
) >= sectors
, 10,
911 dev_err(nfc
->dev
, "subpage done timeout\n");
916 rc
= mtk_ecc_wait_done(nfc
->ecc
, ECC_DECODE
);
917 bitflips
= rc
< 0 ? -ETIMEDOUT
:
918 mtk_nfc_update_ecc_stats(mtd
, buf
, sectors
);
919 mtk_nfc_read_fdm(chip
, start
, sectors
);
923 dma_unmap_single(nfc
->dev
, addr
, len
, DMA_FROM_DEVICE
);
928 mtk_ecc_disable(nfc
->ecc
);
930 if (clamp(mtk_nand
->bad_mark
.sec
, start
, end
) == mtk_nand
->bad_mark
.sec
)
931 mtk_nand
->bad_mark
.bm_swap(mtd
, bufpoi
, raw
);
933 nfi_writel(nfc
, 0, NFI_CON
);
938 static int mtk_nfc_read_subpage_hwecc(struct mtd_info
*mtd
,
939 struct nand_chip
*chip
, u32 off
,
940 u32 len
, u8
*p
, int pg
)
942 return mtk_nfc_read_subpage(mtd
, chip
, off
, len
, p
, pg
, 0);
945 static int mtk_nfc_read_page_hwecc(struct mtd_info
*mtd
,
946 struct nand_chip
*chip
, u8
*p
,
949 return mtk_nfc_read_subpage(mtd
, chip
, 0, mtd
->writesize
, p
, pg
, 0);
952 static int mtk_nfc_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
953 u8
*buf
, int oob_on
, int page
)
955 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
956 struct mtk_nfc
*nfc
= nand_get_controller_data(chip
);
957 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
960 memset(nfc
->buffer
, 0xff, mtd
->writesize
+ mtd
->oobsize
);
961 ret
= mtk_nfc_read_subpage(mtd
, chip
, 0, mtd
->writesize
, nfc
->buffer
,
966 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
967 memcpy(oob_ptr(chip
, i
), mtk_oob_ptr(chip
, i
), fdm
->reg_size
);
969 if (i
== mtk_nand
->bad_mark
.sec
)
970 mtk_nand
->bad_mark
.bm_swap(mtd
, nfc
->buffer
, 1);
973 memcpy(data_ptr(chip
, buf
, i
), mtk_data_ptr(chip
, i
),
980 static int mtk_nfc_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
983 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
985 return mtk_nfc_read_page_raw(mtd
, chip
, NULL
, 1, page
);
988 static inline void mtk_nfc_hw_init(struct mtk_nfc
*nfc
)
991 * ACCON: access timing control register
992 * -------------------------------------
993 * 31:28: minimum required time for CS post pulling down after accessing
995 * 27:22: minimum required time for CS pre pulling down before accessing
997 * 21:16: minimum required time from NCEB low to NREB low
998 * 15:12: minimum required time from NWEB high to NREB low.
999 * 11:08: write enable hold time
1000 * 07:04: write wait states
1001 * 03:00: read wait states
1003 nfi_writel(nfc
, 0x10804211, NFI_ACCCON
);
1006 * CNRNB: nand ready/busy register
1007 * -------------------------------
1008 * 7:4: timeout register for polling the NAND busy/ready signal
1009 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
1011 nfi_writew(nfc
, 0xf1, NFI_CNRNB
);
1012 nfi_writew(nfc
, PAGEFMT_8K_16K
, NFI_PAGEFMT
);
1014 mtk_nfc_hw_reset(nfc
);
1016 nfi_readl(nfc
, NFI_INTR_STA
);
1017 nfi_writel(nfc
, 0, NFI_INTR_EN
);
1020 static irqreturn_t
mtk_nfc_irq(int irq
, void *id
)
1022 struct mtk_nfc
*nfc
= id
;
1025 sta
= nfi_readw(nfc
, NFI_INTR_STA
);
1026 ien
= nfi_readw(nfc
, NFI_INTR_EN
);
1031 nfi_writew(nfc
, ~sta
& ien
, NFI_INTR_EN
);
1032 complete(&nfc
->done
);
1037 static int mtk_nfc_enable_clk(struct device
*dev
, struct mtk_nfc_clk
*clk
)
1041 ret
= clk_prepare_enable(clk
->nfi_clk
);
1043 dev_err(dev
, "failed to enable nfi clk\n");
1047 ret
= clk_prepare_enable(clk
->pad_clk
);
1049 dev_err(dev
, "failed to enable pad clk\n");
1050 clk_disable_unprepare(clk
->nfi_clk
);
1057 static void mtk_nfc_disable_clk(struct mtk_nfc_clk
*clk
)
1059 clk_disable_unprepare(clk
->nfi_clk
);
1060 clk_disable_unprepare(clk
->pad_clk
);
1063 static int mtk_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
1064 struct mtd_oob_region
*oob_region
)
1066 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1067 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
1068 struct mtk_nfc_fdm
*fdm
= &mtk_nand
->fdm
;
1071 eccsteps
= mtd
->writesize
/ chip
->ecc
.size
;
1073 if (section
>= eccsteps
)
1076 oob_region
->length
= fdm
->reg_size
- fdm
->ecc_size
;
1077 oob_region
->offset
= section
* fdm
->reg_size
+ fdm
->ecc_size
;
1082 static int mtk_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1083 struct mtd_oob_region
*oob_region
)
1085 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1086 struct mtk_nfc_nand_chip
*mtk_nand
= to_mtk_nand(chip
);
1092 eccsteps
= mtd
->writesize
/ chip
->ecc
.size
;
1093 oob_region
->offset
= mtk_nand
->fdm
.reg_size
* eccsteps
;
1094 oob_region
->length
= mtd
->oobsize
- oob_region
->offset
;
1099 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops
= {
1100 .free
= mtk_nfc_ooblayout_free
,
1101 .ecc
= mtk_nfc_ooblayout_ecc
,
1104 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm
*fdm
, struct mtd_info
*mtd
)
1106 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1107 struct mtk_nfc_nand_chip
*chip
= to_mtk_nand(nand
);
1110 ecc_bytes
= DIV_ROUND_UP(nand
->ecc
.strength
* ECC_PARITY_BITS
, 8);
1112 fdm
->reg_size
= chip
->spare_per_sector
- ecc_bytes
;
1113 if (fdm
->reg_size
> NFI_FDM_MAX_SIZE
)
1114 fdm
->reg_size
= NFI_FDM_MAX_SIZE
;
1116 /* bad block mark storage */
1120 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl
*bm_ctl
,
1121 struct mtd_info
*mtd
)
1123 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1125 if (mtd
->writesize
== 512) {
1126 bm_ctl
->bm_swap
= mtk_nfc_no_bad_mark_swap
;
1128 bm_ctl
->bm_swap
= mtk_nfc_bad_mark_swap
;
1129 bm_ctl
->sec
= mtd
->writesize
/ mtk_data_len(nand
);
1130 bm_ctl
->pos
= mtd
->writesize
% mtk_data_len(nand
);
1134 static void mtk_nfc_set_spare_per_sector(u32
*sps
, struct mtd_info
*mtd
)
1136 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1137 u32 spare
[] = {16, 26, 27, 28, 32, 36, 40, 44,
1138 48, 49, 50, 51, 52, 62, 63, 64};
1141 eccsteps
= mtd
->writesize
/ nand
->ecc
.size
;
1142 *sps
= mtd
->oobsize
/ eccsteps
;
1144 if (nand
->ecc
.size
== 1024)
1147 for (i
= 0; i
< ARRAY_SIZE(spare
); i
++) {
1148 if (*sps
<= spare
[i
]) {
1151 else if (*sps
!= spare
[i
])
1152 *sps
= spare
[i
- 1];
1157 if (i
>= ARRAY_SIZE(spare
))
1158 *sps
= spare
[ARRAY_SIZE(spare
) - 1];
1160 if (nand
->ecc
.size
== 1024)
1164 static int mtk_nfc_ecc_init(struct device
*dev
, struct mtd_info
*mtd
)
1166 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1170 /* support only ecc hw mode */
1171 if (nand
->ecc
.mode
!= NAND_ECC_HW
) {
1172 dev_err(dev
, "ecc.mode not supported\n");
1176 /* if optional dt settings not present */
1177 if (!nand
->ecc
.size
|| !nand
->ecc
.strength
) {
1178 /* use datasheet requirements */
1179 nand
->ecc
.strength
= nand
->ecc_strength_ds
;
1180 nand
->ecc
.size
= nand
->ecc_step_ds
;
1183 * align eccstrength and eccsize
1184 * this controller only supports 512 and 1024 sizes
1186 if (nand
->ecc
.size
< 1024) {
1187 if (mtd
->writesize
> 512) {
1188 nand
->ecc
.size
= 1024;
1189 nand
->ecc
.strength
<<= 1;
1191 nand
->ecc
.size
= 512;
1194 nand
->ecc
.size
= 1024;
1197 mtk_nfc_set_spare_per_sector(&spare
, mtd
);
1199 /* calculate oob bytes except ecc parity data */
1200 free
= ((nand
->ecc
.strength
* ECC_PARITY_BITS
) + 7) >> 3;
1201 free
= spare
- free
;
1204 * enhance ecc strength if oob left is bigger than max FDM size
1205 * or reduce ecc strength if oob size is not enough for ecc
1208 if (free
> NFI_FDM_MAX_SIZE
) {
1209 spare
-= NFI_FDM_MAX_SIZE
;
1210 nand
->ecc
.strength
= (spare
<< 3) / ECC_PARITY_BITS
;
1211 } else if (free
< 0) {
1212 spare
-= NFI_FDM_MIN_SIZE
;
1213 nand
->ecc
.strength
= (spare
<< 3) / ECC_PARITY_BITS
;
1217 mtk_ecc_adjust_strength(&nand
->ecc
.strength
);
1219 dev_info(dev
, "eccsize %d eccstrength %d\n",
1220 nand
->ecc
.size
, nand
->ecc
.strength
);
1225 static int mtk_nfc_nand_chip_init(struct device
*dev
, struct mtk_nfc
*nfc
,
1226 struct device_node
*np
)
1228 struct mtk_nfc_nand_chip
*chip
;
1229 struct nand_chip
*nand
;
1230 struct mtd_info
*mtd
;
1236 if (!of_get_property(np
, "reg", &nsels
))
1239 nsels
/= sizeof(u32
);
1240 if (!nsels
|| nsels
> MTK_NAND_MAX_NSELS
) {
1241 dev_err(dev
, "invalid reg property size %d\n", nsels
);
1245 chip
= devm_kzalloc(dev
, sizeof(*chip
) + nsels
* sizeof(u8
),
1250 chip
->nsels
= nsels
;
1251 for (i
= 0; i
< nsels
; i
++) {
1252 ret
= of_property_read_u32_index(np
, "reg", i
, &tmp
);
1254 dev_err(dev
, "reg property failure : %d\n", ret
);
1257 chip
->sels
[i
] = tmp
;
1261 nand
->controller
= &nfc
->controller
;
1263 nand_set_flash_node(nand
, np
);
1264 nand_set_controller_data(nand
, nfc
);
1266 nand
->options
|= NAND_USE_BOUNCE_BUFFER
| NAND_SUBPAGE_READ
;
1267 nand
->dev_ready
= mtk_nfc_dev_ready
;
1268 nand
->select_chip
= mtk_nfc_select_chip
;
1269 nand
->write_byte
= mtk_nfc_write_byte
;
1270 nand
->write_buf
= mtk_nfc_write_buf
;
1271 nand
->read_byte
= mtk_nfc_read_byte
;
1272 nand
->read_buf
= mtk_nfc_read_buf
;
1273 nand
->cmd_ctrl
= mtk_nfc_cmd_ctrl
;
1275 /* set default mode in case dt entry is missing */
1276 nand
->ecc
.mode
= NAND_ECC_HW
;
1278 nand
->ecc
.write_subpage
= mtk_nfc_write_subpage_hwecc
;
1279 nand
->ecc
.write_page_raw
= mtk_nfc_write_page_raw
;
1280 nand
->ecc
.write_page
= mtk_nfc_write_page_hwecc
;
1281 nand
->ecc
.write_oob_raw
= mtk_nfc_write_oob_std
;
1282 nand
->ecc
.write_oob
= mtk_nfc_write_oob_std
;
1284 nand
->ecc
.read_subpage
= mtk_nfc_read_subpage_hwecc
;
1285 nand
->ecc
.read_page_raw
= mtk_nfc_read_page_raw
;
1286 nand
->ecc
.read_page
= mtk_nfc_read_page_hwecc
;
1287 nand
->ecc
.read_oob_raw
= mtk_nfc_read_oob_std
;
1288 nand
->ecc
.read_oob
= mtk_nfc_read_oob_std
;
1290 mtd
= nand_to_mtd(nand
);
1291 mtd
->owner
= THIS_MODULE
;
1292 mtd
->dev
.parent
= dev
;
1293 mtd
->name
= MTK_NAME
;
1294 mtd_set_ooblayout(mtd
, &mtk_nfc_ooblayout_ops
);
1296 mtk_nfc_hw_init(nfc
);
1298 ret
= nand_scan_ident(mtd
, nsels
, NULL
);
1302 /* store bbt magic in page, cause OOB is not protected */
1303 if (nand
->bbt_options
& NAND_BBT_USE_FLASH
)
1304 nand
->bbt_options
|= NAND_BBT_NO_OOB
;
1306 ret
= mtk_nfc_ecc_init(dev
, mtd
);
1310 if (nand
->options
& NAND_BUSWIDTH_16
) {
1311 dev_err(dev
, "16bits buswidth not supported");
1315 mtk_nfc_set_spare_per_sector(&chip
->spare_per_sector
, mtd
);
1316 mtk_nfc_set_fdm(&chip
->fdm
, mtd
);
1317 mtk_nfc_set_bad_mark_ctl(&chip
->bad_mark
, mtd
);
1319 len
= mtd
->writesize
+ mtd
->oobsize
;
1320 nfc
->buffer
= devm_kzalloc(dev
, len
, GFP_KERNEL
);
1324 ret
= nand_scan_tail(mtd
);
1328 ret
= mtd_device_parse_register(mtd
, NULL
, NULL
, NULL
, 0);
1330 dev_err(dev
, "mtd parse partition error\n");
1335 list_add_tail(&chip
->node
, &nfc
->chips
);
1340 static int mtk_nfc_nand_chips_init(struct device
*dev
, struct mtk_nfc
*nfc
)
1342 struct device_node
*np
= dev
->of_node
;
1343 struct device_node
*nand_np
;
1346 for_each_child_of_node(np
, nand_np
) {
1347 ret
= mtk_nfc_nand_chip_init(dev
, nfc
, nand_np
);
1349 of_node_put(nand_np
);
1357 static int mtk_nfc_probe(struct platform_device
*pdev
)
1359 struct device
*dev
= &pdev
->dev
;
1360 struct device_node
*np
= dev
->of_node
;
1361 struct mtk_nfc
*nfc
;
1362 struct resource
*res
;
1365 nfc
= devm_kzalloc(dev
, sizeof(*nfc
), GFP_KERNEL
);
1369 spin_lock_init(&nfc
->controller
.lock
);
1370 init_waitqueue_head(&nfc
->controller
.wq
);
1371 INIT_LIST_HEAD(&nfc
->chips
);
1373 /* probe defer if not ready */
1374 nfc
->ecc
= of_mtk_ecc_get(np
);
1375 if (IS_ERR(nfc
->ecc
))
1376 return PTR_ERR(nfc
->ecc
);
1382 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1383 nfc
->regs
= devm_ioremap_resource(dev
, res
);
1384 if (IS_ERR(nfc
->regs
)) {
1385 ret
= PTR_ERR(nfc
->regs
);
1386 dev_err(dev
, "no nfi base\n");
1390 nfc
->clk
.nfi_clk
= devm_clk_get(dev
, "nfi_clk");
1391 if (IS_ERR(nfc
->clk
.nfi_clk
)) {
1392 dev_err(dev
, "no clk\n");
1393 ret
= PTR_ERR(nfc
->clk
.nfi_clk
);
1397 nfc
->clk
.pad_clk
= devm_clk_get(dev
, "pad_clk");
1398 if (IS_ERR(nfc
->clk
.pad_clk
)) {
1399 dev_err(dev
, "no pad clk\n");
1400 ret
= PTR_ERR(nfc
->clk
.pad_clk
);
1404 ret
= mtk_nfc_enable_clk(dev
, &nfc
->clk
);
1408 irq
= platform_get_irq(pdev
, 0);
1410 dev_err(dev
, "no nfi irq resource\n");
1415 ret
= devm_request_irq(dev
, irq
, mtk_nfc_irq
, 0x0, "mtk-nand", nfc
);
1417 dev_err(dev
, "failed to request nfi irq\n");
1421 ret
= dma_set_mask(dev
, DMA_BIT_MASK(32));
1423 dev_err(dev
, "failed to set dma mask\n");
1427 platform_set_drvdata(pdev
, nfc
);
1429 ret
= mtk_nfc_nand_chips_init(dev
, nfc
);
1431 dev_err(dev
, "failed to init nand chips\n");
1438 mtk_nfc_disable_clk(&nfc
->clk
);
1441 mtk_ecc_release(nfc
->ecc
);
1446 static int mtk_nfc_remove(struct platform_device
*pdev
)
1448 struct mtk_nfc
*nfc
= platform_get_drvdata(pdev
);
1449 struct mtk_nfc_nand_chip
*chip
;
1451 while (!list_empty(&nfc
->chips
)) {
1452 chip
= list_first_entry(&nfc
->chips
, struct mtk_nfc_nand_chip
,
1454 nand_release(nand_to_mtd(&chip
->nand
));
1455 list_del(&chip
->node
);
1458 mtk_ecc_release(nfc
->ecc
);
1459 mtk_nfc_disable_clk(&nfc
->clk
);
1464 #ifdef CONFIG_PM_SLEEP
1465 static int mtk_nfc_suspend(struct device
*dev
)
1467 struct mtk_nfc
*nfc
= dev_get_drvdata(dev
);
1469 mtk_nfc_disable_clk(&nfc
->clk
);
1474 static int mtk_nfc_resume(struct device
*dev
)
1476 struct mtk_nfc
*nfc
= dev_get_drvdata(dev
);
1477 struct mtk_nfc_nand_chip
*chip
;
1478 struct nand_chip
*nand
;
1479 struct mtd_info
*mtd
;
1485 ret
= mtk_nfc_enable_clk(dev
, &nfc
->clk
);
1489 mtk_nfc_hw_init(nfc
);
1491 /* reset NAND chip if VCC was powered off */
1492 list_for_each_entry(chip
, &nfc
->chips
, node
) {
1494 mtd
= nand_to_mtd(nand
);
1495 for (i
= 0; i
< chip
->nsels
; i
++) {
1496 nand
->select_chip(mtd
, i
);
1497 nand
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1504 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops
, mtk_nfc_suspend
, mtk_nfc_resume
);
1507 static const struct of_device_id mtk_nfc_id_table
[] = {
1508 { .compatible
= "mediatek,mt2701-nfc" },
1511 MODULE_DEVICE_TABLE(of
, mtk_nfc_id_table
);
1513 static struct platform_driver mtk_nfc_driver
= {
1514 .probe
= mtk_nfc_probe
,
1515 .remove
= mtk_nfc_remove
,
1518 .of_match_table
= mtk_nfc_id_table
,
1519 #ifdef CONFIG_PM_SLEEP
1520 .pm
= &mtk_nfc_pm_ops
,
1525 module_platform_driver(mtk_nfc_driver
);
1527 MODULE_LICENSE("GPL");
1528 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
1529 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");