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[people/ms/u-boot.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21 #include <common.h>
22 #include <nand.h>
23 #include <linux/err.h>
24 #include <asm/io.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
26 defined(CONFIG_MX51) || defined(CONFIG_MX53)
27 #include <asm/arch/imx-regs.h>
28 #endif
29 #include "mxc_nand.h"
30
31 #define DRIVER_NAME "mxc_nand"
32
33 struct mxc_nand_host {
34 struct mtd_info mtd;
35 struct nand_chip *nand;
36
37 struct mxc_nand_regs __iomem *regs;
38 #ifdef MXC_NFC_V3_2
39 struct mxc_nand_ip_regs __iomem *ip_regs;
40 #endif
41 int spare_only;
42 int status_request;
43 int pagesize_2k;
44 int clk_act;
45 uint16_t col_addr;
46 unsigned int page_addr;
47 };
48
49 static struct mxc_nand_host mxc_host;
50 static struct mxc_nand_host *host = &mxc_host;
51
52 /* Define delays in microsec for NAND device operations */
53 #define TROP_US_DELAY 2000
54 /* Macros to get byte and bit positions of ECC */
55 #define COLPOS(x) ((x) >> 3)
56 #define BITPOS(x) ((x) & 0xf)
57
58 /* Define single bit Error positions in Main & Spare area */
59 #define MAIN_SINGLEBIT_ERROR 0x4
60 #define SPARE_SINGLEBIT_ERROR 0x1
61
62 /* OOB placement block for use with hardware ecc generation */
63 #if defined(MXC_NFC_V1)
64 #ifndef CONFIG_SYS_NAND_LARGEPAGE
65 static struct nand_ecclayout nand_hw_eccoob = {
66 .eccbytes = 5,
67 .eccpos = {6, 7, 8, 9, 10},
68 .oobfree = { {0, 5}, {11, 5}, }
69 };
70 #else
71 static struct nand_ecclayout nand_hw_eccoob2k = {
72 .eccbytes = 20,
73 .eccpos = {
74 6, 7, 8, 9, 10,
75 22, 23, 24, 25, 26,
76 38, 39, 40, 41, 42,
77 54, 55, 56, 57, 58,
78 },
79 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
80 };
81 #endif
82 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
83 #ifndef CONFIG_SYS_NAND_LARGEPAGE
84 static struct nand_ecclayout nand_hw_eccoob = {
85 .eccbytes = 9,
86 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
87 .oobfree = { {2, 5} }
88 };
89 #else
90 static struct nand_ecclayout nand_hw_eccoob2k = {
91 .eccbytes = 36,
92 .eccpos = {
93 7, 8, 9, 10, 11, 12, 13, 14, 15,
94 23, 24, 25, 26, 27, 28, 29, 30, 31,
95 39, 40, 41, 42, 43, 44, 45, 46, 47,
96 55, 56, 57, 58, 59, 60, 61, 62, 63,
97 },
98 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
99 };
100 #endif
101 #endif
102
103 static int is_16bit_nand(void)
104 {
105 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
106 return 1;
107 #else
108 return 0;
109 #endif
110 }
111
112 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
113 {
114 uint32_t *d = dest;
115
116 size >>= 2;
117 while (size--)
118 __raw_writel(__raw_readl(source++), d++);
119 return dest;
120 }
121
122 /*
123 * This function polls the NANDFC to wait for the basic operation to
124 * complete by checking the INT bit.
125 */
126 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
127 uint16_t param)
128 {
129 uint32_t tmp;
130
131 while (max_retries-- > 0) {
132 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
133 tmp = readnfc(&host->regs->config2);
134 if (tmp & NFC_V1_V2_CONFIG2_INT) {
135 tmp &= ~NFC_V1_V2_CONFIG2_INT;
136 writenfc(tmp, &host->regs->config2);
137 #elif defined(MXC_NFC_V3_2)
138 tmp = readnfc(&host->ip_regs->ipc);
139 if (tmp & NFC_V3_IPC_INT) {
140 tmp &= ~NFC_V3_IPC_INT;
141 writenfc(tmp, &host->ip_regs->ipc);
142 #endif
143 break;
144 }
145 udelay(1);
146 }
147 if (max_retries < 0) {
148 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
149 __func__, param);
150 }
151 }
152
153 /*
154 * This function issues the specified command to the NAND device and
155 * waits for completion.
156 */
157 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
158 {
159 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
160
161 writenfc(cmd, &host->regs->flash_cmd);
162 writenfc(NFC_CMD, &host->regs->operation);
163
164 /* Wait for operation to complete */
165 wait_op_done(host, TROP_US_DELAY, cmd);
166 }
167
168 /*
169 * This function sends an address (or partial address) to the
170 * NAND device. The address is used to select the source/destination for
171 * a NAND command.
172 */
173 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
174 {
175 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
176
177 writenfc(addr, &host->regs->flash_addr);
178 writenfc(NFC_ADDR, &host->regs->operation);
179
180 /* Wait for operation to complete */
181 wait_op_done(host, TROP_US_DELAY, addr);
182 }
183
184 /*
185 * This function requests the NANDFC to initiate the transfer
186 * of data currently in the NANDFC RAM buffer to the NAND device.
187 */
188 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
189 int spare_only)
190 {
191 if (spare_only)
192 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
193
194 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
195 int i;
196 /*
197 * The controller copies the 64 bytes of spare data from
198 * the first 16 bytes of each of the 4 64 byte spare buffers.
199 * Copy the contiguous data starting in spare_area[0] to
200 * the four spare area buffers.
201 */
202 for (i = 1; i < 4; i++) {
203 void __iomem *src = &host->regs->spare_area[0][i * 16];
204 void __iomem *dst = &host->regs->spare_area[i][0];
205
206 mxc_nand_memcpy32(dst, src, 16);
207 }
208 }
209
210 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
211 writenfc(buf_id, &host->regs->buf_addr);
212 #elif defined(MXC_NFC_V3_2)
213 uint32_t tmp = readnfc(&host->regs->config1);
214 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
215 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
216 writenfc(tmp, &host->regs->config1);
217 #endif
218
219 /* Configure spare or page+spare access */
220 if (!host->pagesize_2k) {
221 uint32_t config1 = readnfc(&host->regs->config1);
222 if (spare_only)
223 config1 |= NFC_CONFIG1_SP_EN;
224 else
225 config1 &= ~NFC_CONFIG1_SP_EN;
226 writenfc(config1, &host->regs->config1);
227 }
228
229 writenfc(NFC_INPUT, &host->regs->operation);
230
231 /* Wait for operation to complete */
232 wait_op_done(host, TROP_US_DELAY, spare_only);
233 }
234
235 /*
236 * Requests NANDFC to initiate the transfer of data from the
237 * NAND device into in the NANDFC ram buffer.
238 */
239 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
240 int spare_only)
241 {
242 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
243
244 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
245 writenfc(buf_id, &host->regs->buf_addr);
246 #elif defined(MXC_NFC_V3_2)
247 uint32_t tmp = readnfc(&host->regs->config1);
248 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
249 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
250 writenfc(tmp, &host->regs->config1);
251 #endif
252
253 /* Configure spare or page+spare access */
254 if (!host->pagesize_2k) {
255 uint32_t config1 = readnfc(&host->regs->config1);
256 if (spare_only)
257 config1 |= NFC_CONFIG1_SP_EN;
258 else
259 config1 &= ~NFC_CONFIG1_SP_EN;
260 writenfc(config1, &host->regs->config1);
261 }
262
263 writenfc(NFC_OUTPUT, &host->regs->operation);
264
265 /* Wait for operation to complete */
266 wait_op_done(host, TROP_US_DELAY, spare_only);
267
268 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
269 int i;
270
271 /*
272 * The controller copies the 64 bytes of spare data to
273 * the first 16 bytes of each of the 4 spare buffers.
274 * Make the data contiguous starting in spare_area[0].
275 */
276 for (i = 1; i < 4; i++) {
277 void __iomem *src = &host->regs->spare_area[i][0];
278 void __iomem *dst = &host->regs->spare_area[0][i * 16];
279
280 mxc_nand_memcpy32(dst, src, 16);
281 }
282 }
283 }
284
285 /* Request the NANDFC to perform a read of the NAND device ID. */
286 static void send_read_id(struct mxc_nand_host *host)
287 {
288 uint32_t tmp;
289
290 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
291 /* NANDFC buffer 0 is used for device ID output */
292 writenfc(0x0, &host->regs->buf_addr);
293 #elif defined(MXC_NFC_V3_2)
294 tmp = readnfc(&host->regs->config1);
295 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
296 writenfc(tmp, &host->regs->config1);
297 #endif
298
299 /* Read ID into main buffer */
300 tmp = readnfc(&host->regs->config1);
301 tmp &= ~NFC_CONFIG1_SP_EN;
302 writenfc(tmp, &host->regs->config1);
303
304 writenfc(NFC_ID, &host->regs->operation);
305
306 /* Wait for operation to complete */
307 wait_op_done(host, TROP_US_DELAY, 0);
308 }
309
310 /*
311 * This function requests the NANDFC to perform a read of the
312 * NAND device status and returns the current status.
313 */
314 static uint16_t get_dev_status(struct mxc_nand_host *host)
315 {
316 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
317 void __iomem *main_buf = host->regs->main_area[1];
318 uint32_t store;
319 #endif
320 uint32_t ret, tmp;
321 /* Issue status request to NAND device */
322
323 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
324 /* store the main area1 first word, later do recovery */
325 store = readl(main_buf);
326 /* NANDFC buffer 1 is used for device status */
327 writenfc(1, &host->regs->buf_addr);
328 #endif
329
330 /* Read status into main buffer */
331 tmp = readnfc(&host->regs->config1);
332 tmp &= ~NFC_CONFIG1_SP_EN;
333 writenfc(tmp, &host->regs->config1);
334
335 writenfc(NFC_STATUS, &host->regs->operation);
336
337 /* Wait for operation to complete */
338 wait_op_done(host, TROP_US_DELAY, 0);
339
340 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
341 /*
342 * Status is placed in first word of main buffer
343 * get status, then recovery area 1 data
344 */
345 ret = readw(main_buf);
346 writel(store, main_buf);
347 #elif defined(MXC_NFC_V3_2)
348 ret = readnfc(&host->regs->config1) >> 16;
349 #endif
350
351 return ret;
352 }
353
354 /* This function is used by upper layer to checks if device is ready */
355 static int mxc_nand_dev_ready(struct mtd_info *mtd)
356 {
357 /*
358 * NFC handles R/B internally. Therefore, this function
359 * always returns status as ready.
360 */
361 return 1;
362 }
363
364 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
365 {
366 struct nand_chip *nand_chip = mtd->priv;
367 struct mxc_nand_host *host = nand_chip->priv;
368 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
369 uint16_t tmp = readnfc(&host->regs->config1);
370
371 if (on)
372 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
373 else
374 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
375 writenfc(tmp, &host->regs->config1);
376 #elif defined(MXC_NFC_V3_2)
377 uint32_t tmp = readnfc(&host->ip_regs->config2);
378
379 if (on)
380 tmp |= NFC_V3_CONFIG2_ECC_EN;
381 else
382 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
383 writenfc(tmp, &host->ip_regs->config2);
384 #endif
385 }
386
387 #ifdef CONFIG_MXC_NAND_HWECC
388 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
389 {
390 /*
391 * If HW ECC is enabled, we turn it on during init. There is
392 * no need to enable again here.
393 */
394 }
395
396 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
397 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
398 struct nand_chip *chip,
399 int page)
400 {
401 struct mxc_nand_host *host = chip->priv;
402 uint8_t *buf = chip->oob_poi;
403 int length = mtd->oobsize;
404 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
405 uint8_t *bufpoi = buf;
406 int i, toread;
407
408 MTDDEBUG(MTD_DEBUG_LEVEL0,
409 "%s: Reading OOB area of page %u to oob %p\n",
410 __func__, page, buf);
411
412 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
413 for (i = 0; i < chip->ecc.steps; i++) {
414 toread = min_t(int, length, chip->ecc.prepad);
415 if (toread) {
416 chip->read_buf(mtd, bufpoi, toread);
417 bufpoi += toread;
418 length -= toread;
419 }
420 bufpoi += chip->ecc.bytes;
421 host->col_addr += chip->ecc.bytes;
422 length -= chip->ecc.bytes;
423
424 toread = min_t(int, length, chip->ecc.postpad);
425 if (toread) {
426 chip->read_buf(mtd, bufpoi, toread);
427 bufpoi += toread;
428 length -= toread;
429 }
430 }
431 if (length > 0)
432 chip->read_buf(mtd, bufpoi, length);
433
434 _mxc_nand_enable_hwecc(mtd, 0);
435 chip->cmdfunc(mtd, NAND_CMD_READOOB,
436 mtd->writesize + chip->ecc.prepad, page);
437 bufpoi = buf + chip->ecc.prepad;
438 length = mtd->oobsize - chip->ecc.prepad;
439 for (i = 0; i < chip->ecc.steps; i++) {
440 toread = min_t(int, length, chip->ecc.bytes);
441 chip->read_buf(mtd, bufpoi, toread);
442 bufpoi += eccpitch;
443 length -= eccpitch;
444 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
445 }
446 _mxc_nand_enable_hwecc(mtd, 1);
447 return 1;
448 }
449
450 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
451 struct nand_chip *chip,
452 uint8_t *buf,
453 int oob_required,
454 int page)
455 {
456 struct mxc_nand_host *host = chip->priv;
457 int eccsize = chip->ecc.size;
458 int eccbytes = chip->ecc.bytes;
459 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
460 uint8_t *oob = chip->oob_poi;
461 int steps, size;
462 int n;
463
464 _mxc_nand_enable_hwecc(mtd, 0);
465 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
466
467 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
468 host->col_addr = n * eccsize;
469 chip->read_buf(mtd, buf, eccsize);
470 buf += eccsize;
471
472 host->col_addr = mtd->writesize + n * eccpitch;
473 if (chip->ecc.prepad) {
474 chip->read_buf(mtd, oob, chip->ecc.prepad);
475 oob += chip->ecc.prepad;
476 }
477
478 chip->read_buf(mtd, oob, eccbytes);
479 oob += eccbytes;
480
481 if (chip->ecc.postpad) {
482 chip->read_buf(mtd, oob, chip->ecc.postpad);
483 oob += chip->ecc.postpad;
484 }
485 }
486
487 size = mtd->oobsize - (oob - chip->oob_poi);
488 if (size)
489 chip->read_buf(mtd, oob, size);
490 _mxc_nand_enable_hwecc(mtd, 1);
491
492 return 0;
493 }
494
495 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
496 struct nand_chip *chip,
497 uint8_t *buf,
498 int oob_required,
499 int page)
500 {
501 struct mxc_nand_host *host = chip->priv;
502 int n, eccsize = chip->ecc.size;
503 int eccbytes = chip->ecc.bytes;
504 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
505 int eccsteps = chip->ecc.steps;
506 uint8_t *p = buf;
507 uint8_t *oob = chip->oob_poi;
508
509 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
510 page, buf, oob);
511
512 /* first read the data area and the available portion of OOB */
513 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
514 int stat;
515
516 host->col_addr = n * eccsize;
517
518 chip->read_buf(mtd, p, eccsize);
519
520 host->col_addr = mtd->writesize + n * eccpitch;
521
522 if (chip->ecc.prepad) {
523 chip->read_buf(mtd, oob, chip->ecc.prepad);
524 oob += chip->ecc.prepad;
525 }
526
527 stat = chip->ecc.correct(mtd, p, oob, NULL);
528
529 if (stat < 0)
530 mtd->ecc_stats.failed++;
531 else
532 mtd->ecc_stats.corrected += stat;
533 oob += eccbytes;
534
535 if (chip->ecc.postpad) {
536 chip->read_buf(mtd, oob, chip->ecc.postpad);
537 oob += chip->ecc.postpad;
538 }
539 }
540
541 /* Calculate remaining oob bytes */
542 n = mtd->oobsize - (oob - chip->oob_poi);
543 if (n)
544 chip->read_buf(mtd, oob, n);
545
546 /* Then switch ECC off and read the OOB area to get the ECC code */
547 _mxc_nand_enable_hwecc(mtd, 0);
548 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
549 eccsteps = chip->ecc.steps;
550 oob = chip->oob_poi + chip->ecc.prepad;
551 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
552 host->col_addr = mtd->writesize +
553 n * eccpitch +
554 chip->ecc.prepad;
555 chip->read_buf(mtd, oob, eccbytes);
556 oob += eccbytes + chip->ecc.postpad;
557 }
558 _mxc_nand_enable_hwecc(mtd, 1);
559 return 0;
560 }
561
562 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
563 struct nand_chip *chip, int page)
564 {
565 struct mxc_nand_host *host = chip->priv;
566 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
567 int length = mtd->oobsize;
568 int i, len, status, steps = chip->ecc.steps;
569 const uint8_t *bufpoi = chip->oob_poi;
570
571 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
572 for (i = 0; i < steps; i++) {
573 len = min_t(int, length, eccpitch);
574
575 chip->write_buf(mtd, bufpoi, len);
576 bufpoi += len;
577 length -= len;
578 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
579 }
580 if (length > 0)
581 chip->write_buf(mtd, bufpoi, length);
582
583 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
584 status = chip->waitfunc(mtd, chip);
585 return status & NAND_STATUS_FAIL ? -EIO : 0;
586 }
587
588 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
589 struct nand_chip *chip,
590 const uint8_t *buf,
591 int oob_required)
592 {
593 struct mxc_nand_host *host = chip->priv;
594 int eccsize = chip->ecc.size;
595 int eccbytes = chip->ecc.bytes;
596 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
597 uint8_t *oob = chip->oob_poi;
598 int steps, size;
599 int n;
600
601 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
602 host->col_addr = n * eccsize;
603 chip->write_buf(mtd, buf, eccsize);
604 buf += eccsize;
605
606 host->col_addr = mtd->writesize + n * eccpitch;
607
608 if (chip->ecc.prepad) {
609 chip->write_buf(mtd, oob, chip->ecc.prepad);
610 oob += chip->ecc.prepad;
611 }
612
613 host->col_addr += eccbytes;
614 oob += eccbytes;
615
616 if (chip->ecc.postpad) {
617 chip->write_buf(mtd, oob, chip->ecc.postpad);
618 oob += chip->ecc.postpad;
619 }
620 }
621
622 size = mtd->oobsize - (oob - chip->oob_poi);
623 if (size)
624 chip->write_buf(mtd, oob, size);
625 return 0;
626 }
627
628 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
629 struct nand_chip *chip,
630 const uint8_t *buf,
631 int oob_required)
632 {
633 struct mxc_nand_host *host = chip->priv;
634 int i, n, eccsize = chip->ecc.size;
635 int eccbytes = chip->ecc.bytes;
636 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
637 int eccsteps = chip->ecc.steps;
638 const uint8_t *p = buf;
639 uint8_t *oob = chip->oob_poi;
640
641 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
642
643 for (i = n = 0;
644 eccsteps;
645 n++, eccsteps--, i += eccbytes, p += eccsize) {
646 host->col_addr = n * eccsize;
647
648 chip->write_buf(mtd, p, eccsize);
649
650 host->col_addr = mtd->writesize + n * eccpitch;
651
652 if (chip->ecc.prepad) {
653 chip->write_buf(mtd, oob, chip->ecc.prepad);
654 oob += chip->ecc.prepad;
655 }
656
657 chip->write_buf(mtd, oob, eccbytes);
658 oob += eccbytes;
659
660 if (chip->ecc.postpad) {
661 chip->write_buf(mtd, oob, chip->ecc.postpad);
662 oob += chip->ecc.postpad;
663 }
664 }
665
666 /* Calculate remaining oob bytes */
667 i = mtd->oobsize - (oob - chip->oob_poi);
668 if (i)
669 chip->write_buf(mtd, oob, i);
670 return 0;
671 }
672
673 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
674 u_char *read_ecc, u_char *calc_ecc)
675 {
676 struct nand_chip *nand_chip = mtd->priv;
677 struct mxc_nand_host *host = nand_chip->priv;
678 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
679 int subpages = mtd->writesize / nand_chip->subpagesize;
680 int pg2blk_shift = nand_chip->phys_erase_shift -
681 nand_chip->page_shift;
682
683 do {
684 if ((ecc_status & 0xf) > 4) {
685 static int last_bad = -1;
686
687 if (last_bad != host->page_addr >> pg2blk_shift) {
688 last_bad = host->page_addr >> pg2blk_shift;
689 printk(KERN_DEBUG
690 "MXC_NAND: HWECC uncorrectable ECC error"
691 " in block %u page %u subpage %d\n",
692 last_bad, host->page_addr,
693 mtd->writesize / nand_chip->subpagesize
694 - subpages);
695 }
696 return -1;
697 }
698 ecc_status >>= 4;
699 subpages--;
700 } while (subpages > 0);
701
702 return 0;
703 }
704 #else
705 #define mxc_nand_read_page_syndrome NULL
706 #define mxc_nand_read_page_raw_syndrome NULL
707 #define mxc_nand_read_oob_syndrome NULL
708 #define mxc_nand_write_page_syndrome NULL
709 #define mxc_nand_write_page_raw_syndrome NULL
710 #define mxc_nand_write_oob_syndrome NULL
711
712 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
713 u_char *read_ecc, u_char *calc_ecc)
714 {
715 struct nand_chip *nand_chip = mtd->priv;
716 struct mxc_nand_host *host = nand_chip->priv;
717
718 /*
719 * 1-Bit errors are automatically corrected in HW. No need for
720 * additional correction. 2-Bit errors cannot be corrected by
721 * HW ECC, so we need to return failure
722 */
723 uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
724
725 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
726 MTDDEBUG(MTD_DEBUG_LEVEL0,
727 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
728 return -1;
729 }
730
731 return 0;
732 }
733 #endif
734
735 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
736 u_char *ecc_code)
737 {
738 return 0;
739 }
740 #endif
741
742 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
743 {
744 struct nand_chip *nand_chip = mtd->priv;
745 struct mxc_nand_host *host = nand_chip->priv;
746 uint8_t ret = 0;
747 uint16_t col;
748 uint16_t __iomem *main_buf =
749 (uint16_t __iomem *)host->regs->main_area[0];
750 uint16_t __iomem *spare_buf =
751 (uint16_t __iomem *)host->regs->spare_area[0];
752 union {
753 uint16_t word;
754 uint8_t bytes[2];
755 } nfc_word;
756
757 /* Check for status request */
758 if (host->status_request)
759 return get_dev_status(host) & 0xFF;
760
761 /* Get column for 16-bit access */
762 col = host->col_addr >> 1;
763
764 /* If we are accessing the spare region */
765 if (host->spare_only)
766 nfc_word.word = readw(&spare_buf[col]);
767 else
768 nfc_word.word = readw(&main_buf[col]);
769
770 /* Pick upper/lower byte of word from RAM buffer */
771 ret = nfc_word.bytes[host->col_addr & 0x1];
772
773 /* Update saved column address */
774 if (nand_chip->options & NAND_BUSWIDTH_16)
775 host->col_addr += 2;
776 else
777 host->col_addr++;
778
779 return ret;
780 }
781
782 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
783 {
784 struct nand_chip *nand_chip = mtd->priv;
785 struct mxc_nand_host *host = nand_chip->priv;
786 uint16_t col, ret;
787 uint16_t __iomem *p;
788
789 MTDDEBUG(MTD_DEBUG_LEVEL3,
790 "mxc_nand_read_word(col = %d)\n", host->col_addr);
791
792 col = host->col_addr;
793 /* Adjust saved column address */
794 if (col < mtd->writesize && host->spare_only)
795 col += mtd->writesize;
796
797 if (col < mtd->writesize) {
798 p = (uint16_t __iomem *)(host->regs->main_area[0] +
799 (col >> 1));
800 } else {
801 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
802 ((col - mtd->writesize) >> 1));
803 }
804
805 if (col & 1) {
806 union {
807 uint16_t word;
808 uint8_t bytes[2];
809 } nfc_word[3];
810
811 nfc_word[0].word = readw(p);
812 nfc_word[1].word = readw(p + 1);
813
814 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
815 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
816
817 ret = nfc_word[2].word;
818 } else {
819 ret = readw(p);
820 }
821
822 /* Update saved column address */
823 host->col_addr = col + 2;
824
825 return ret;
826 }
827
828 /*
829 * Write data of length len to buffer buf. The data to be
830 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
831 * Operation by the NFC, the data is written to NAND Flash
832 */
833 static void mxc_nand_write_buf(struct mtd_info *mtd,
834 const u_char *buf, int len)
835 {
836 struct nand_chip *nand_chip = mtd->priv;
837 struct mxc_nand_host *host = nand_chip->priv;
838 int n, col, i = 0;
839
840 MTDDEBUG(MTD_DEBUG_LEVEL3,
841 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
842 len);
843
844 col = host->col_addr;
845
846 /* Adjust saved column address */
847 if (col < mtd->writesize && host->spare_only)
848 col += mtd->writesize;
849
850 n = mtd->writesize + mtd->oobsize - col;
851 n = min(len, n);
852
853 MTDDEBUG(MTD_DEBUG_LEVEL3,
854 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
855
856 while (n > 0) {
857 void __iomem *p;
858
859 if (col < mtd->writesize) {
860 p = host->regs->main_area[0] + (col & ~3);
861 } else {
862 p = host->regs->spare_area[0] -
863 mtd->writesize + (col & ~3);
864 }
865
866 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
867 __LINE__, p);
868
869 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
870 union {
871 uint32_t word;
872 uint8_t bytes[4];
873 } nfc_word;
874
875 nfc_word.word = readl(p);
876 nfc_word.bytes[col & 3] = buf[i++];
877 n--;
878 col++;
879
880 writel(nfc_word.word, p);
881 } else {
882 int m = mtd->writesize - col;
883
884 if (col >= mtd->writesize)
885 m += mtd->oobsize;
886
887 m = min(n, m) & ~3;
888
889 MTDDEBUG(MTD_DEBUG_LEVEL3,
890 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
891 __func__, __LINE__, n, m, i, col);
892
893 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
894 col += m;
895 i += m;
896 n -= m;
897 }
898 }
899 /* Update saved column address */
900 host->col_addr = col;
901 }
902
903 /*
904 * Read the data buffer from the NAND Flash. To read the data from NAND
905 * Flash first the data output cycle is initiated by the NFC, which copies
906 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
907 */
908 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
909 {
910 struct nand_chip *nand_chip = mtd->priv;
911 struct mxc_nand_host *host = nand_chip->priv;
912 int n, col, i = 0;
913
914 MTDDEBUG(MTD_DEBUG_LEVEL3,
915 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
916
917 col = host->col_addr;
918
919 /* Adjust saved column address */
920 if (col < mtd->writesize && host->spare_only)
921 col += mtd->writesize;
922
923 n = mtd->writesize + mtd->oobsize - col;
924 n = min(len, n);
925
926 while (n > 0) {
927 void __iomem *p;
928
929 if (col < mtd->writesize) {
930 p = host->regs->main_area[0] + (col & ~3);
931 } else {
932 p = host->regs->spare_area[0] -
933 mtd->writesize + (col & ~3);
934 }
935
936 if (((col | (int)&buf[i]) & 3) || n < 4) {
937 union {
938 uint32_t word;
939 uint8_t bytes[4];
940 } nfc_word;
941
942 nfc_word.word = readl(p);
943 buf[i++] = nfc_word.bytes[col & 3];
944 n--;
945 col++;
946 } else {
947 int m = mtd->writesize - col;
948
949 if (col >= mtd->writesize)
950 m += mtd->oobsize;
951
952 m = min(n, m) & ~3;
953 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
954
955 col += m;
956 i += m;
957 n -= m;
958 }
959 }
960 /* Update saved column address */
961 host->col_addr = col;
962 }
963
964 /*
965 * Used by the upper layer to verify the data in NAND Flash
966 * with the data in the buf.
967 */
968 static int mxc_nand_verify_buf(struct mtd_info *mtd,
969 const u_char *buf, int len)
970 {
971 u_char tmp[256];
972 uint bsize;
973
974 while (len) {
975 bsize = min(len, 256);
976 mxc_nand_read_buf(mtd, tmp, bsize);
977
978 if (memcmp(buf, tmp, bsize))
979 return 1;
980
981 buf += bsize;
982 len -= bsize;
983 }
984
985 return 0;
986 }
987
988 /*
989 * This function is used by upper layer for select and
990 * deselect of the NAND chip
991 */
992 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
993 {
994 struct nand_chip *nand_chip = mtd->priv;
995 struct mxc_nand_host *host = nand_chip->priv;
996
997 switch (chip) {
998 case -1:
999 /* TODO: Disable the NFC clock */
1000 if (host->clk_act)
1001 host->clk_act = 0;
1002 break;
1003 case 0:
1004 /* TODO: Enable the NFC clock */
1005 if (!host->clk_act)
1006 host->clk_act = 1;
1007 break;
1008
1009 default:
1010 break;
1011 }
1012 }
1013
1014 /*
1015 * Used by the upper layer to write command to NAND Flash for
1016 * different operations to be carried out on NAND Flash
1017 */
1018 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1019 int column, int page_addr)
1020 {
1021 struct nand_chip *nand_chip = mtd->priv;
1022 struct mxc_nand_host *host = nand_chip->priv;
1023
1024 MTDDEBUG(MTD_DEBUG_LEVEL3,
1025 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1026 command, column, page_addr);
1027
1028 /* Reset command state information */
1029 host->status_request = false;
1030
1031 /* Command pre-processing step */
1032 switch (command) {
1033
1034 case NAND_CMD_STATUS:
1035 host->col_addr = 0;
1036 host->status_request = true;
1037 break;
1038
1039 case NAND_CMD_READ0:
1040 host->page_addr = page_addr;
1041 host->col_addr = column;
1042 host->spare_only = false;
1043 break;
1044
1045 case NAND_CMD_READOOB:
1046 host->col_addr = column;
1047 host->spare_only = true;
1048 if (host->pagesize_2k)
1049 command = NAND_CMD_READ0; /* only READ0 is valid */
1050 break;
1051
1052 case NAND_CMD_SEQIN:
1053 if (column >= mtd->writesize) {
1054 /*
1055 * before sending SEQIN command for partial write,
1056 * we need read one page out. FSL NFC does not support
1057 * partial write. It always sends out 512+ecc+512+ecc
1058 * for large page nand flash. But for small page nand
1059 * flash, it does support SPARE ONLY operation.
1060 */
1061 if (host->pagesize_2k) {
1062 /* call ourself to read a page */
1063 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1064 page_addr);
1065 }
1066
1067 host->col_addr = column - mtd->writesize;
1068 host->spare_only = true;
1069
1070 /* Set program pointer to spare region */
1071 if (!host->pagesize_2k)
1072 send_cmd(host, NAND_CMD_READOOB);
1073 } else {
1074 host->spare_only = false;
1075 host->col_addr = column;
1076
1077 /* Set program pointer to page start */
1078 if (!host->pagesize_2k)
1079 send_cmd(host, NAND_CMD_READ0);
1080 }
1081 break;
1082
1083 case NAND_CMD_PAGEPROG:
1084 send_prog_page(host, 0, host->spare_only);
1085
1086 if (host->pagesize_2k && is_mxc_nfc_1()) {
1087 /* data in 4 areas */
1088 send_prog_page(host, 1, host->spare_only);
1089 send_prog_page(host, 2, host->spare_only);
1090 send_prog_page(host, 3, host->spare_only);
1091 }
1092
1093 break;
1094 }
1095
1096 /* Write out the command to the device. */
1097 send_cmd(host, command);
1098
1099 /* Write out column address, if necessary */
1100 if (column != -1) {
1101 /*
1102 * MXC NANDFC can only perform full page+spare or
1103 * spare-only read/write. When the upper layers perform
1104 * a read/write buffer operation, we will use the saved
1105 * column address to index into the full page.
1106 */
1107 send_addr(host, 0);
1108 if (host->pagesize_2k)
1109 /* another col addr cycle for 2k page */
1110 send_addr(host, 0);
1111 }
1112
1113 /* Write out page address, if necessary */
1114 if (page_addr != -1) {
1115 u32 page_mask = nand_chip->pagemask;
1116 do {
1117 send_addr(host, page_addr & 0xFF);
1118 page_addr >>= 8;
1119 page_mask >>= 8;
1120 } while (page_mask);
1121 }
1122
1123 /* Command post-processing step */
1124 switch (command) {
1125
1126 case NAND_CMD_RESET:
1127 break;
1128
1129 case NAND_CMD_READOOB:
1130 case NAND_CMD_READ0:
1131 if (host->pagesize_2k) {
1132 /* send read confirm command */
1133 send_cmd(host, NAND_CMD_READSTART);
1134 /* read for each AREA */
1135 send_read_page(host, 0, host->spare_only);
1136 if (is_mxc_nfc_1()) {
1137 send_read_page(host, 1, host->spare_only);
1138 send_read_page(host, 2, host->spare_only);
1139 send_read_page(host, 3, host->spare_only);
1140 }
1141 } else {
1142 send_read_page(host, 0, host->spare_only);
1143 }
1144 break;
1145
1146 case NAND_CMD_READID:
1147 host->col_addr = 0;
1148 send_read_id(host);
1149 break;
1150
1151 case NAND_CMD_PAGEPROG:
1152 break;
1153
1154 case NAND_CMD_STATUS:
1155 break;
1156
1157 case NAND_CMD_ERASE2:
1158 break;
1159 }
1160 }
1161
1162 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1163
1164 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1165 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1166
1167 static struct nand_bbt_descr bbt_main_descr = {
1168 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1169 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1170 .offs = 0,
1171 .len = 4,
1172 .veroffs = 4,
1173 .maxblocks = 4,
1174 .pattern = bbt_pattern,
1175 };
1176
1177 static struct nand_bbt_descr bbt_mirror_descr = {
1178 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1179 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1180 .offs = 0,
1181 .len = 4,
1182 .veroffs = 4,
1183 .maxblocks = 4,
1184 .pattern = mirror_pattern,
1185 };
1186
1187 #endif
1188
1189 int board_nand_init(struct nand_chip *this)
1190 {
1191 struct mtd_info *mtd;
1192 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1193 uint32_t tmp;
1194 #endif
1195
1196 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1197 this->bbt_options |= NAND_BBT_USE_FLASH;
1198 this->bbt_td = &bbt_main_descr;
1199 this->bbt_md = &bbt_mirror_descr;
1200 #endif
1201
1202 /* structures must be linked */
1203 mtd = &host->mtd;
1204 mtd->priv = this;
1205 host->nand = this;
1206
1207 /* 5 us command delay time */
1208 this->chip_delay = 5;
1209
1210 this->priv = host;
1211 this->dev_ready = mxc_nand_dev_ready;
1212 this->cmdfunc = mxc_nand_command;
1213 this->select_chip = mxc_nand_select_chip;
1214 this->read_byte = mxc_nand_read_byte;
1215 this->read_word = mxc_nand_read_word;
1216 this->write_buf = mxc_nand_write_buf;
1217 this->read_buf = mxc_nand_read_buf;
1218 this->verify_buf = mxc_nand_verify_buf;
1219
1220 host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1221 #ifdef MXC_NFC_V3_2
1222 host->ip_regs =
1223 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1224 #endif
1225 host->clk_act = 1;
1226
1227 #ifdef CONFIG_MXC_NAND_HWECC
1228 this->ecc.calculate = mxc_nand_calculate_ecc;
1229 this->ecc.hwctl = mxc_nand_enable_hwecc;
1230 this->ecc.correct = mxc_nand_correct_data;
1231 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1232 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1233 this->ecc.read_page = mxc_nand_read_page_syndrome;
1234 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1235 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1236 this->ecc.write_page = mxc_nand_write_page_syndrome;
1237 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1238 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1239 this->ecc.bytes = 9;
1240 this->ecc.prepad = 7;
1241 } else {
1242 this->ecc.mode = NAND_ECC_HW;
1243 }
1244
1245 if (this->ecc.mode == NAND_ECC_HW) {
1246 if (is_mxc_nfc_1())
1247 this->ecc.strength = 1;
1248 else
1249 this->ecc.strength = 4;
1250 }
1251
1252 host->pagesize_2k = 0;
1253
1254 this->ecc.size = 512;
1255 _mxc_nand_enable_hwecc(mtd, 1);
1256 #else
1257 this->ecc.layout = &nand_soft_eccoob;
1258 this->ecc.mode = NAND_ECC_SOFT;
1259 _mxc_nand_enable_hwecc(mtd, 0);
1260 #endif
1261 /* Reset NAND */
1262 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1263
1264 /* NAND bus width determines access functions used by upper layer */
1265 if (is_16bit_nand())
1266 this->options |= NAND_BUSWIDTH_16;
1267
1268 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1269 host->pagesize_2k = 1;
1270 this->ecc.layout = &nand_hw_eccoob2k;
1271 #else
1272 host->pagesize_2k = 0;
1273 this->ecc.layout = &nand_hw_eccoob;
1274 #endif
1275
1276 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1277 #ifdef MXC_NFC_V2_1
1278 tmp = readnfc(&host->regs->config1);
1279 tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1280 tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1281 writenfc(tmp, &host->regs->config1);
1282 if (host->pagesize_2k)
1283 writenfc(64/2, &host->regs->spare_area_size);
1284 else
1285 writenfc(16/2, &host->regs->spare_area_size);
1286 #endif
1287
1288 /*
1289 * preset operation
1290 * Unlock the internal RAM Buffer
1291 */
1292 writenfc(0x2, &host->regs->config);
1293
1294 /* Blocks to be unlocked */
1295 writenfc(0x0, &host->regs->unlockstart_blkaddr);
1296 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1297 * unlockend_blkaddr, but the magic 0x4000 does not always work
1298 * when writing more than some 32 megabytes (on 2k page nands)
1299 * However 0xFFFF doesn't seem to have this kind
1300 * of limitation (tried it back and forth several times).
1301 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1302 * only, but probably this was not tested there for v1.
1303 * The very same limitation seems to apply to this kernel driver.
1304 * This might be NAND chip specific and the i.MX31 datasheet is
1305 * extremely vague about the semantics of this register.
1306 */
1307 writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1308
1309 /* Unlock Block Command for given address range */
1310 writenfc(0x4, &host->regs->wrprot);
1311 #elif defined(MXC_NFC_V3_2)
1312 writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1313 writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1314
1315 /* Unlock the internal RAM Buffer */
1316 writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1317 &host->ip_regs->wrprot);
1318
1319 /* Blocks to be unlocked */
1320 for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1321 writenfc(0x0 | 0xFFFF << 16,
1322 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1323
1324 writenfc(0, &host->ip_regs->ipc);
1325
1326 tmp = readnfc(&host->ip_regs->config2);
1327 tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1328 NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1329 tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1330
1331 if (host->pagesize_2k) {
1332 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1333 tmp |= NFC_V3_CONFIG2_PS_2048;
1334 } else {
1335 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1336 tmp |= NFC_V3_CONFIG2_PS_512;
1337 }
1338
1339 writenfc(tmp, &host->ip_regs->config2);
1340
1341 tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1342 NFC_V3_CONFIG3_NO_SDMA |
1343 NFC_V3_CONFIG3_RBB_MODE |
1344 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1345 NFC_V3_CONFIG3_ADD_OP(0);
1346
1347 if (!(this->options & NAND_BUSWIDTH_16))
1348 tmp |= NFC_V3_CONFIG3_FW8;
1349
1350 writenfc(tmp, &host->ip_regs->config3);
1351
1352 writenfc(0, &host->ip_regs->delay_line);
1353 #endif
1354
1355 return 0;
1356 }
"Das U-Boot" Source Tree