2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
26 defined(CONFIG_MX51) || defined(CONFIG_MX53)
27 #include <asm/arch/imx-regs.h>
31 #define DRIVER_NAME "mxc_nand"
33 typedef enum {false, true} bool;
35 struct mxc_nand_host
{
37 struct nand_chip
*nand
;
39 struct fsl_nfc_regs __iomem
*regs
;
41 struct fsl_nfc_ip_regs __iomem
*ip_regs
;
48 unsigned int page_addr
;
51 static struct mxc_nand_host mxc_host
;
52 static struct mxc_nand_host
*host
= &mxc_host
;
54 /* Define delays in microsec for NAND device operations */
55 #define TROP_US_DELAY 2000
56 /* Macros to get byte and bit positions of ECC */
57 #define COLPOS(x) ((x) >> 3)
58 #define BITPOS(x) ((x) & 0xf)
60 /* Define single bit Error positions in Main & Spare area */
61 #define MAIN_SINGLEBIT_ERROR 0x4
62 #define SPARE_SINGLEBIT_ERROR 0x1
64 /* OOB placement block for use with hardware ecc generation */
65 #if defined(MXC_NFC_V1)
66 #ifndef CONFIG_SYS_NAND_LARGEPAGE
67 static struct nand_ecclayout nand_hw_eccoob
= {
69 .eccpos
= {6, 7, 8, 9, 10},
70 .oobfree
= { {0, 5}, {11, 5}, }
73 static struct nand_ecclayout nand_hw_eccoob2k
= {
81 .oobfree
= { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
84 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
85 #ifndef CONFIG_SYS_NAND_LARGEPAGE
86 static struct nand_ecclayout nand_hw_eccoob
= {
88 .eccpos
= {7, 8, 9, 10, 11, 12, 13, 14, 15},
92 static struct nand_ecclayout nand_hw_eccoob2k
= {
95 7, 8, 9, 10, 11, 12, 13, 14, 15,
96 23, 24, 25, 26, 27, 28, 29, 30, 31,
97 39, 40, 41, 42, 43, 44, 45, 46, 47,
98 55, 56, 57, 58, 59, 60, 61, 62, 63,
100 .oobfree
= { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
105 static int is_16bit_nand(void)
107 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
114 static uint32_t *mxc_nand_memcpy32(uint32_t *dest
, uint32_t *source
, size_t size
)
120 __raw_writel(__raw_readl(source
++), d
++);
125 * This function polls the NANDFC to wait for the basic operation to
126 * complete by checking the INT bit.
128 static void wait_op_done(struct mxc_nand_host
*host
, int max_retries
,
133 while (max_retries
-- > 0) {
134 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
135 tmp
= readnfc(&host
->regs
->config2
);
136 if (tmp
& NFC_V1_V2_CONFIG2_INT
) {
137 tmp
&= ~NFC_V1_V2_CONFIG2_INT
;
138 writenfc(tmp
, &host
->regs
->config2
);
139 #elif defined(MXC_NFC_V3_2)
140 tmp
= readnfc(&host
->ip_regs
->ipc
);
141 if (tmp
& NFC_V3_IPC_INT
) {
142 tmp
&= ~NFC_V3_IPC_INT
;
143 writenfc(tmp
, &host
->ip_regs
->ipc
);
149 if (max_retries
< 0) {
150 MTDDEBUG(MTD_DEBUG_LEVEL0
, "%s(%d): INT not set\n",
156 * This function issues the specified command to the NAND device and
157 * waits for completion.
159 static void send_cmd(struct mxc_nand_host
*host
, uint16_t cmd
)
161 MTDDEBUG(MTD_DEBUG_LEVEL3
, "send_cmd(host, 0x%x)\n", cmd
);
163 writenfc(cmd
, &host
->regs
->flash_cmd
);
164 writenfc(NFC_CMD
, &host
->regs
->operation
);
166 /* Wait for operation to complete */
167 wait_op_done(host
, TROP_US_DELAY
, cmd
);
171 * This function sends an address (or partial address) to the
172 * NAND device. The address is used to select the source/destination for
175 static void send_addr(struct mxc_nand_host
*host
, uint16_t addr
)
177 MTDDEBUG(MTD_DEBUG_LEVEL3
, "send_addr(host, 0x%x)\n", addr
);
179 writenfc(addr
, &host
->regs
->flash_addr
);
180 writenfc(NFC_ADDR
, &host
->regs
->operation
);
182 /* Wait for operation to complete */
183 wait_op_done(host
, TROP_US_DELAY
, addr
);
187 * This function requests the NANDFC to initiate the transfer
188 * of data currently in the NANDFC RAM buffer to the NAND device.
190 static void send_prog_page(struct mxc_nand_host
*host
, uint8_t buf_id
,
194 MTDDEBUG(MTD_DEBUG_LEVEL1
, "send_prog_page (%d)\n", spare_only
);
196 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
199 * The controller copies the 64 bytes of spare data from
200 * the first 16 bytes of each of the 4 64 byte spare buffers.
201 * Copy the contiguous data starting in spare_area[0] to
202 * the four spare area buffers.
204 for (i
= 1; i
< 4; i
++) {
205 void __iomem
*src
= &host
->regs
->spare_area
[0][i
* 16];
206 void __iomem
*dst
= &host
->regs
->spare_area
[i
][0];
208 mxc_nand_memcpy32(dst
, src
, 16);
212 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
213 writenfc(buf_id
, &host
->regs
->buf_addr
);
214 #elif defined(MXC_NFC_V3_2)
215 uint32_t tmp
= readnfc(&host
->regs
->config1
);
216 tmp
&= ~NFC_V3_CONFIG1_RBA_MASK
;
217 tmp
|= NFC_V3_CONFIG1_RBA(buf_id
);
218 writenfc(tmp
, &host
->regs
->config1
);
221 /* Configure spare or page+spare access */
222 if (!host
->pagesize_2k
) {
223 uint32_t config1
= readnfc(&host
->regs
->config1
);
225 config1
|= NFC_CONFIG1_SP_EN
;
227 config1
&= ~NFC_CONFIG1_SP_EN
;
228 writenfc(config1
, &host
->regs
->config1
);
231 writenfc(NFC_INPUT
, &host
->regs
->operation
);
233 /* Wait for operation to complete */
234 wait_op_done(host
, TROP_US_DELAY
, spare_only
);
238 * Requests NANDFC to initiate the transfer of data from the
239 * NAND device into in the NANDFC ram buffer.
241 static void send_read_page(struct mxc_nand_host
*host
, uint8_t buf_id
,
244 MTDDEBUG(MTD_DEBUG_LEVEL3
, "send_read_page (%d)\n", spare_only
);
246 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
247 writenfc(buf_id
, &host
->regs
->buf_addr
);
248 #elif defined(MXC_NFC_V3_2)
249 uint32_t tmp
= readnfc(&host
->regs
->config1
);
250 tmp
&= ~NFC_V3_CONFIG1_RBA_MASK
;
251 tmp
|= NFC_V3_CONFIG1_RBA(buf_id
);
252 writenfc(tmp
, &host
->regs
->config1
);
255 /* Configure spare or page+spare access */
256 if (!host
->pagesize_2k
) {
257 uint32_t config1
= readnfc(&host
->regs
->config1
);
259 config1
|= NFC_CONFIG1_SP_EN
;
261 config1
&= ~NFC_CONFIG1_SP_EN
;
262 writenfc(config1
, &host
->regs
->config1
);
265 writenfc(NFC_OUTPUT
, &host
->regs
->operation
);
267 /* Wait for operation to complete */
268 wait_op_done(host
, TROP_US_DELAY
, spare_only
);
270 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
274 * The controller copies the 64 bytes of spare data to
275 * the first 16 bytes of each of the 4 spare buffers.
276 * Make the data contiguous starting in spare_area[0].
278 for (i
= 1; i
< 4; i
++) {
279 void __iomem
*src
= &host
->regs
->spare_area
[i
][0];
280 void __iomem
*dst
= &host
->regs
->spare_area
[0][i
* 16];
282 mxc_nand_memcpy32(dst
, src
, 16);
287 /* Request the NANDFC to perform a read of the NAND device ID. */
288 static void send_read_id(struct mxc_nand_host
*host
)
292 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
293 /* NANDFC buffer 0 is used for device ID output */
294 writenfc(0x0, &host
->regs
->buf_addr
);
295 #elif defined(MXC_NFC_V3_2)
296 tmp
= readnfc(&host
->regs
->config1
);
297 tmp
&= ~NFC_V3_CONFIG1_RBA_MASK
;
298 writenfc(tmp
, &host
->regs
->config1
);
301 /* Read ID into main buffer */
302 tmp
= readnfc(&host
->regs
->config1
);
303 tmp
&= ~NFC_CONFIG1_SP_EN
;
304 writenfc(tmp
, &host
->regs
->config1
);
306 writenfc(NFC_ID
, &host
->regs
->operation
);
308 /* Wait for operation to complete */
309 wait_op_done(host
, TROP_US_DELAY
, 0);
313 * This function requests the NANDFC to perform a read of the
314 * NAND device status and returns the current status.
316 static uint16_t get_dev_status(struct mxc_nand_host
*host
)
318 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
319 void __iomem
*main_buf
= host
->regs
->main_area
[1];
323 /* Issue status request to NAND device */
325 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
326 /* store the main area1 first word, later do recovery */
327 store
= readl(main_buf
);
328 /* NANDFC buffer 1 is used for device status */
329 writenfc(1, &host
->regs
->buf_addr
);
332 /* Read status into main buffer */
333 tmp
= readnfc(&host
->regs
->config1
);
334 tmp
&= ~NFC_CONFIG1_SP_EN
;
335 writenfc(tmp
, &host
->regs
->config1
);
337 writenfc(NFC_STATUS
, &host
->regs
->operation
);
339 /* Wait for operation to complete */
340 wait_op_done(host
, TROP_US_DELAY
, 0);
342 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
344 * Status is placed in first word of main buffer
345 * get status, then recovery area 1 data
347 ret
= readw(main_buf
);
348 writel(store
, main_buf
);
349 #elif defined(MXC_NFC_V3_2)
350 ret
= readnfc(&host
->regs
->config1
) >> 16;
356 /* This function is used by upper layer to checks if device is ready */
357 static int mxc_nand_dev_ready(struct mtd_info
*mtd
)
360 * NFC handles R/B internally. Therefore, this function
361 * always returns status as ready.
366 static void _mxc_nand_enable_hwecc(struct mtd_info
*mtd
, int on
)
368 struct nand_chip
*nand_chip
= mtd
->priv
;
369 struct mxc_nand_host
*host
= nand_chip
->priv
;
370 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
371 uint16_t tmp
= readnfc(&host
->regs
->config1
);
374 tmp
|= NFC_V1_V2_CONFIG1_ECC_EN
;
376 tmp
&= ~NFC_V1_V2_CONFIG1_ECC_EN
;
377 writenfc(tmp
, &host
->regs
->config1
);
378 #elif defined(MXC_NFC_V3_2)
379 uint32_t tmp
= readnfc(&host
->ip_regs
->config2
);
382 tmp
|= NFC_V3_CONFIG2_ECC_EN
;
384 tmp
&= ~NFC_V3_CONFIG2_ECC_EN
;
385 writenfc(tmp
, &host
->ip_regs
->config2
);
389 #ifdef CONFIG_MXC_NAND_HWECC
390 static void mxc_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
393 * If HW ECC is enabled, we turn it on during init. There is
394 * no need to enable again here.
398 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
399 static int mxc_nand_read_oob_syndrome(struct mtd_info
*mtd
,
400 struct nand_chip
*chip
,
401 int page
, int sndcmd
)
403 struct mxc_nand_host
*host
= chip
->priv
;
404 uint8_t *buf
= chip
->oob_poi
;
405 int length
= mtd
->oobsize
;
406 int eccpitch
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
407 uint8_t *bufpoi
= buf
;
410 MTDDEBUG(MTD_DEBUG_LEVEL0
,
411 "%s: Reading OOB area of page %u to oob %p\n",
412 __FUNCTION__
, host
->page_addr
, buf
);
414 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, mtd
->writesize
, page
);
415 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
416 toread
= min_t(int, length
, chip
->ecc
.prepad
);
418 chip
->read_buf(mtd
, bufpoi
, toread
);
422 bufpoi
+= chip
->ecc
.bytes
;
423 host
->col_addr
+= chip
->ecc
.bytes
;
424 length
-= chip
->ecc
.bytes
;
426 toread
= min_t(int, length
, chip
->ecc
.postpad
);
428 chip
->read_buf(mtd
, bufpoi
, toread
);
434 chip
->read_buf(mtd
, bufpoi
, length
);
436 _mxc_nand_enable_hwecc(mtd
, 0);
437 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
438 mtd
->writesize
+ chip
->ecc
.prepad
, page
);
439 bufpoi
= buf
+ chip
->ecc
.prepad
;
440 length
= mtd
->oobsize
- chip
->ecc
.prepad
;
441 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
442 toread
= min_t(int, length
, chip
->ecc
.bytes
);
443 chip
->read_buf(mtd
, bufpoi
, toread
);
446 host
->col_addr
+= chip
->ecc
.postpad
+ chip
->ecc
.prepad
;
448 _mxc_nand_enable_hwecc(mtd
, 1);
452 static int mxc_nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
453 struct nand_chip
*chip
,
457 struct mxc_nand_host
*host
= chip
->priv
;
458 int eccsize
= chip
->ecc
.size
;
459 int eccbytes
= chip
->ecc
.bytes
;
460 int eccpitch
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
461 uint8_t *oob
= chip
->oob_poi
;
465 _mxc_nand_enable_hwecc(mtd
, 0);
466 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, host
->page_addr
);
468 for (n
= 0, steps
= chip
->ecc
.steps
; steps
> 0; n
++, steps
--) {
469 host
->col_addr
= n
* eccsize
;
470 chip
->read_buf(mtd
, buf
, eccsize
);
473 host
->col_addr
= mtd
->writesize
+ n
* eccpitch
;
474 if (chip
->ecc
.prepad
) {
475 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
476 oob
+= chip
->ecc
.prepad
;
479 chip
->read_buf(mtd
, oob
, eccbytes
);
482 if (chip
->ecc
.postpad
) {
483 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
484 oob
+= chip
->ecc
.postpad
;
488 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
490 chip
->read_buf(mtd
, oob
, size
);
491 _mxc_nand_enable_hwecc(mtd
, 1);
496 static int mxc_nand_read_page_syndrome(struct mtd_info
*mtd
,
497 struct nand_chip
*chip
,
501 struct mxc_nand_host
*host
= chip
->priv
;
502 int n
, eccsize
= chip
->ecc
.size
;
503 int eccbytes
= chip
->ecc
.bytes
;
504 int eccpitch
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
505 int eccsteps
= chip
->ecc
.steps
;
507 uint8_t *oob
= chip
->oob_poi
;
509 MTDDEBUG(MTD_DEBUG_LEVEL1
, "Reading page %u to buf %p oob %p\n",
510 host
->page_addr
, buf
, oob
);
512 /* first read the data area and the available portion of OOB */
513 for (n
= 0; eccsteps
; n
++, eccsteps
--, p
+= eccsize
) {
516 host
->col_addr
= n
* eccsize
;
518 chip
->read_buf(mtd
, p
, eccsize
);
520 host
->col_addr
= mtd
->writesize
+ n
* eccpitch
;
522 if (chip
->ecc
.prepad
) {
523 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
524 oob
+= chip
->ecc
.prepad
;
527 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
530 mtd
->ecc_stats
.failed
++;
532 mtd
->ecc_stats
.corrected
+= stat
;
535 if (chip
->ecc
.postpad
) {
536 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
537 oob
+= chip
->ecc
.postpad
;
541 /* Calculate remaining oob bytes */
542 n
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
544 chip
->read_buf(mtd
, oob
, n
);
546 /* Then switch ECC off and read the OOB area to get the ECC code */
547 _mxc_nand_enable_hwecc(mtd
, 0);
548 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, mtd
->writesize
, host
->page_addr
);
549 eccsteps
= chip
->ecc
.steps
;
550 oob
= chip
->oob_poi
+ chip
->ecc
.prepad
;
551 for (n
= 0; eccsteps
; n
++, eccsteps
--, p
+= eccsize
) {
552 host
->col_addr
= mtd
->writesize
+
555 chip
->read_buf(mtd
, oob
, eccbytes
);
556 oob
+= eccbytes
+ chip
->ecc
.postpad
;
558 _mxc_nand_enable_hwecc(mtd
, 1);
562 static int mxc_nand_write_oob_syndrome(struct mtd_info
*mtd
,
563 struct nand_chip
*chip
, int page
)
565 struct mxc_nand_host
*host
= chip
->priv
;
566 int eccpitch
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
567 int length
= mtd
->oobsize
;
568 int i
, len
, status
, steps
= chip
->ecc
.steps
;
569 const uint8_t *bufpoi
= chip
->oob_poi
;
571 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
572 for (i
= 0; i
< steps
; i
++) {
573 len
= min_t(int, length
, eccpitch
);
575 chip
->write_buf(mtd
, bufpoi
, len
);
578 host
->col_addr
+= chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
581 chip
->write_buf(mtd
, bufpoi
, length
);
583 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
584 status
= chip
->waitfunc(mtd
, chip
);
585 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
588 static void mxc_nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
589 struct nand_chip
*chip
,
592 struct mxc_nand_host
*host
= chip
->priv
;
593 int eccsize
= chip
->ecc
.size
;
594 int eccbytes
= chip
->ecc
.bytes
;
595 int eccpitch
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
596 uint8_t *oob
= chip
->oob_poi
;
600 for (n
= 0, steps
= chip
->ecc
.steps
; steps
> 0; n
++, steps
--) {
601 host
->col_addr
= n
* eccsize
;
602 chip
->write_buf(mtd
, buf
, eccsize
);
605 host
->col_addr
= mtd
->writesize
+ n
* eccpitch
;
607 if (chip
->ecc
.prepad
) {
608 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
609 oob
+= chip
->ecc
.prepad
;
612 host
->col_addr
+= eccbytes
;
615 if (chip
->ecc
.postpad
) {
616 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
617 oob
+= chip
->ecc
.postpad
;
621 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
623 chip
->write_buf(mtd
, oob
, size
);
626 static void mxc_nand_write_page_syndrome(struct mtd_info
*mtd
,
627 struct nand_chip
*chip
,
630 struct mxc_nand_host
*host
= chip
->priv
;
631 int i
, n
, eccsize
= chip
->ecc
.size
;
632 int eccbytes
= chip
->ecc
.bytes
;
633 int eccpitch
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
634 int eccsteps
= chip
->ecc
.steps
;
635 const uint8_t *p
= buf
;
636 uint8_t *oob
= chip
->oob_poi
;
638 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
642 n
++, eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
643 host
->col_addr
= n
* eccsize
;
645 chip
->write_buf(mtd
, p
, eccsize
);
647 host
->col_addr
= mtd
->writesize
+ n
* eccpitch
;
649 if (chip
->ecc
.prepad
) {
650 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
651 oob
+= chip
->ecc
.prepad
;
654 chip
->write_buf(mtd
, oob
, eccbytes
);
657 if (chip
->ecc
.postpad
) {
658 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
659 oob
+= chip
->ecc
.postpad
;
663 /* Calculate remaining oob bytes */
664 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
666 chip
->write_buf(mtd
, oob
, i
);
669 static int mxc_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
670 u_char
*read_ecc
, u_char
*calc_ecc
)
672 struct nand_chip
*nand_chip
= mtd
->priv
;
673 struct mxc_nand_host
*host
= nand_chip
->priv
;
674 uint32_t ecc_status
= readl(&host
->regs
->ecc_status_result
);
675 int subpages
= mtd
->writesize
/ nand_chip
->subpagesize
;
676 int pg2blk_shift
= nand_chip
->phys_erase_shift
-
677 nand_chip
->page_shift
;
680 if ((ecc_status
& 0xf) > 4) {
681 static int last_bad
= -1;
683 if (last_bad
!= host
->page_addr
>> pg2blk_shift
) {
684 last_bad
= host
->page_addr
>> pg2blk_shift
;
686 "MXC_NAND: HWECC uncorrectable ECC error"
687 " in block %u page %u subpage %d\n",
688 last_bad
, host
->page_addr
,
689 mtd
->writesize
/ nand_chip
->subpagesize
696 } while (subpages
> 0);
701 #define mxc_nand_read_page_syndrome NULL
702 #define mxc_nand_read_page_raw_syndrome NULL
703 #define mxc_nand_read_oob_syndrome NULL
704 #define mxc_nand_write_page_syndrome NULL
705 #define mxc_nand_write_page_raw_syndrome NULL
706 #define mxc_nand_write_oob_syndrome NULL
708 static int mxc_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
709 u_char
*read_ecc
, u_char
*calc_ecc
)
711 struct nand_chip
*nand_chip
= mtd
->priv
;
712 struct mxc_nand_host
*host
= nand_chip
->priv
;
715 * 1-Bit errors are automatically corrected in HW. No need for
716 * additional correction. 2-Bit errors cannot be corrected by
717 * HW ECC, so we need to return failure
719 uint16_t ecc_status
= readnfc(&host
->regs
->ecc_status_result
);
721 if (((ecc_status
& 0x3) == 2) || ((ecc_status
>> 2) == 2)) {
722 MTDDEBUG(MTD_DEBUG_LEVEL0
,
723 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
731 static int mxc_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
738 static u_char
mxc_nand_read_byte(struct mtd_info
*mtd
)
740 struct nand_chip
*nand_chip
= mtd
->priv
;
741 struct mxc_nand_host
*host
= nand_chip
->priv
;
744 uint16_t __iomem
*main_buf
=
745 (uint16_t __iomem
*)host
->regs
->main_area
[0];
746 uint16_t __iomem
*spare_buf
=
747 (uint16_t __iomem
*)host
->regs
->spare_area
[0];
753 /* Check for status request */
754 if (host
->status_request
)
755 return get_dev_status(host
) & 0xFF;
757 /* Get column for 16-bit access */
758 col
= host
->col_addr
>> 1;
760 /* If we are accessing the spare region */
761 if (host
->spare_only
)
762 nfc_word
.word
= readw(&spare_buf
[col
]);
764 nfc_word
.word
= readw(&main_buf
[col
]);
766 /* Pick upper/lower byte of word from RAM buffer */
767 ret
= nfc_word
.bytes
[host
->col_addr
& 0x1];
769 /* Update saved column address */
770 if (nand_chip
->options
& NAND_BUSWIDTH_16
)
778 static uint16_t mxc_nand_read_word(struct mtd_info
*mtd
)
780 struct nand_chip
*nand_chip
= mtd
->priv
;
781 struct mxc_nand_host
*host
= nand_chip
->priv
;
785 MTDDEBUG(MTD_DEBUG_LEVEL3
,
786 "mxc_nand_read_word(col = %d)\n", host
->col_addr
);
788 col
= host
->col_addr
;
789 /* Adjust saved column address */
790 if (col
< mtd
->writesize
&& host
->spare_only
)
791 col
+= mtd
->writesize
;
793 if (col
< mtd
->writesize
) {
794 p
= (uint16_t __iomem
*)(host
->regs
->main_area
[0] +
797 p
= (uint16_t __iomem
*)(host
->regs
->spare_area
[0] +
798 ((col
- mtd
->writesize
) >> 1));
807 nfc_word
[0].word
= readw(p
);
808 nfc_word
[1].word
= readw(p
+ 1);
810 nfc_word
[2].bytes
[0] = nfc_word
[0].bytes
[1];
811 nfc_word
[2].bytes
[1] = nfc_word
[1].bytes
[0];
813 ret
= nfc_word
[2].word
;
818 /* Update saved column address */
819 host
->col_addr
= col
+ 2;
825 * Write data of length len to buffer buf. The data to be
826 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
827 * Operation by the NFC, the data is written to NAND Flash
829 static void mxc_nand_write_buf(struct mtd_info
*mtd
,
830 const u_char
*buf
, int len
)
832 struct nand_chip
*nand_chip
= mtd
->priv
;
833 struct mxc_nand_host
*host
= nand_chip
->priv
;
836 MTDDEBUG(MTD_DEBUG_LEVEL3
,
837 "mxc_nand_write_buf(col = %d, len = %d)\n", host
->col_addr
,
840 col
= host
->col_addr
;
842 /* Adjust saved column address */
843 if (col
< mtd
->writesize
&& host
->spare_only
)
844 col
+= mtd
->writesize
;
846 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
849 MTDDEBUG(MTD_DEBUG_LEVEL3
,
850 "%s:%d: col = %d, n = %d\n", __func__
, __LINE__
, col
, n
);
855 if (col
< mtd
->writesize
) {
856 p
= host
->regs
->main_area
[0] + (col
& ~3);
858 p
= host
->regs
->spare_area
[0] -
859 mtd
->writesize
+ (col
& ~3);
862 MTDDEBUG(MTD_DEBUG_LEVEL3
, "%s:%d: p = %p\n", __func__
,
865 if (((col
| (unsigned long)&buf
[i
]) & 3) || n
< 4) {
871 nfc_word
.word
= readl(p
);
872 nfc_word
.bytes
[col
& 3] = buf
[i
++];
876 writel(nfc_word
.word
, p
);
878 int m
= mtd
->writesize
- col
;
880 if (col
>= mtd
->writesize
)
885 MTDDEBUG(MTD_DEBUG_LEVEL3
,
886 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
887 __func__
, __LINE__
, n
, m
, i
, col
);
889 mxc_nand_memcpy32(p
, (uint32_t *)&buf
[i
], m
);
895 /* Update saved column address */
896 host
->col_addr
= col
;
900 * Read the data buffer from the NAND Flash. To read the data from NAND
901 * Flash first the data output cycle is initiated by the NFC, which copies
902 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
904 static void mxc_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
906 struct nand_chip
*nand_chip
= mtd
->priv
;
907 struct mxc_nand_host
*host
= nand_chip
->priv
;
910 MTDDEBUG(MTD_DEBUG_LEVEL3
,
911 "mxc_nand_read_buf(col = %d, len = %d)\n", host
->col_addr
, len
);
913 col
= host
->col_addr
;
915 /* Adjust saved column address */
916 if (col
< mtd
->writesize
&& host
->spare_only
)
917 col
+= mtd
->writesize
;
919 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
925 if (col
< mtd
->writesize
) {
926 p
= host
->regs
->main_area
[0] + (col
& ~3);
928 p
= host
->regs
->spare_area
[0] -
929 mtd
->writesize
+ (col
& ~3);
932 if (((col
| (int)&buf
[i
]) & 3) || n
< 4) {
938 nfc_word
.word
= readl(p
);
939 buf
[i
++] = nfc_word
.bytes
[col
& 3];
943 int m
= mtd
->writesize
- col
;
945 if (col
>= mtd
->writesize
)
949 mxc_nand_memcpy32((uint32_t *)&buf
[i
], p
, m
);
956 /* Update saved column address */
957 host
->col_addr
= col
;
961 * Used by the upper layer to verify the data in NAND Flash
962 * with the data in the buf.
964 static int mxc_nand_verify_buf(struct mtd_info
*mtd
,
965 const u_char
*buf
, int len
)
971 bsize
= min(len
, 256);
972 mxc_nand_read_buf(mtd
, tmp
, bsize
);
974 if (memcmp(buf
, tmp
, bsize
))
985 * This function is used by upper layer for select and
986 * deselect of the NAND chip
988 static void mxc_nand_select_chip(struct mtd_info
*mtd
, int chip
)
990 struct nand_chip
*nand_chip
= mtd
->priv
;
991 struct mxc_nand_host
*host
= nand_chip
->priv
;
995 /* TODO: Disable the NFC clock */
1000 /* TODO: Enable the NFC clock */
1011 * Used by the upper layer to write command to NAND Flash for
1012 * different operations to be carried out on NAND Flash
1014 void mxc_nand_command(struct mtd_info
*mtd
, unsigned command
,
1015 int column
, int page_addr
)
1017 struct nand_chip
*nand_chip
= mtd
->priv
;
1018 struct mxc_nand_host
*host
= nand_chip
->priv
;
1020 MTDDEBUG(MTD_DEBUG_LEVEL3
,
1021 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1022 command
, column
, page_addr
);
1024 /* Reset command state information */
1025 host
->status_request
= false;
1027 /* Command pre-processing step */
1030 case NAND_CMD_STATUS
:
1032 host
->status_request
= true;
1035 case NAND_CMD_READ0
:
1036 host
->page_addr
= page_addr
;
1037 host
->col_addr
= column
;
1038 host
->spare_only
= false;
1041 case NAND_CMD_READOOB
:
1042 host
->col_addr
= column
;
1043 host
->spare_only
= true;
1044 if (host
->pagesize_2k
)
1045 command
= NAND_CMD_READ0
; /* only READ0 is valid */
1048 case NAND_CMD_SEQIN
:
1049 if (column
>= mtd
->writesize
) {
1051 * before sending SEQIN command for partial write,
1052 * we need read one page out. FSL NFC does not support
1053 * partial write. It always sends out 512+ecc+512+ecc
1054 * for large page nand flash. But for small page nand
1055 * flash, it does support SPARE ONLY operation.
1057 if (host
->pagesize_2k
) {
1058 /* call ourself to read a page */
1059 mxc_nand_command(mtd
, NAND_CMD_READ0
, 0,
1063 host
->col_addr
= column
- mtd
->writesize
;
1064 host
->spare_only
= true;
1066 /* Set program pointer to spare region */
1067 if (!host
->pagesize_2k
)
1068 send_cmd(host
, NAND_CMD_READOOB
);
1070 host
->spare_only
= false;
1071 host
->col_addr
= column
;
1073 /* Set program pointer to page start */
1074 if (!host
->pagesize_2k
)
1075 send_cmd(host
, NAND_CMD_READ0
);
1079 case NAND_CMD_PAGEPROG
:
1080 send_prog_page(host
, 0, host
->spare_only
);
1082 if (host
->pagesize_2k
&& is_mxc_nfc_1()) {
1083 /* data in 4 areas */
1084 send_prog_page(host
, 1, host
->spare_only
);
1085 send_prog_page(host
, 2, host
->spare_only
);
1086 send_prog_page(host
, 3, host
->spare_only
);
1092 /* Write out the command to the device. */
1093 send_cmd(host
, command
);
1095 /* Write out column address, if necessary */
1098 * MXC NANDFC can only perform full page+spare or
1099 * spare-only read/write. When the upper layers perform
1100 * a read/write buffer operation, we will use the saved
1101 * column address to index into the full page.
1104 if (host
->pagesize_2k
)
1105 /* another col addr cycle for 2k page */
1109 /* Write out page address, if necessary */
1110 if (page_addr
!= -1) {
1111 u32 page_mask
= nand_chip
->pagemask
;
1113 send_addr(host
, page_addr
& 0xFF);
1116 } while (page_mask
);
1119 /* Command post-processing step */
1122 case NAND_CMD_RESET
:
1125 case NAND_CMD_READOOB
:
1126 case NAND_CMD_READ0
:
1127 if (host
->pagesize_2k
) {
1128 /* send read confirm command */
1129 send_cmd(host
, NAND_CMD_READSTART
);
1130 /* read for each AREA */
1131 send_read_page(host
, 0, host
->spare_only
);
1132 if (is_mxc_nfc_1()) {
1133 send_read_page(host
, 1, host
->spare_only
);
1134 send_read_page(host
, 2, host
->spare_only
);
1135 send_read_page(host
, 3, host
->spare_only
);
1138 send_read_page(host
, 0, host
->spare_only
);
1142 case NAND_CMD_READID
:
1147 case NAND_CMD_PAGEPROG
:
1150 case NAND_CMD_STATUS
:
1153 case NAND_CMD_ERASE2
:
1158 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1160 static u8 bbt_pattern
[] = {'B', 'b', 't', '0' };
1161 static u8 mirror_pattern
[] = {'1', 't', 'b', 'B' };
1163 static struct nand_bbt_descr bbt_main_descr
= {
1164 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
1165 NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1170 .pattern
= bbt_pattern
,
1173 static struct nand_bbt_descr bbt_mirror_descr
= {
1174 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
1175 NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1180 .pattern
= mirror_pattern
,
1185 int board_nand_init(struct nand_chip
*this)
1187 struct mtd_info
*mtd
;
1188 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1192 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1193 this->options
|= NAND_USE_FLASH_BBT
;
1194 this->bbt_td
= &bbt_main_descr
;
1195 this->bbt_md
= &bbt_mirror_descr
;
1198 /* structures must be linked */
1203 /* 5 us command delay time */
1204 this->chip_delay
= 5;
1207 this->dev_ready
= mxc_nand_dev_ready
;
1208 this->cmdfunc
= mxc_nand_command
;
1209 this->select_chip
= mxc_nand_select_chip
;
1210 this->read_byte
= mxc_nand_read_byte
;
1211 this->read_word
= mxc_nand_read_word
;
1212 this->write_buf
= mxc_nand_write_buf
;
1213 this->read_buf
= mxc_nand_read_buf
;
1214 this->verify_buf
= mxc_nand_verify_buf
;
1216 host
->regs
= (struct fsl_nfc_regs __iomem
*)CONFIG_MXC_NAND_REGS_BASE
;
1219 (struct fsl_nfc_ip_regs __iomem
*)CONFIG_MXC_NAND_IP_REGS_BASE
;
1223 #ifdef CONFIG_MXC_NAND_HWECC
1224 this->ecc
.calculate
= mxc_nand_calculate_ecc
;
1225 this->ecc
.hwctl
= mxc_nand_enable_hwecc
;
1226 this->ecc
.correct
= mxc_nand_correct_data
;
1227 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1228 this->ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1229 this->ecc
.read_page
= mxc_nand_read_page_syndrome
;
1230 this->ecc
.read_page_raw
= mxc_nand_read_page_raw_syndrome
;
1231 this->ecc
.read_oob
= mxc_nand_read_oob_syndrome
;
1232 this->ecc
.write_page
= mxc_nand_write_page_syndrome
;
1233 this->ecc
.write_page_raw
= mxc_nand_write_page_raw_syndrome
;
1234 this->ecc
.write_oob
= mxc_nand_write_oob_syndrome
;
1235 this->ecc
.bytes
= 9;
1236 this->ecc
.prepad
= 7;
1238 this->ecc
.mode
= NAND_ECC_HW
;
1241 host
->pagesize_2k
= 0;
1243 this->ecc
.size
= 512;
1244 _mxc_nand_enable_hwecc(mtd
, 1);
1246 this->ecc
.layout
= &nand_soft_eccoob
;
1247 this->ecc
.mode
= NAND_ECC_SOFT
;
1248 _mxc_nand_enable_hwecc(mtd
, 0);
1251 this->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1253 /* NAND bus width determines access functions used by upper layer */
1254 if (is_16bit_nand())
1255 this->options
|= NAND_BUSWIDTH_16
;
1257 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1258 host
->pagesize_2k
= 1;
1259 this->ecc
.layout
= &nand_hw_eccoob2k
;
1261 host
->pagesize_2k
= 0;
1262 this->ecc
.layout
= &nand_hw_eccoob
;
1265 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1267 tmp
= readnfc(&host
->regs
->config1
);
1268 tmp
|= NFC_V2_CONFIG1_ONE_CYCLE
;
1269 tmp
|= NFC_V2_CONFIG1_ECC_MODE_4
;
1270 writenfc(tmp
, &host
->regs
->config1
);
1271 if (host
->pagesize_2k
)
1272 writenfc(64/2, &host
->regs
->spare_area_size
);
1274 writenfc(16/2, &host
->regs
->spare_area_size
);
1279 * Unlock the internal RAM Buffer
1281 writenfc(0x2, &host
->regs
->config
);
1283 /* Blocks to be unlocked */
1284 writenfc(0x0, &host
->regs
->unlockstart_blkaddr
);
1285 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1286 * unlockend_blkaddr, but the magic 0x4000 does not always work
1287 * when writing more than some 32 megabytes (on 2k page nands)
1288 * However 0xFFFF doesn't seem to have this kind
1289 * of limitation (tried it back and forth several times).
1290 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1291 * only, but probably this was not tested there for v1.
1292 * The very same limitation seems to apply to this kernel driver.
1293 * This might be NAND chip specific and the i.MX31 datasheet is
1294 * extremely vague about the semantics of this register.
1296 writenfc(0xFFFF, &host
->regs
->unlockend_blkaddr
);
1298 /* Unlock Block Command for given address range */
1299 writenfc(0x4, &host
->regs
->wrprot
);
1300 #elif defined(MXC_NFC_V3_2)
1301 writenfc(NFC_V3_CONFIG1_RBA(0), &host
->regs
->config1
);
1302 writenfc(NFC_V3_IPC_CREQ
, &host
->ip_regs
->ipc
);
1304 /* Unlock the internal RAM Buffer */
1305 writenfc(NFC_V3_WRPROT_BLS_UNLOCK
| NFC_V3_WRPROT_UNLOCK
,
1306 &host
->ip_regs
->wrprot
);
1308 /* Blocks to be unlocked */
1309 for (tmp
= 0; tmp
< CONFIG_SYS_NAND_MAX_CHIPS
; tmp
++)
1310 writenfc(0x0 | 0xFFFF << 16,
1311 &host
->ip_regs
->wrprot_unlock_blkaddr
[tmp
]);
1313 writenfc(0, &host
->ip_regs
->ipc
);
1315 tmp
= readnfc(&host
->ip_regs
->config2
);
1316 tmp
&= ~(NFC_V3_CONFIG2_SPAS_MASK
| NFC_V3_CONFIG2_EDC_MASK
|
1317 NFC_V3_CONFIG2_ECC_MODE_8
| NFC_V3_CONFIG2_PS_MASK
);
1318 tmp
|= NFC_V3_CONFIG2_ONE_CYCLE
;
1320 if (host
->pagesize_2k
) {
1321 tmp
|= NFC_V3_CONFIG2_SPAS(64/2);
1322 tmp
|= NFC_V3_CONFIG2_PS_2048
;
1324 tmp
|= NFC_V3_CONFIG2_SPAS(16/2);
1325 tmp
|= NFC_V3_CONFIG2_PS_512
;
1328 writenfc(tmp
, &host
->ip_regs
->config2
);
1330 tmp
= NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1331 NFC_V3_CONFIG3_NO_SDMA
|
1332 NFC_V3_CONFIG3_RBB_MODE
|
1333 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1334 NFC_V3_CONFIG3_ADD_OP(0);
1336 if (!(this->options
& NAND_BUSWIDTH_16
))
1337 tmp
|= NFC_V3_CONFIG3_FW8
;
1339 writenfc(tmp
, &host
->ip_regs
->config3
);
1341 writenfc(0, &host
->ip_regs
->delay_line
);