1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Freescale GPMI NFC NAND Flash Driver
11 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/types.h>
20 #include <linux/errno.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/imx-regs.h>
24 #include <asm/mach-imx/regs-bch.h>
25 #include <asm/mach-imx/regs-gpmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/mach-imx/dma.h>
29 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
31 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
32 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
37 #define MXS_NAND_METADATA_SIZE 10
38 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
40 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
46 #define MXS_NAND_BCH_TIMEOUT 10000
48 struct mxs_nand_info
{
51 uint32_t cmd_queue_len
;
52 uint32_t data_buf_size
;
58 uint8_t marking_block_bad
;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob
)(struct mtd_info
*mtd
,
63 loff_t from
, struct mtd_oob_ops
*ops
);
64 int (*hooked_write_oob
)(struct mtd_info
*mtd
,
65 loff_t to
, struct mtd_oob_ops
*ops
);
66 int (*hooked_block_markbad
)(struct mtd_info
*mtd
,
70 struct mxs_dma_desc
**desc
;
74 struct nand_ecclayout fake_ecc_layout
;
75 static int chunk_data_size
= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
76 static int galois_field
= 13;
79 * Cache management functions
81 #ifndef CONFIG_SYS_DCACHE_OFF
82 static void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
)
84 uint32_t addr
= (uint32_t)info
->data_buf
;
86 flush_dcache_range(addr
, addr
+ info
->data_buf_size
);
89 static void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
)
91 uint32_t addr
= (uint32_t)info
->data_buf
;
93 invalidate_dcache_range(addr
, addr
+ info
->data_buf_size
);
96 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
)
98 uint32_t addr
= (uint32_t)info
->cmd_buf
;
100 flush_dcache_range(addr
, addr
+ MXS_NAND_COMMAND_BUFFER_SIZE
);
103 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
) {}
104 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
) {}
105 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
) {}
108 static struct mxs_dma_desc
*mxs_nand_get_dma_desc(struct mxs_nand_info
*info
)
110 struct mxs_dma_desc
*desc
;
112 if (info
->desc_index
>= MXS_NAND_DMA_DESCRIPTOR_COUNT
) {
113 printf("MXS NAND: Too many DMA descriptors requested\n");
117 desc
= info
->desc
[info
->desc_index
];
123 static void mxs_nand_return_dma_descs(struct mxs_nand_info
*info
)
126 struct mxs_dma_desc
*desc
;
128 for (i
= 0; i
< info
->desc_index
; i
++) {
129 desc
= info
->desc
[i
];
130 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
131 desc
->address
= (dma_addr_t
)desc
;
134 info
->desc_index
= 0;
137 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size
)
139 return page_data_size
/ chunk_data_size
;
142 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength
)
144 return ecc_strength
* galois_field
;
147 static uint32_t mxs_nand_aux_status_offset(void)
149 return (MXS_NAND_METADATA_SIZE
+ 0x3) & ~0x3;
152 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size
,
153 uint32_t page_oob_size
)
156 int max_ecc_strength_supported
;
158 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
159 if (is_mx6sx() || is_mx7())
160 max_ecc_strength_supported
= 62;
162 max_ecc_strength_supported
= 40;
165 * Determine the ECC layout with the formula:
166 * ECC bits per chunk = (total page spare data bits) /
167 * (bits per ECC level) / (chunks per page)
169 * total page spare data bits =
170 * (page oob size - meta data size) * (bits per byte)
172 ecc_strength
= ((page_oob_size
- MXS_NAND_METADATA_SIZE
) * 8)
174 mxs_nand_ecc_chunk_cnt(page_data_size
));
176 return min(round_down(ecc_strength
, 2), max_ecc_strength_supported
);
179 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size
,
180 uint32_t ecc_strength
)
182 uint32_t chunk_data_size_in_bits
;
183 uint32_t chunk_ecc_size_in_bits
;
184 uint32_t chunk_total_size_in_bits
;
185 uint32_t block_mark_chunk_number
;
186 uint32_t block_mark_chunk_bit_offset
;
187 uint32_t block_mark_bit_offset
;
189 chunk_data_size_in_bits
= chunk_data_size
* 8;
190 chunk_ecc_size_in_bits
= mxs_nand_ecc_size_in_bits(ecc_strength
);
192 chunk_total_size_in_bits
=
193 chunk_data_size_in_bits
+ chunk_ecc_size_in_bits
;
195 /* Compute the bit offset of the block mark within the physical page. */
196 block_mark_bit_offset
= page_data_size
* 8;
198 /* Subtract the metadata bits. */
199 block_mark_bit_offset
-= MXS_NAND_METADATA_SIZE
* 8;
202 * Compute the chunk number (starting at zero) in which the block mark
205 block_mark_chunk_number
=
206 block_mark_bit_offset
/ chunk_total_size_in_bits
;
209 * Compute the bit offset of the block mark within its chunk, and
212 block_mark_chunk_bit_offset
= block_mark_bit_offset
-
213 (block_mark_chunk_number
* chunk_total_size_in_bits
);
215 if (block_mark_chunk_bit_offset
> chunk_data_size_in_bits
)
219 * Now that we know the chunk number in which the block mark appears,
220 * we can subtract all the ECC bits that appear before it.
222 block_mark_bit_offset
-=
223 block_mark_chunk_number
* chunk_ecc_size_in_bits
;
225 return block_mark_bit_offset
;
228 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info
*mtd
)
230 uint32_t ecc_strength
;
231 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
232 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) >> 3;
235 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info
*mtd
)
237 uint32_t ecc_strength
;
238 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
239 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) & 0x7;
243 * Wait for BCH complete IRQ and clear the IRQ
245 static int mxs_nand_wait_for_bch_complete(void)
247 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
248 int timeout
= MXS_NAND_BCH_TIMEOUT
;
251 ret
= mxs_wait_mask_set(&bch_regs
->hw_bch_ctrl_reg
,
252 BCH_CTRL_COMPLETE_IRQ
, timeout
);
254 writel(BCH_CTRL_COMPLETE_IRQ
, &bch_regs
->hw_bch_ctrl_clr
);
260 * This is the function that we install in the cmd_ctrl function pointer of the
261 * owning struct nand_chip. The only functions in the reference implementation
262 * that use these functions pointers are cmdfunc and select_chip.
264 * In this driver, we implement our own select_chip, so this function will only
265 * be called by the reference implementation's cmdfunc. For this reason, we can
266 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
269 static void mxs_nand_cmd_ctrl(struct mtd_info
*mtd
, int data
, unsigned int ctrl
)
271 struct nand_chip
*nand
= mtd_to_nand(mtd
);
272 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
273 struct mxs_dma_desc
*d
;
274 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
278 * If this condition is true, something is _VERY_ wrong in MTD
281 if (nand_info
->cmd_queue_len
== MXS_NAND_COMMAND_BUFFER_SIZE
) {
282 printf("MXS NAND: Command queue too long\n");
287 * Every operation begins with a command byte and a series of zero or
288 * more address bytes. These are distinguished by either the Address
289 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
290 * asserted. When MTD is ready to execute the command, it will
291 * deasert both latch enables.
293 * Rather than run a separate DMA operation for every single byte, we
294 * queue them up and run a single DMA operation for the entire series
295 * of command and data bytes.
297 if (ctrl
& (NAND_ALE
| NAND_CLE
)) {
298 if (data
!= NAND_CMD_NONE
)
299 nand_info
->cmd_buf
[nand_info
->cmd_queue_len
++] = data
;
304 * If control arrives here, MTD has deasserted both the ALE and CLE,
305 * which means it's ready to run an operation. Check if we have any
308 if (nand_info
->cmd_queue_len
== 0)
311 /* Compile the DMA descriptor -- a descriptor that sends command. */
312 d
= mxs_nand_get_dma_desc(nand_info
);
314 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
315 MXS_DMA_DESC_CHAIN
| MXS_DMA_DESC_DEC_SEM
|
316 MXS_DMA_DESC_WAIT4END
| (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
317 (nand_info
->cmd_queue_len
<< MXS_DMA_DESC_BYTES_OFFSET
);
319 d
->cmd
.address
= (dma_addr_t
)nand_info
->cmd_buf
;
321 d
->cmd
.pio_words
[0] =
322 GPMI_CTRL0_COMMAND_MODE_WRITE
|
323 GPMI_CTRL0_WORD_LENGTH
|
324 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
325 GPMI_CTRL0_ADDRESS_NAND_CLE
|
326 GPMI_CTRL0_ADDRESS_INCREMENT
|
327 nand_info
->cmd_queue_len
;
329 mxs_dma_desc_append(channel
, d
);
332 mxs_nand_flush_cmd_buf(nand_info
);
334 /* Execute the DMA chain. */
335 ret
= mxs_dma_go(channel
);
337 printf("MXS NAND: Error sending command\n");
339 mxs_nand_return_dma_descs(nand_info
);
341 /* Reset the command queue. */
342 nand_info
->cmd_queue_len
= 0;
346 * Test if the NAND flash is ready.
348 static int mxs_nand_device_ready(struct mtd_info
*mtd
)
350 struct nand_chip
*chip
= mtd_to_nand(mtd
);
351 struct mxs_nand_info
*nand_info
= nand_get_controller_data(chip
);
352 struct mxs_gpmi_regs
*gpmi_regs
=
353 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
356 tmp
= readl(&gpmi_regs
->hw_gpmi_stat
);
357 tmp
>>= (GPMI_STAT_READY_BUSY_OFFSET
+ nand_info
->cur_chip
);
363 * Select the NAND chip.
365 static void mxs_nand_select_chip(struct mtd_info
*mtd
, int chip
)
367 struct nand_chip
*nand
= mtd_to_nand(mtd
);
368 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
370 nand_info
->cur_chip
= chip
;
374 * Handle block mark swapping.
376 * Note that, when this function is called, it doesn't know whether it's
377 * swapping the block mark, or swapping it *back* -- but it doesn't matter
378 * because the the operation is the same.
380 static void mxs_nand_swap_block_mark(struct mtd_info
*mtd
,
381 uint8_t *data_buf
, uint8_t *oob_buf
)
389 bit_offset
= mxs_nand_mark_bit_offset(mtd
);
390 buf_offset
= mxs_nand_mark_byte_offset(mtd
);
393 * Get the byte from the data area that overlays the block mark. Since
394 * the ECC engine applies its own view to the bits in the page, the
395 * physical block mark won't (in general) appear on a byte boundary in
398 src
= data_buf
[buf_offset
] >> bit_offset
;
399 src
|= data_buf
[buf_offset
+ 1] << (8 - bit_offset
);
405 data_buf
[buf_offset
] &= ~(0xff << bit_offset
);
406 data_buf
[buf_offset
+ 1] &= 0xff << bit_offset
;
408 data_buf
[buf_offset
] |= dst
<< bit_offset
;
409 data_buf
[buf_offset
+ 1] |= dst
>> (8 - bit_offset
);
413 * Read data from NAND.
415 static void mxs_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int length
)
417 struct nand_chip
*nand
= mtd_to_nand(mtd
);
418 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
419 struct mxs_dma_desc
*d
;
420 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
423 if (length
> NAND_MAX_PAGESIZE
) {
424 printf("MXS NAND: DMA buffer too big\n");
429 printf("MXS NAND: DMA buffer is NULL\n");
433 /* Compile the DMA descriptor - a descriptor that reads data. */
434 d
= mxs_nand_get_dma_desc(nand_info
);
436 MXS_DMA_DESC_COMMAND_DMA_WRITE
| MXS_DMA_DESC_IRQ
|
437 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
438 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
439 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
441 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
443 d
->cmd
.pio_words
[0] =
444 GPMI_CTRL0_COMMAND_MODE_READ
|
445 GPMI_CTRL0_WORD_LENGTH
|
446 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
447 GPMI_CTRL0_ADDRESS_NAND_DATA
|
450 mxs_dma_desc_append(channel
, d
);
453 * A DMA descriptor that waits for the command to end and the chip to
456 * I think we actually should *not* be waiting for the chip to become
457 * ready because, after all, we don't care. I think the original code
458 * did that and no one has re-thought it yet.
460 d
= mxs_nand_get_dma_desc(nand_info
);
462 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
463 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_DEC_SEM
|
464 MXS_DMA_DESC_WAIT4END
| (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
468 d
->cmd
.pio_words
[0] =
469 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
470 GPMI_CTRL0_WORD_LENGTH
|
471 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
472 GPMI_CTRL0_ADDRESS_NAND_DATA
;
474 mxs_dma_desc_append(channel
, d
);
476 /* Invalidate caches */
477 mxs_nand_inval_data_buf(nand_info
);
479 /* Execute the DMA chain. */
480 ret
= mxs_dma_go(channel
);
482 printf("MXS NAND: DMA read error\n");
486 /* Invalidate caches */
487 mxs_nand_inval_data_buf(nand_info
);
489 memcpy(buf
, nand_info
->data_buf
, length
);
492 mxs_nand_return_dma_descs(nand_info
);
496 * Write data to NAND.
498 static void mxs_nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
501 struct nand_chip
*nand
= mtd_to_nand(mtd
);
502 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
503 struct mxs_dma_desc
*d
;
504 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
507 if (length
> NAND_MAX_PAGESIZE
) {
508 printf("MXS NAND: DMA buffer too big\n");
513 printf("MXS NAND: DMA buffer is NULL\n");
517 memcpy(nand_info
->data_buf
, buf
, length
);
519 /* Compile the DMA descriptor - a descriptor that writes data. */
520 d
= mxs_nand_get_dma_desc(nand_info
);
522 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
523 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
524 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
525 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
527 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
529 d
->cmd
.pio_words
[0] =
530 GPMI_CTRL0_COMMAND_MODE_WRITE
|
531 GPMI_CTRL0_WORD_LENGTH
|
532 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
533 GPMI_CTRL0_ADDRESS_NAND_DATA
|
536 mxs_dma_desc_append(channel
, d
);
539 mxs_nand_flush_data_buf(nand_info
);
541 /* Execute the DMA chain. */
542 ret
= mxs_dma_go(channel
);
544 printf("MXS NAND: DMA write error\n");
546 mxs_nand_return_dma_descs(nand_info
);
550 * Read a single byte from NAND.
552 static uint8_t mxs_nand_read_byte(struct mtd_info
*mtd
)
555 mxs_nand_read_buf(mtd
, &buf
, 1);
560 * Read a page from NAND.
562 static int mxs_nand_ecc_read_page(struct mtd_info
*mtd
, struct nand_chip
*nand
,
563 uint8_t *buf
, int oob_required
,
566 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
567 struct mxs_dma_desc
*d
;
568 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
569 uint32_t corrected
= 0, failed
= 0;
573 /* Compile the DMA descriptor - wait for ready. */
574 d
= mxs_nand_get_dma_desc(nand_info
);
576 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
577 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
578 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
582 d
->cmd
.pio_words
[0] =
583 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
584 GPMI_CTRL0_WORD_LENGTH
|
585 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
586 GPMI_CTRL0_ADDRESS_NAND_DATA
;
588 mxs_dma_desc_append(channel
, d
);
590 /* Compile the DMA descriptor - enable the BCH block and read. */
591 d
= mxs_nand_get_dma_desc(nand_info
);
593 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
594 MXS_DMA_DESC_WAIT4END
| (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
598 d
->cmd
.pio_words
[0] =
599 GPMI_CTRL0_COMMAND_MODE_READ
|
600 GPMI_CTRL0_WORD_LENGTH
|
601 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
602 GPMI_CTRL0_ADDRESS_NAND_DATA
|
603 (mtd
->writesize
+ mtd
->oobsize
);
604 d
->cmd
.pio_words
[1] = 0;
605 d
->cmd
.pio_words
[2] =
606 GPMI_ECCCTRL_ENABLE_ECC
|
607 GPMI_ECCCTRL_ECC_CMD_DECODE
|
608 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
609 d
->cmd
.pio_words
[3] = mtd
->writesize
+ mtd
->oobsize
;
610 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
611 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
613 mxs_dma_desc_append(channel
, d
);
615 /* Compile the DMA descriptor - disable the BCH block. */
616 d
= mxs_nand_get_dma_desc(nand_info
);
618 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
619 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
620 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
624 d
->cmd
.pio_words
[0] =
625 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
626 GPMI_CTRL0_WORD_LENGTH
|
627 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
628 GPMI_CTRL0_ADDRESS_NAND_DATA
|
629 (mtd
->writesize
+ mtd
->oobsize
);
630 d
->cmd
.pio_words
[1] = 0;
631 d
->cmd
.pio_words
[2] = 0;
633 mxs_dma_desc_append(channel
, d
);
635 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
636 d
= mxs_nand_get_dma_desc(nand_info
);
638 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
639 MXS_DMA_DESC_DEC_SEM
;
643 mxs_dma_desc_append(channel
, d
);
645 /* Invalidate caches */
646 mxs_nand_inval_data_buf(nand_info
);
648 /* Execute the DMA chain. */
649 ret
= mxs_dma_go(channel
);
651 printf("MXS NAND: DMA read error\n");
655 ret
= mxs_nand_wait_for_bch_complete();
657 printf("MXS NAND: BCH read timeout\n");
661 /* Invalidate caches */
662 mxs_nand_inval_data_buf(nand_info
);
664 /* Read DMA completed, now do the mark swapping. */
665 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
667 /* Loop over status bytes, accumulating ECC status. */
668 status
= nand_info
->oob_buf
+ mxs_nand_aux_status_offset();
669 for (i
= 0; i
< mxs_nand_ecc_chunk_cnt(mtd
->writesize
); i
++) {
670 if (status
[i
] == 0x00)
673 if (status
[i
] == 0xff)
676 if (status
[i
] == 0xfe) {
681 corrected
+= status
[i
];
684 /* Propagate ECC status to the owning MTD. */
685 mtd
->ecc_stats
.failed
+= failed
;
686 mtd
->ecc_stats
.corrected
+= corrected
;
689 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
690 * details about our policy for delivering the OOB.
692 * We fill the caller's buffer with set bits, and then copy the block
693 * mark to the caller's buffer. Note that, if block mark swapping was
694 * necessary, it has already been done, so we can rely on the first
695 * byte of the auxiliary buffer to contain the block mark.
697 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
699 nand
->oob_poi
[0] = nand_info
->oob_buf
[0];
701 memcpy(buf
, nand_info
->data_buf
, mtd
->writesize
);
704 mxs_nand_return_dma_descs(nand_info
);
710 * Write a page to NAND.
712 static int mxs_nand_ecc_write_page(struct mtd_info
*mtd
,
713 struct nand_chip
*nand
, const uint8_t *buf
,
714 int oob_required
, int page
)
716 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
717 struct mxs_dma_desc
*d
;
718 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
721 memcpy(nand_info
->data_buf
, buf
, mtd
->writesize
);
722 memcpy(nand_info
->oob_buf
, nand
->oob_poi
, mtd
->oobsize
);
724 /* Handle block mark swapping. */
725 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
727 /* Compile the DMA descriptor - write data. */
728 d
= mxs_nand_get_dma_desc(nand_info
);
730 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
731 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
732 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
736 d
->cmd
.pio_words
[0] =
737 GPMI_CTRL0_COMMAND_MODE_WRITE
|
738 GPMI_CTRL0_WORD_LENGTH
|
739 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
740 GPMI_CTRL0_ADDRESS_NAND_DATA
;
741 d
->cmd
.pio_words
[1] = 0;
742 d
->cmd
.pio_words
[2] =
743 GPMI_ECCCTRL_ENABLE_ECC
|
744 GPMI_ECCCTRL_ECC_CMD_ENCODE
|
745 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
746 d
->cmd
.pio_words
[3] = (mtd
->writesize
+ mtd
->oobsize
);
747 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
748 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
750 mxs_dma_desc_append(channel
, d
);
753 mxs_nand_flush_data_buf(nand_info
);
755 /* Execute the DMA chain. */
756 ret
= mxs_dma_go(channel
);
758 printf("MXS NAND: DMA write error\n");
762 ret
= mxs_nand_wait_for_bch_complete();
764 printf("MXS NAND: BCH write timeout\n");
769 mxs_nand_return_dma_descs(nand_info
);
774 * Read OOB from NAND.
776 * This function is a veneer that replaces the function originally installed by
777 * the NAND Flash MTD code.
779 static int mxs_nand_hook_read_oob(struct mtd_info
*mtd
, loff_t from
,
780 struct mtd_oob_ops
*ops
)
782 struct nand_chip
*chip
= mtd_to_nand(mtd
);
783 struct mxs_nand_info
*nand_info
= nand_get_controller_data(chip
);
786 if (ops
->mode
== MTD_OPS_RAW
)
787 nand_info
->raw_oob_mode
= 1;
789 nand_info
->raw_oob_mode
= 0;
791 ret
= nand_info
->hooked_read_oob(mtd
, from
, ops
);
793 nand_info
->raw_oob_mode
= 0;
801 * This function is a veneer that replaces the function originally installed by
802 * the NAND Flash MTD code.
804 static int mxs_nand_hook_write_oob(struct mtd_info
*mtd
, loff_t to
,
805 struct mtd_oob_ops
*ops
)
807 struct nand_chip
*chip
= mtd_to_nand(mtd
);
808 struct mxs_nand_info
*nand_info
= nand_get_controller_data(chip
);
811 if (ops
->mode
== MTD_OPS_RAW
)
812 nand_info
->raw_oob_mode
= 1;
814 nand_info
->raw_oob_mode
= 0;
816 ret
= nand_info
->hooked_write_oob(mtd
, to
, ops
);
818 nand_info
->raw_oob_mode
= 0;
824 * Mark a block bad in NAND.
826 * This function is a veneer that replaces the function originally installed by
827 * the NAND Flash MTD code.
829 static int mxs_nand_hook_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
831 struct nand_chip
*chip
= mtd_to_nand(mtd
);
832 struct mxs_nand_info
*nand_info
= nand_get_controller_data(chip
);
835 nand_info
->marking_block_bad
= 1;
837 ret
= nand_info
->hooked_block_markbad(mtd
, ofs
);
839 nand_info
->marking_block_bad
= 0;
845 * There are several places in this driver where we have to handle the OOB and
846 * block marks. This is the function where things are the most complicated, so
847 * this is where we try to explain it all. All the other places refer back to
850 * These are the rules, in order of decreasing importance:
852 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
853 * write operations take measures to protect it.
855 * 2) In read operations, the first byte of the OOB we return must reflect the
856 * true state of the block mark, no matter where that block mark appears in
859 * 3) ECC-based read operations return an OOB full of set bits (since we never
860 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
863 * 4) "Raw" read operations return a direct view of the physical bytes in the
864 * page, using the conventional definition of which bytes are data and which
865 * are OOB. This gives the caller a way to see the actual, physical bytes
866 * in the page, without the distortions applied by our ECC engine.
868 * What we do for this specific read operation depends on whether we're doing
869 * "raw" read, or an ECC-based read.
871 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
872 * easy. When reading a page, for example, the NAND Flash MTD code calls our
873 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
874 * ECC-based or raw view of the page is implicit in which function it calls
875 * (there is a similar pair of ECC-based/raw functions for writing).
877 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
878 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
879 * caller wants an ECC-based or raw view of the page is not propagated down to
882 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
883 * ecc.read_oob and ecc.write_oob function pointers in the owning
884 * struct mtd_info with our own functions. These hook functions set the
885 * raw_oob_mode field so that, when control finally arrives here, we'll know
888 static int mxs_nand_ecc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
891 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
894 * First, fill in the OOB buffer. If we're doing a raw read, we need to
895 * get the bytes from the physical page. If we're not doing a raw read,
896 * we need to fill the buffer with set bits.
898 if (nand_info
->raw_oob_mode
) {
900 * If control arrives here, we're doing a "raw" read. Send the
901 * command to read the conventional OOB and read it.
903 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
904 nand
->read_buf(mtd
, nand
->oob_poi
, mtd
->oobsize
);
907 * If control arrives here, we're not doing a "raw" read. Fill
908 * the OOB buffer with set bits and correct the block mark.
910 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
912 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
913 mxs_nand_read_buf(mtd
, nand
->oob_poi
, 1);
921 * Write OOB data to NAND.
923 static int mxs_nand_ecc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
926 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
927 uint8_t block_mark
= 0;
930 * There are fundamental incompatibilities between the i.MX GPMI NFC and
931 * the NAND Flash MTD model that make it essentially impossible to write
932 * the out-of-band bytes.
934 * We permit *ONE* exception. If the *intent* of writing the OOB is to
935 * mark a block bad, we can do that.
938 if (!nand_info
->marking_block_bad
) {
939 printf("NXS NAND: Writing OOB isn't supported\n");
943 /* Write the block mark. */
944 nand
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
945 nand
->write_buf(mtd
, &block_mark
, 1);
946 nand
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
948 /* Check if it worked. */
949 if (nand
->waitfunc(mtd
, nand
) & NAND_STATUS_FAIL
)
956 * Claims all blocks are good.
958 * In principle, this function is *only* called when the NAND Flash MTD system
959 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
960 * the driver for bad block information.
962 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
963 * this function is *only* called when we take it away.
965 * Thus, this function is only called when we want *all* blocks to look good,
966 * so it *always* return success.
968 static int mxs_nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
974 * Nominally, the purpose of this function is to look for or create the bad
975 * block table. In fact, since the we call this function at the very end of
976 * the initialization process started by nand_scan(), and we doesn't have a
977 * more formal mechanism, we "hook" this function to continue init process.
979 * At this point, the physical NAND Flash chips have been identified and
980 * counted, so we know the physical geometry. This enables us to make some
981 * important configuration decisions.
983 * The return value of this function propagates directly back to this driver's
984 * call to nand_scan(). Anything other than zero will cause this driver to
985 * tear everything down and declare failure.
987 static int mxs_nand_scan_bbt(struct mtd_info
*mtd
)
989 struct nand_chip
*nand
= mtd_to_nand(mtd
);
990 struct mxs_nand_info
*nand_info
= nand_get_controller_data(nand
);
991 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
994 if (mtd
->oobsize
> MXS_NAND_CHUNK_DATA_CHUNK_SIZE
) {
996 chunk_data_size
= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
* 2;
999 if (mtd
->oobsize
> chunk_data_size
) {
1000 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size
);
1004 /* Configure BCH and set NFC geometry */
1005 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
1007 /* Configure layout 0 */
1008 tmp
= (mxs_nand_ecc_chunk_cnt(mtd
->writesize
) - 1)
1009 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET
;
1010 tmp
|= MXS_NAND_METADATA_SIZE
<< BCH_FLASHLAYOUT0_META_SIZE_OFFSET
;
1011 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
1012 << BCH_FLASHLAYOUT0_ECC0_OFFSET
;
1013 tmp
|= chunk_data_size
>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
1014 tmp
|= (14 == galois_field
? 1 : 0) <<
1015 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET
;
1016 writel(tmp
, &bch_regs
->hw_bch_flash0layout0
);
1018 tmp
= (mtd
->writesize
+ mtd
->oobsize
)
1019 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET
;
1020 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
1021 << BCH_FLASHLAYOUT1_ECCN_OFFSET
;
1022 tmp
|= chunk_data_size
>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
1023 tmp
|= (14 == galois_field
? 1 : 0) <<
1024 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET
;
1025 writel(tmp
, &bch_regs
->hw_bch_flash0layout1
);
1027 /* Set *all* chip selects to use layout 0 */
1028 writel(0, &bch_regs
->hw_bch_layoutselect
);
1030 /* Enable BCH complete interrupt */
1031 writel(BCH_CTRL_COMPLETE_IRQ_EN
, &bch_regs
->hw_bch_ctrl_set
);
1033 /* Hook some operations at the MTD level. */
1034 if (mtd
->_read_oob
!= mxs_nand_hook_read_oob
) {
1035 nand_info
->hooked_read_oob
= mtd
->_read_oob
;
1036 mtd
->_read_oob
= mxs_nand_hook_read_oob
;
1039 if (mtd
->_write_oob
!= mxs_nand_hook_write_oob
) {
1040 nand_info
->hooked_write_oob
= mtd
->_write_oob
;
1041 mtd
->_write_oob
= mxs_nand_hook_write_oob
;
1044 if (mtd
->_block_markbad
!= mxs_nand_hook_block_markbad
) {
1045 nand_info
->hooked_block_markbad
= mtd
->_block_markbad
;
1046 mtd
->_block_markbad
= mxs_nand_hook_block_markbad
;
1049 /* We use the reference implementation for bad block management. */
1050 return nand_default_bbt(mtd
);
1054 * Allocate DMA buffers
1056 int mxs_nand_alloc_buffers(struct mxs_nand_info
*nand_info
)
1059 const int size
= NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
;
1061 nand_info
->data_buf_size
= roundup(size
, MXS_DMA_ALIGNMENT
);
1064 buf
= memalign(MXS_DMA_ALIGNMENT
, nand_info
->data_buf_size
);
1066 printf("MXS NAND: Error allocating DMA buffers\n");
1070 memset(buf
, 0, nand_info
->data_buf_size
);
1072 nand_info
->data_buf
= buf
;
1073 nand_info
->oob_buf
= buf
+ NAND_MAX_PAGESIZE
;
1074 /* Command buffers */
1075 nand_info
->cmd_buf
= memalign(MXS_DMA_ALIGNMENT
,
1076 MXS_NAND_COMMAND_BUFFER_SIZE
);
1077 if (!nand_info
->cmd_buf
) {
1079 printf("MXS NAND: Error allocating command buffers\n");
1082 memset(nand_info
->cmd_buf
, 0, MXS_NAND_COMMAND_BUFFER_SIZE
);
1083 nand_info
->cmd_queue_len
= 0;
1089 * Initializes the NFC hardware.
1091 int mxs_nand_init(struct mxs_nand_info
*info
)
1093 struct mxs_gpmi_regs
*gpmi_regs
=
1094 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
1095 struct mxs_bch_regs
*bch_regs
=
1096 (struct mxs_bch_regs
*)MXS_BCH_BASE
;
1097 int i
= 0, j
, ret
= 0;
1099 info
->desc
= malloc(sizeof(struct mxs_dma_desc
*) *
1100 MXS_NAND_DMA_DESCRIPTOR_COUNT
);
1106 /* Allocate the DMA descriptors. */
1107 for (i
= 0; i
< MXS_NAND_DMA_DESCRIPTOR_COUNT
; i
++) {
1108 info
->desc
[i
] = mxs_dma_desc_alloc();
1109 if (!info
->desc
[i
]) {
1115 /* Init the DMA controller. */
1117 for (j
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
;
1118 j
<= MXS_DMA_CHANNEL_AHB_APBH_GPMI7
; j
++) {
1119 ret
= mxs_dma_init_channel(j
);
1124 /* Reset the GPMI block. */
1125 mxs_reset_block(&gpmi_regs
->hw_gpmi_ctrl0_reg
);
1126 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
1129 * Choose NAND mode, set IRQ polarity, disable write protection and
1132 clrsetbits_le32(&gpmi_regs
->hw_gpmi_ctrl1
,
1133 GPMI_CTRL1_GPMI_MODE
,
1134 GPMI_CTRL1_ATA_IRQRDY_POLARITY
| GPMI_CTRL1_DEV_RESET
|
1135 GPMI_CTRL1_BCH_MODE
);
1140 for (--j
; j
>= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
; j
--)
1143 for (--i
; i
>= 0; i
--)
1144 mxs_dma_desc_free(info
->desc
[i
]);
1148 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1153 * This function is called during the driver binding process.
1155 * @param pdev the device structure used to store device specific
1156 * information that is used by the suspend, resume and
1159 * @return The function always returns 0.
1161 int board_nand_init(struct nand_chip
*nand
)
1163 struct mxs_nand_info
*nand_info
;
1166 nand_info
= malloc(sizeof(struct mxs_nand_info
));
1168 printf("MXS NAND: Failed to allocate private data\n");
1171 memset(nand_info
, 0, sizeof(struct mxs_nand_info
));
1173 err
= mxs_nand_alloc_buffers(nand_info
);
1177 err
= mxs_nand_init(nand_info
);
1181 memset(&fake_ecc_layout
, 0, sizeof(fake_ecc_layout
));
1183 nand_set_controller_data(nand
, nand_info
);
1184 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1186 nand
->cmd_ctrl
= mxs_nand_cmd_ctrl
;
1188 nand
->dev_ready
= mxs_nand_device_ready
;
1189 nand
->select_chip
= mxs_nand_select_chip
;
1190 nand
->block_bad
= mxs_nand_block_bad
;
1191 nand
->scan_bbt
= mxs_nand_scan_bbt
;
1193 nand
->read_byte
= mxs_nand_read_byte
;
1195 nand
->read_buf
= mxs_nand_read_buf
;
1196 nand
->write_buf
= mxs_nand_write_buf
;
1198 nand
->ecc
.read_page
= mxs_nand_ecc_read_page
;
1199 nand
->ecc
.write_page
= mxs_nand_ecc_write_page
;
1200 nand
->ecc
.read_oob
= mxs_nand_ecc_read_oob
;
1201 nand
->ecc
.write_oob
= mxs_nand_ecc_write_oob
;
1203 nand
->ecc
.layout
= &fake_ecc_layout
;
1204 nand
->ecc
.mode
= NAND_ECC_HW
;
1205 nand
->ecc
.bytes
= 9;
1206 nand
->ecc
.size
= 512;
1207 nand
->ecc
.strength
= 8;
1212 free(nand_info
->data_buf
);
1213 free(nand_info
->cmd_buf
);