2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <asm/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if defined(CONFIG_MX6)
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
42 #define MXS_NAND_BCH_TIMEOUT 10000
44 struct mxs_nand_info
{
47 uint32_t cmd_queue_len
;
48 uint32_t data_buf_size
;
54 uint8_t marking_block_bad
;
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob
)(struct mtd_info
*mtd
,
59 loff_t from
, struct mtd_oob_ops
*ops
);
60 int (*hooked_write_oob
)(struct mtd_info
*mtd
,
61 loff_t to
, struct mtd_oob_ops
*ops
);
62 int (*hooked_block_markbad
)(struct mtd_info
*mtd
,
66 struct mxs_dma_desc
**desc
;
70 struct nand_ecclayout fake_ecc_layout
;
73 * Cache management functions
75 #ifndef CONFIG_SYS_DCACHE_OFF
76 static void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
)
78 uint32_t addr
= (uint32_t)info
->data_buf
;
80 flush_dcache_range(addr
, addr
+ info
->data_buf_size
);
83 static void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
)
85 uint32_t addr
= (uint32_t)info
->data_buf
;
87 invalidate_dcache_range(addr
, addr
+ info
->data_buf_size
);
90 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
)
92 uint32_t addr
= (uint32_t)info
->cmd_buf
;
94 flush_dcache_range(addr
, addr
+ MXS_NAND_COMMAND_BUFFER_SIZE
);
97 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info
*info
) {}
98 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info
*info
) {}
99 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info
*info
) {}
102 static struct mxs_dma_desc
*mxs_nand_get_dma_desc(struct mxs_nand_info
*info
)
104 struct mxs_dma_desc
*desc
;
106 if (info
->desc_index
>= MXS_NAND_DMA_DESCRIPTOR_COUNT
) {
107 printf("MXS NAND: Too many DMA descriptors requested\n");
111 desc
= info
->desc
[info
->desc_index
];
117 static void mxs_nand_return_dma_descs(struct mxs_nand_info
*info
)
120 struct mxs_dma_desc
*desc
;
122 for (i
= 0; i
< info
->desc_index
; i
++) {
123 desc
= info
->desc
[i
];
124 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
125 desc
->address
= (dma_addr_t
)desc
;
128 info
->desc_index
= 0;
131 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size
)
133 return page_data_size
/ MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
136 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength
)
138 return ecc_strength
* 13;
141 static uint32_t mxs_nand_aux_status_offset(void)
143 return (MXS_NAND_METADATA_SIZE
+ 0x3) & ~0x3;
146 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size
,
147 uint32_t page_oob_size
)
152 * Determine the ECC layout with the formula:
153 * ECC bits per chunk = (total page spare data bits) /
154 * (bits per ECC level) / (chunks per page)
156 * total page spare data bits =
157 * (page oob size - meta data size) * (bits per byte)
159 ecc_strength
= ((page_oob_size
- MXS_NAND_METADATA_SIZE
) * 8)
160 / (13 * mxs_nand_ecc_chunk_cnt(page_data_size
));
162 return round_down(ecc_strength
, 2);
165 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size
,
166 uint32_t ecc_strength
)
168 uint32_t chunk_data_size_in_bits
;
169 uint32_t chunk_ecc_size_in_bits
;
170 uint32_t chunk_total_size_in_bits
;
171 uint32_t block_mark_chunk_number
;
172 uint32_t block_mark_chunk_bit_offset
;
173 uint32_t block_mark_bit_offset
;
175 chunk_data_size_in_bits
= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
* 8;
176 chunk_ecc_size_in_bits
= mxs_nand_ecc_size_in_bits(ecc_strength
);
178 chunk_total_size_in_bits
=
179 chunk_data_size_in_bits
+ chunk_ecc_size_in_bits
;
181 /* Compute the bit offset of the block mark within the physical page. */
182 block_mark_bit_offset
= page_data_size
* 8;
184 /* Subtract the metadata bits. */
185 block_mark_bit_offset
-= MXS_NAND_METADATA_SIZE
* 8;
188 * Compute the chunk number (starting at zero) in which the block mark
191 block_mark_chunk_number
=
192 block_mark_bit_offset
/ chunk_total_size_in_bits
;
195 * Compute the bit offset of the block mark within its chunk, and
198 block_mark_chunk_bit_offset
= block_mark_bit_offset
-
199 (block_mark_chunk_number
* chunk_total_size_in_bits
);
201 if (block_mark_chunk_bit_offset
> chunk_data_size_in_bits
)
205 * Now that we know the chunk number in which the block mark appears,
206 * we can subtract all the ECC bits that appear before it.
208 block_mark_bit_offset
-=
209 block_mark_chunk_number
* chunk_ecc_size_in_bits
;
211 return block_mark_bit_offset
;
214 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info
*mtd
)
216 uint32_t ecc_strength
;
217 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
218 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) >> 3;
221 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info
*mtd
)
223 uint32_t ecc_strength
;
224 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
225 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) & 0x7;
229 * Wait for BCH complete IRQ and clear the IRQ
231 static int mxs_nand_wait_for_bch_complete(void)
233 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
234 int timeout
= MXS_NAND_BCH_TIMEOUT
;
237 ret
= mxs_wait_mask_set(&bch_regs
->hw_bch_ctrl_reg
,
238 BCH_CTRL_COMPLETE_IRQ
, timeout
);
240 writel(BCH_CTRL_COMPLETE_IRQ
, &bch_regs
->hw_bch_ctrl_clr
);
246 * This is the function that we install in the cmd_ctrl function pointer of the
247 * owning struct nand_chip. The only functions in the reference implementation
248 * that use these functions pointers are cmdfunc and select_chip.
250 * In this driver, we implement our own select_chip, so this function will only
251 * be called by the reference implementation's cmdfunc. For this reason, we can
252 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
255 static void mxs_nand_cmd_ctrl(struct mtd_info
*mtd
, int data
, unsigned int ctrl
)
257 struct nand_chip
*nand
= mtd
->priv
;
258 struct mxs_nand_info
*nand_info
= nand
->priv
;
259 struct mxs_dma_desc
*d
;
260 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
264 * If this condition is true, something is _VERY_ wrong in MTD
267 if (nand_info
->cmd_queue_len
== MXS_NAND_COMMAND_BUFFER_SIZE
) {
268 printf("MXS NAND: Command queue too long\n");
273 * Every operation begins with a command byte and a series of zero or
274 * more address bytes. These are distinguished by either the Address
275 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
276 * asserted. When MTD is ready to execute the command, it will
277 * deasert both latch enables.
279 * Rather than run a separate DMA operation for every single byte, we
280 * queue them up and run a single DMA operation for the entire series
281 * of command and data bytes.
283 if (ctrl
& (NAND_ALE
| NAND_CLE
)) {
284 if (data
!= NAND_CMD_NONE
)
285 nand_info
->cmd_buf
[nand_info
->cmd_queue_len
++] = data
;
290 * If control arrives here, MTD has deasserted both the ALE and CLE,
291 * which means it's ready to run an operation. Check if we have any
294 if (nand_info
->cmd_queue_len
== 0)
297 /* Compile the DMA descriptor -- a descriptor that sends command. */
298 d
= mxs_nand_get_dma_desc(nand_info
);
300 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
301 MXS_DMA_DESC_CHAIN
| MXS_DMA_DESC_DEC_SEM
|
302 MXS_DMA_DESC_WAIT4END
| (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
303 (nand_info
->cmd_queue_len
<< MXS_DMA_DESC_BYTES_OFFSET
);
305 d
->cmd
.address
= (dma_addr_t
)nand_info
->cmd_buf
;
307 d
->cmd
.pio_words
[0] =
308 GPMI_CTRL0_COMMAND_MODE_WRITE
|
309 GPMI_CTRL0_WORD_LENGTH
|
310 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
311 GPMI_CTRL0_ADDRESS_NAND_CLE
|
312 GPMI_CTRL0_ADDRESS_INCREMENT
|
313 nand_info
->cmd_queue_len
;
315 mxs_dma_desc_append(channel
, d
);
318 mxs_nand_flush_cmd_buf(nand_info
);
320 /* Execute the DMA chain. */
321 ret
= mxs_dma_go(channel
);
323 printf("MXS NAND: Error sending command\n");
325 mxs_nand_return_dma_descs(nand_info
);
327 /* Reset the command queue. */
328 nand_info
->cmd_queue_len
= 0;
332 * Test if the NAND flash is ready.
334 static int mxs_nand_device_ready(struct mtd_info
*mtd
)
336 struct nand_chip
*chip
= mtd
->priv
;
337 struct mxs_nand_info
*nand_info
= chip
->priv
;
338 struct mxs_gpmi_regs
*gpmi_regs
=
339 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
342 tmp
= readl(&gpmi_regs
->hw_gpmi_stat
);
343 tmp
>>= (GPMI_STAT_READY_BUSY_OFFSET
+ nand_info
->cur_chip
);
349 * Select the NAND chip.
351 static void mxs_nand_select_chip(struct mtd_info
*mtd
, int chip
)
353 struct nand_chip
*nand
= mtd
->priv
;
354 struct mxs_nand_info
*nand_info
= nand
->priv
;
356 nand_info
->cur_chip
= chip
;
360 * Handle block mark swapping.
362 * Note that, when this function is called, it doesn't know whether it's
363 * swapping the block mark, or swapping it *back* -- but it doesn't matter
364 * because the the operation is the same.
366 static void mxs_nand_swap_block_mark(struct mtd_info
*mtd
,
367 uint8_t *data_buf
, uint8_t *oob_buf
)
375 bit_offset
= mxs_nand_mark_bit_offset(mtd
);
376 buf_offset
= mxs_nand_mark_byte_offset(mtd
);
379 * Get the byte from the data area that overlays the block mark. Since
380 * the ECC engine applies its own view to the bits in the page, the
381 * physical block mark won't (in general) appear on a byte boundary in
384 src
= data_buf
[buf_offset
] >> bit_offset
;
385 src
|= data_buf
[buf_offset
+ 1] << (8 - bit_offset
);
391 data_buf
[buf_offset
] &= ~(0xff << bit_offset
);
392 data_buf
[buf_offset
+ 1] &= 0xff << bit_offset
;
394 data_buf
[buf_offset
] |= dst
<< bit_offset
;
395 data_buf
[buf_offset
+ 1] |= dst
>> (8 - bit_offset
);
399 * Read data from NAND.
401 static void mxs_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int length
)
403 struct nand_chip
*nand
= mtd
->priv
;
404 struct mxs_nand_info
*nand_info
= nand
->priv
;
405 struct mxs_dma_desc
*d
;
406 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
409 if (length
> NAND_MAX_PAGESIZE
) {
410 printf("MXS NAND: DMA buffer too big\n");
415 printf("MXS NAND: DMA buffer is NULL\n");
419 /* Compile the DMA descriptor - a descriptor that reads data. */
420 d
= mxs_nand_get_dma_desc(nand_info
);
422 MXS_DMA_DESC_COMMAND_DMA_WRITE
| MXS_DMA_DESC_IRQ
|
423 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
424 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
425 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
427 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
429 d
->cmd
.pio_words
[0] =
430 GPMI_CTRL0_COMMAND_MODE_READ
|
431 GPMI_CTRL0_WORD_LENGTH
|
432 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
433 GPMI_CTRL0_ADDRESS_NAND_DATA
|
436 mxs_dma_desc_append(channel
, d
);
439 * A DMA descriptor that waits for the command to end and the chip to
442 * I think we actually should *not* be waiting for the chip to become
443 * ready because, after all, we don't care. I think the original code
444 * did that and no one has re-thought it yet.
446 d
= mxs_nand_get_dma_desc(nand_info
);
448 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
449 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_DEC_SEM
|
450 MXS_DMA_DESC_WAIT4END
| (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
454 d
->cmd
.pio_words
[0] =
455 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
456 GPMI_CTRL0_WORD_LENGTH
|
457 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
458 GPMI_CTRL0_ADDRESS_NAND_DATA
;
460 mxs_dma_desc_append(channel
, d
);
462 /* Execute the DMA chain. */
463 ret
= mxs_dma_go(channel
);
465 printf("MXS NAND: DMA read error\n");
469 /* Invalidate caches */
470 mxs_nand_inval_data_buf(nand_info
);
472 memcpy(buf
, nand_info
->data_buf
, length
);
475 mxs_nand_return_dma_descs(nand_info
);
479 * Write data to NAND.
481 static void mxs_nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
484 struct nand_chip
*nand
= mtd
->priv
;
485 struct mxs_nand_info
*nand_info
= nand
->priv
;
486 struct mxs_dma_desc
*d
;
487 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
490 if (length
> NAND_MAX_PAGESIZE
) {
491 printf("MXS NAND: DMA buffer too big\n");
496 printf("MXS NAND: DMA buffer is NULL\n");
500 memcpy(nand_info
->data_buf
, buf
, length
);
502 /* Compile the DMA descriptor - a descriptor that writes data. */
503 d
= mxs_nand_get_dma_desc(nand_info
);
505 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
506 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
507 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
508 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
510 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
512 d
->cmd
.pio_words
[0] =
513 GPMI_CTRL0_COMMAND_MODE_WRITE
|
514 GPMI_CTRL0_WORD_LENGTH
|
515 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
516 GPMI_CTRL0_ADDRESS_NAND_DATA
|
519 mxs_dma_desc_append(channel
, d
);
522 mxs_nand_flush_data_buf(nand_info
);
524 /* Execute the DMA chain. */
525 ret
= mxs_dma_go(channel
);
527 printf("MXS NAND: DMA write error\n");
529 mxs_nand_return_dma_descs(nand_info
);
533 * Read a single byte from NAND.
535 static uint8_t mxs_nand_read_byte(struct mtd_info
*mtd
)
538 mxs_nand_read_buf(mtd
, &buf
, 1);
543 * Read a page from NAND.
545 static int mxs_nand_ecc_read_page(struct mtd_info
*mtd
, struct nand_chip
*nand
,
546 uint8_t *buf
, int oob_required
,
549 struct mxs_nand_info
*nand_info
= nand
->priv
;
550 struct mxs_dma_desc
*d
;
551 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
552 uint32_t corrected
= 0, failed
= 0;
556 /* Compile the DMA descriptor - wait for ready. */
557 d
= mxs_nand_get_dma_desc(nand_info
);
559 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
560 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
561 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
565 d
->cmd
.pio_words
[0] =
566 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
567 GPMI_CTRL0_WORD_LENGTH
|
568 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
569 GPMI_CTRL0_ADDRESS_NAND_DATA
;
571 mxs_dma_desc_append(channel
, d
);
573 /* Compile the DMA descriptor - enable the BCH block and read. */
574 d
= mxs_nand_get_dma_desc(nand_info
);
576 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
577 MXS_DMA_DESC_WAIT4END
| (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
581 d
->cmd
.pio_words
[0] =
582 GPMI_CTRL0_COMMAND_MODE_READ
|
583 GPMI_CTRL0_WORD_LENGTH
|
584 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
585 GPMI_CTRL0_ADDRESS_NAND_DATA
|
586 (mtd
->writesize
+ mtd
->oobsize
);
587 d
->cmd
.pio_words
[1] = 0;
588 d
->cmd
.pio_words
[2] =
589 GPMI_ECCCTRL_ENABLE_ECC
|
590 GPMI_ECCCTRL_ECC_CMD_DECODE
|
591 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
592 d
->cmd
.pio_words
[3] = mtd
->writesize
+ mtd
->oobsize
;
593 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
594 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
596 mxs_dma_desc_append(channel
, d
);
598 /* Compile the DMA descriptor - disable the BCH block. */
599 d
= mxs_nand_get_dma_desc(nand_info
);
601 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
602 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
603 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
607 d
->cmd
.pio_words
[0] =
608 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
609 GPMI_CTRL0_WORD_LENGTH
|
610 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
611 GPMI_CTRL0_ADDRESS_NAND_DATA
|
612 (mtd
->writesize
+ mtd
->oobsize
);
613 d
->cmd
.pio_words
[1] = 0;
614 d
->cmd
.pio_words
[2] = 0;
616 mxs_dma_desc_append(channel
, d
);
618 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
619 d
= mxs_nand_get_dma_desc(nand_info
);
621 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
622 MXS_DMA_DESC_DEC_SEM
;
626 mxs_dma_desc_append(channel
, d
);
628 /* Execute the DMA chain. */
629 ret
= mxs_dma_go(channel
);
631 printf("MXS NAND: DMA read error\n");
635 ret
= mxs_nand_wait_for_bch_complete();
637 printf("MXS NAND: BCH read timeout\n");
641 /* Invalidate caches */
642 mxs_nand_inval_data_buf(nand_info
);
644 /* Read DMA completed, now do the mark swapping. */
645 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
647 /* Loop over status bytes, accumulating ECC status. */
648 status
= nand_info
->oob_buf
+ mxs_nand_aux_status_offset();
649 for (i
= 0; i
< mxs_nand_ecc_chunk_cnt(mtd
->writesize
); i
++) {
650 if (status
[i
] == 0x00)
653 if (status
[i
] == 0xff)
656 if (status
[i
] == 0xfe) {
661 corrected
+= status
[i
];
664 /* Propagate ECC status to the owning MTD. */
665 mtd
->ecc_stats
.failed
+= failed
;
666 mtd
->ecc_stats
.corrected
+= corrected
;
669 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
670 * details about our policy for delivering the OOB.
672 * We fill the caller's buffer with set bits, and then copy the block
673 * mark to the caller's buffer. Note that, if block mark swapping was
674 * necessary, it has already been done, so we can rely on the first
675 * byte of the auxiliary buffer to contain the block mark.
677 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
679 nand
->oob_poi
[0] = nand_info
->oob_buf
[0];
681 memcpy(buf
, nand_info
->data_buf
, mtd
->writesize
);
684 mxs_nand_return_dma_descs(nand_info
);
690 * Write a page to NAND.
692 static int mxs_nand_ecc_write_page(struct mtd_info
*mtd
,
693 struct nand_chip
*nand
, const uint8_t *buf
,
696 struct mxs_nand_info
*nand_info
= nand
->priv
;
697 struct mxs_dma_desc
*d
;
698 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
701 memcpy(nand_info
->data_buf
, buf
, mtd
->writesize
);
702 memcpy(nand_info
->oob_buf
, nand
->oob_poi
, mtd
->oobsize
);
704 /* Handle block mark swapping. */
705 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
707 /* Compile the DMA descriptor - write data. */
708 d
= mxs_nand_get_dma_desc(nand_info
);
710 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
711 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
712 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
716 d
->cmd
.pio_words
[0] =
717 GPMI_CTRL0_COMMAND_MODE_WRITE
|
718 GPMI_CTRL0_WORD_LENGTH
|
719 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
720 GPMI_CTRL0_ADDRESS_NAND_DATA
;
721 d
->cmd
.pio_words
[1] = 0;
722 d
->cmd
.pio_words
[2] =
723 GPMI_ECCCTRL_ENABLE_ECC
|
724 GPMI_ECCCTRL_ECC_CMD_ENCODE
|
725 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
726 d
->cmd
.pio_words
[3] = (mtd
->writesize
+ mtd
->oobsize
);
727 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
728 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
730 mxs_dma_desc_append(channel
, d
);
733 mxs_nand_flush_data_buf(nand_info
);
735 /* Execute the DMA chain. */
736 ret
= mxs_dma_go(channel
);
738 printf("MXS NAND: DMA write error\n");
742 ret
= mxs_nand_wait_for_bch_complete();
744 printf("MXS NAND: BCH write timeout\n");
749 mxs_nand_return_dma_descs(nand_info
);
754 * Read OOB from NAND.
756 * This function is a veneer that replaces the function originally installed by
757 * the NAND Flash MTD code.
759 static int mxs_nand_hook_read_oob(struct mtd_info
*mtd
, loff_t from
,
760 struct mtd_oob_ops
*ops
)
762 struct nand_chip
*chip
= mtd
->priv
;
763 struct mxs_nand_info
*nand_info
= chip
->priv
;
766 if (ops
->mode
== MTD_OPS_RAW
)
767 nand_info
->raw_oob_mode
= 1;
769 nand_info
->raw_oob_mode
= 0;
771 ret
= nand_info
->hooked_read_oob(mtd
, from
, ops
);
773 nand_info
->raw_oob_mode
= 0;
781 * This function is a veneer that replaces the function originally installed by
782 * the NAND Flash MTD code.
784 static int mxs_nand_hook_write_oob(struct mtd_info
*mtd
, loff_t to
,
785 struct mtd_oob_ops
*ops
)
787 struct nand_chip
*chip
= mtd
->priv
;
788 struct mxs_nand_info
*nand_info
= chip
->priv
;
791 if (ops
->mode
== MTD_OPS_RAW
)
792 nand_info
->raw_oob_mode
= 1;
794 nand_info
->raw_oob_mode
= 0;
796 ret
= nand_info
->hooked_write_oob(mtd
, to
, ops
);
798 nand_info
->raw_oob_mode
= 0;
804 * Mark a block bad in NAND.
806 * This function is a veneer that replaces the function originally installed by
807 * the NAND Flash MTD code.
809 static int mxs_nand_hook_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
811 struct nand_chip
*chip
= mtd
->priv
;
812 struct mxs_nand_info
*nand_info
= chip
->priv
;
815 nand_info
->marking_block_bad
= 1;
817 ret
= nand_info
->hooked_block_markbad(mtd
, ofs
);
819 nand_info
->marking_block_bad
= 0;
825 * There are several places in this driver where we have to handle the OOB and
826 * block marks. This is the function where things are the most complicated, so
827 * this is where we try to explain it all. All the other places refer back to
830 * These are the rules, in order of decreasing importance:
832 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
833 * write operations take measures to protect it.
835 * 2) In read operations, the first byte of the OOB we return must reflect the
836 * true state of the block mark, no matter where that block mark appears in
839 * 3) ECC-based read operations return an OOB full of set bits (since we never
840 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
843 * 4) "Raw" read operations return a direct view of the physical bytes in the
844 * page, using the conventional definition of which bytes are data and which
845 * are OOB. This gives the caller a way to see the actual, physical bytes
846 * in the page, without the distortions applied by our ECC engine.
848 * What we do for this specific read operation depends on whether we're doing
849 * "raw" read, or an ECC-based read.
851 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
852 * easy. When reading a page, for example, the NAND Flash MTD code calls our
853 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
854 * ECC-based or raw view of the page is implicit in which function it calls
855 * (there is a similar pair of ECC-based/raw functions for writing).
857 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
858 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
859 * caller wants an ECC-based or raw view of the page is not propagated down to
862 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
863 * ecc.read_oob and ecc.write_oob function pointers in the owning
864 * struct mtd_info with our own functions. These hook functions set the
865 * raw_oob_mode field so that, when control finally arrives here, we'll know
868 static int mxs_nand_ecc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
871 struct mxs_nand_info
*nand_info
= nand
->priv
;
874 * First, fill in the OOB buffer. If we're doing a raw read, we need to
875 * get the bytes from the physical page. If we're not doing a raw read,
876 * we need to fill the buffer with set bits.
878 if (nand_info
->raw_oob_mode
) {
880 * If control arrives here, we're doing a "raw" read. Send the
881 * command to read the conventional OOB and read it.
883 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
884 nand
->read_buf(mtd
, nand
->oob_poi
, mtd
->oobsize
);
887 * If control arrives here, we're not doing a "raw" read. Fill
888 * the OOB buffer with set bits and correct the block mark.
890 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
892 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
893 mxs_nand_read_buf(mtd
, nand
->oob_poi
, 1);
901 * Write OOB data to NAND.
903 static int mxs_nand_ecc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
906 struct mxs_nand_info
*nand_info
= nand
->priv
;
907 uint8_t block_mark
= 0;
910 * There are fundamental incompatibilities between the i.MX GPMI NFC and
911 * the NAND Flash MTD model that make it essentially impossible to write
912 * the out-of-band bytes.
914 * We permit *ONE* exception. If the *intent* of writing the OOB is to
915 * mark a block bad, we can do that.
918 if (!nand_info
->marking_block_bad
) {
919 printf("NXS NAND: Writing OOB isn't supported\n");
923 /* Write the block mark. */
924 nand
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
925 nand
->write_buf(mtd
, &block_mark
, 1);
926 nand
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
928 /* Check if it worked. */
929 if (nand
->waitfunc(mtd
, nand
) & NAND_STATUS_FAIL
)
936 * Claims all blocks are good.
938 * In principle, this function is *only* called when the NAND Flash MTD system
939 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
940 * the driver for bad block information.
942 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
943 * this function is *only* called when we take it away.
945 * Thus, this function is only called when we want *all* blocks to look good,
946 * so it *always* return success.
948 static int mxs_nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
954 * Nominally, the purpose of this function is to look for or create the bad
955 * block table. In fact, since the we call this function at the very end of
956 * the initialization process started by nand_scan(), and we doesn't have a
957 * more formal mechanism, we "hook" this function to continue init process.
959 * At this point, the physical NAND Flash chips have been identified and
960 * counted, so we know the physical geometry. This enables us to make some
961 * important configuration decisions.
963 * The return value of this function propogates directly back to this driver's
964 * call to nand_scan(). Anything other than zero will cause this driver to
965 * tear everything down and declare failure.
967 static int mxs_nand_scan_bbt(struct mtd_info
*mtd
)
969 struct nand_chip
*nand
= mtd
->priv
;
970 struct mxs_nand_info
*nand_info
= nand
->priv
;
971 struct mxs_bch_regs
*bch_regs
= (struct mxs_bch_regs
*)MXS_BCH_BASE
;
974 /* Configure BCH and set NFC geometry */
975 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
977 /* Configure layout 0 */
978 tmp
= (mxs_nand_ecc_chunk_cnt(mtd
->writesize
) - 1)
979 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET
;
980 tmp
|= MXS_NAND_METADATA_SIZE
<< BCH_FLASHLAYOUT0_META_SIZE_OFFSET
;
981 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
982 << BCH_FLASHLAYOUT0_ECC0_OFFSET
;
983 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
984 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
985 writel(tmp
, &bch_regs
->hw_bch_flash0layout0
);
987 tmp
= (mtd
->writesize
+ mtd
->oobsize
)
988 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET
;
989 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
990 << BCH_FLASHLAYOUT1_ECCN_OFFSET
;
991 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
992 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT
;
993 writel(tmp
, &bch_regs
->hw_bch_flash0layout1
);
995 /* Set *all* chip selects to use layout 0 */
996 writel(0, &bch_regs
->hw_bch_layoutselect
);
998 /* Enable BCH complete interrupt */
999 writel(BCH_CTRL_COMPLETE_IRQ_EN
, &bch_regs
->hw_bch_ctrl_set
);
1001 /* Hook some operations at the MTD level. */
1002 if (mtd
->_read_oob
!= mxs_nand_hook_read_oob
) {
1003 nand_info
->hooked_read_oob
= mtd
->_read_oob
;
1004 mtd
->_read_oob
= mxs_nand_hook_read_oob
;
1007 if (mtd
->_write_oob
!= mxs_nand_hook_write_oob
) {
1008 nand_info
->hooked_write_oob
= mtd
->_write_oob
;
1009 mtd
->_write_oob
= mxs_nand_hook_write_oob
;
1012 if (mtd
->_block_markbad
!= mxs_nand_hook_block_markbad
) {
1013 nand_info
->hooked_block_markbad
= mtd
->_block_markbad
;
1014 mtd
->_block_markbad
= mxs_nand_hook_block_markbad
;
1017 /* We use the reference implementation for bad block management. */
1018 return nand_default_bbt(mtd
);
1022 * Allocate DMA buffers
1024 int mxs_nand_alloc_buffers(struct mxs_nand_info
*nand_info
)
1027 const int size
= NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
;
1029 nand_info
->data_buf_size
= roundup(size
, MXS_DMA_ALIGNMENT
);
1032 buf
= memalign(MXS_DMA_ALIGNMENT
, nand_info
->data_buf_size
);
1034 printf("MXS NAND: Error allocating DMA buffers\n");
1038 memset(buf
, 0, nand_info
->data_buf_size
);
1040 nand_info
->data_buf
= buf
;
1041 nand_info
->oob_buf
= buf
+ NAND_MAX_PAGESIZE
;
1042 /* Command buffers */
1043 nand_info
->cmd_buf
= memalign(MXS_DMA_ALIGNMENT
,
1044 MXS_NAND_COMMAND_BUFFER_SIZE
);
1045 if (!nand_info
->cmd_buf
) {
1047 printf("MXS NAND: Error allocating command buffers\n");
1050 memset(nand_info
->cmd_buf
, 0, MXS_NAND_COMMAND_BUFFER_SIZE
);
1051 nand_info
->cmd_queue_len
= 0;
1057 * Initializes the NFC hardware.
1059 int mxs_nand_init(struct mxs_nand_info
*info
)
1061 struct mxs_gpmi_regs
*gpmi_regs
=
1062 (struct mxs_gpmi_regs
*)MXS_GPMI_BASE
;
1063 struct mxs_bch_regs
*bch_regs
=
1064 (struct mxs_bch_regs
*)MXS_BCH_BASE
;
1067 info
->desc
= malloc(sizeof(struct mxs_dma_desc
*) *
1068 MXS_NAND_DMA_DESCRIPTOR_COUNT
);
1072 /* Allocate the DMA descriptors. */
1073 for (i
= 0; i
< MXS_NAND_DMA_DESCRIPTOR_COUNT
; i
++) {
1074 info
->desc
[i
] = mxs_dma_desc_alloc();
1079 /* Init the DMA controller. */
1080 for (j
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
;
1081 j
<= MXS_DMA_CHANNEL_AHB_APBH_GPMI7
; j
++) {
1082 if (mxs_dma_init_channel(j
))
1086 /* Reset the GPMI block. */
1087 mxs_reset_block(&gpmi_regs
->hw_gpmi_ctrl0_reg
);
1088 mxs_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
1091 * Choose NAND mode, set IRQ polarity, disable write protection and
1094 clrsetbits_le32(&gpmi_regs
->hw_gpmi_ctrl1
,
1095 GPMI_CTRL1_GPMI_MODE
,
1096 GPMI_CTRL1_ATA_IRQRDY_POLARITY
| GPMI_CTRL1_DEV_RESET
|
1097 GPMI_CTRL1_BCH_MODE
);
1102 for (--j
; j
>= 0; j
--)
1107 for (--i
; i
>= 0; i
--)
1108 mxs_dma_desc_free(info
->desc
[i
]);
1109 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1114 * This function is called during the driver binding process.
1116 * @param pdev the device structure used to store device specific
1117 * information that is used by the suspend, resume and
1120 * @return The function always returns 0.
1122 int board_nand_init(struct nand_chip
*nand
)
1124 struct mxs_nand_info
*nand_info
;
1127 nand_info
= malloc(sizeof(struct mxs_nand_info
));
1129 printf("MXS NAND: Failed to allocate private data\n");
1132 memset(nand_info
, 0, sizeof(struct mxs_nand_info
));
1134 err
= mxs_nand_alloc_buffers(nand_info
);
1138 err
= mxs_nand_init(nand_info
);
1142 memset(&fake_ecc_layout
, 0, sizeof(fake_ecc_layout
));
1144 nand
->priv
= nand_info
;
1145 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1147 nand
->cmd_ctrl
= mxs_nand_cmd_ctrl
;
1149 nand
->dev_ready
= mxs_nand_device_ready
;
1150 nand
->select_chip
= mxs_nand_select_chip
;
1151 nand
->block_bad
= mxs_nand_block_bad
;
1152 nand
->scan_bbt
= mxs_nand_scan_bbt
;
1154 nand
->read_byte
= mxs_nand_read_byte
;
1156 nand
->read_buf
= mxs_nand_read_buf
;
1157 nand
->write_buf
= mxs_nand_write_buf
;
1159 nand
->ecc
.read_page
= mxs_nand_ecc_read_page
;
1160 nand
->ecc
.write_page
= mxs_nand_ecc_write_page
;
1161 nand
->ecc
.read_oob
= mxs_nand_ecc_read_oob
;
1162 nand
->ecc
.write_oob
= mxs_nand_ecc_write_oob
;
1164 nand
->ecc
.layout
= &fake_ecc_layout
;
1165 nand
->ecc
.mode
= NAND_ECC_HW
;
1166 nand
->ecc
.bytes
= 9;
1167 nand
->ecc
.size
= 512;
1168 nand
->ecc
.strength
= 8;
1173 free(nand_info
->data_buf
);
1174 free(nand_info
->cmd_buf
);