2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/types.h>
33 #include <asm/errno.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/dma.h>
40 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
42 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
43 #define MXS_NAND_METADATA_SIZE 10
45 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
47 #define MXS_NAND_BCH_TIMEOUT 10000
49 struct mxs_nand_info
{
52 uint32_t cmd_queue_len
;
58 uint8_t marking_block_bad
;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob
)(struct mtd_info
*mtd
,
63 loff_t from
, struct mtd_oob_ops
*ops
);
64 int (*hooked_write_oob
)(struct mtd_info
*mtd
,
65 loff_t to
, struct mtd_oob_ops
*ops
);
66 int (*hooked_block_markbad
)(struct mtd_info
*mtd
,
70 struct mxs_dma_desc
**desc
;
74 struct nand_ecclayout fake_ecc_layout
;
76 static struct mxs_dma_desc
*mxs_nand_get_dma_desc(struct mxs_nand_info
*info
)
78 struct mxs_dma_desc
*desc
;
80 if (info
->desc_index
>= MXS_NAND_DMA_DESCRIPTOR_COUNT
) {
81 printf("MXS NAND: Too many DMA descriptors requested\n");
85 desc
= info
->desc
[info
->desc_index
];
91 static void mxs_nand_return_dma_descs(struct mxs_nand_info
*info
)
94 struct mxs_dma_desc
*desc
;
96 for (i
= 0; i
< info
->desc_index
; i
++) {
98 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
99 desc
->address
= (dma_addr_t
)desc
;
102 info
->desc_index
= 0;
105 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size
)
107 return page_data_size
/ MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
110 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength
)
112 return ecc_strength
* 13;
115 static uint32_t mxs_nand_aux_status_offset(void)
117 return (MXS_NAND_METADATA_SIZE
+ 0x3) & ~0x3;
120 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size
,
121 uint32_t page_oob_size
)
123 if (page_data_size
== 2048)
126 if (page_data_size
== 4096) {
127 if (page_oob_size
== 128)
130 if (page_oob_size
== 218)
137 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size
,
138 uint32_t ecc_strength
)
140 uint32_t chunk_data_size_in_bits
;
141 uint32_t chunk_ecc_size_in_bits
;
142 uint32_t chunk_total_size_in_bits
;
143 uint32_t block_mark_chunk_number
;
144 uint32_t block_mark_chunk_bit_offset
;
145 uint32_t block_mark_bit_offset
;
147 chunk_data_size_in_bits
= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
* 8;
148 chunk_ecc_size_in_bits
= mxs_nand_ecc_size_in_bits(ecc_strength
);
150 chunk_total_size_in_bits
=
151 chunk_data_size_in_bits
+ chunk_ecc_size_in_bits
;
153 /* Compute the bit offset of the block mark within the physical page. */
154 block_mark_bit_offset
= page_data_size
* 8;
156 /* Subtract the metadata bits. */
157 block_mark_bit_offset
-= MXS_NAND_METADATA_SIZE
* 8;
160 * Compute the chunk number (starting at zero) in which the block mark
163 block_mark_chunk_number
=
164 block_mark_bit_offset
/ chunk_total_size_in_bits
;
167 * Compute the bit offset of the block mark within its chunk, and
170 block_mark_chunk_bit_offset
= block_mark_bit_offset
-
171 (block_mark_chunk_number
* chunk_total_size_in_bits
);
173 if (block_mark_chunk_bit_offset
> chunk_data_size_in_bits
)
177 * Now that we know the chunk number in which the block mark appears,
178 * we can subtract all the ECC bits that appear before it.
180 block_mark_bit_offset
-=
181 block_mark_chunk_number
* chunk_ecc_size_in_bits
;
183 return block_mark_bit_offset
;
186 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info
*mtd
)
188 uint32_t ecc_strength
;
189 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
190 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) >> 3;
193 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info
*mtd
)
195 uint32_t ecc_strength
;
196 ecc_strength
= mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
);
197 return mxs_nand_get_mark_offset(mtd
->writesize
, ecc_strength
) & 0x7;
201 * Wait for BCH complete IRQ and clear the IRQ
203 static int mxs_nand_wait_for_bch_complete(void)
205 struct mx28_bch_regs
*bch_regs
= (struct mx28_bch_regs
*)MXS_BCH_BASE
;
206 int timeout
= MXS_NAND_BCH_TIMEOUT
;
209 ret
= mx28_wait_mask_set(&bch_regs
->hw_bch_ctrl_reg
,
210 BCH_CTRL_COMPLETE_IRQ
, timeout
);
212 writel(BCH_CTRL_COMPLETE_IRQ
, &bch_regs
->hw_bch_ctrl_clr
);
218 * This is the function that we install in the cmd_ctrl function pointer of the
219 * owning struct nand_chip. The only functions in the reference implementation
220 * that use these functions pointers are cmdfunc and select_chip.
222 * In this driver, we implement our own select_chip, so this function will only
223 * be called by the reference implementation's cmdfunc. For this reason, we can
224 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
227 static void mxs_nand_cmd_ctrl(struct mtd_info
*mtd
, int data
, unsigned int ctrl
)
229 struct nand_chip
*nand
= mtd
->priv
;
230 struct mxs_nand_info
*nand_info
= nand
->priv
;
231 struct mxs_dma_desc
*d
;
232 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
236 * If this condition is true, something is _VERY_ wrong in MTD
239 if (nand_info
->cmd_queue_len
== MXS_NAND_COMMAND_BUFFER_SIZE
) {
240 printf("MXS NAND: Command queue too long\n");
245 * Every operation begins with a command byte and a series of zero or
246 * more address bytes. These are distinguished by either the Address
247 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
248 * asserted. When MTD is ready to execute the command, it will
249 * deasert both latch enables.
251 * Rather than run a separate DMA operation for every single byte, we
252 * queue them up and run a single DMA operation for the entire series
253 * of command and data bytes.
255 if (ctrl
& (NAND_ALE
| NAND_CLE
)) {
256 if (data
!= NAND_CMD_NONE
)
257 nand_info
->cmd_buf
[nand_info
->cmd_queue_len
++] = data
;
262 * If control arrives here, MTD has deasserted both the ALE and CLE,
263 * which means it's ready to run an operation. Check if we have any
266 if (nand_info
->cmd_queue_len
== 0)
269 /* Compile the DMA descriptor -- a descriptor that sends command. */
270 d
= mxs_nand_get_dma_desc(nand_info
);
272 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
273 MXS_DMA_DESC_CHAIN
| MXS_DMA_DESC_DEC_SEM
|
274 MXS_DMA_DESC_WAIT4END
| (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
275 (nand_info
->cmd_queue_len
<< MXS_DMA_DESC_BYTES_OFFSET
);
277 d
->cmd
.address
= (dma_addr_t
)nand_info
->cmd_buf
;
279 d
->cmd
.pio_words
[0] =
280 GPMI_CTRL0_COMMAND_MODE_WRITE
|
281 GPMI_CTRL0_WORD_LENGTH
|
282 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
283 GPMI_CTRL0_ADDRESS_NAND_CLE
|
284 GPMI_CTRL0_ADDRESS_INCREMENT
|
285 nand_info
->cmd_queue_len
;
287 mxs_dma_desc_append(channel
, d
);
289 /* Execute the DMA chain. */
290 ret
= mxs_dma_go(channel
);
292 printf("MXS NAND: Error sending command\n");
294 mxs_nand_return_dma_descs(nand_info
);
296 /* Reset the command queue. */
297 nand_info
->cmd_queue_len
= 0;
301 * Test if the NAND flash is ready.
303 static int mxs_nand_device_ready(struct mtd_info
*mtd
)
305 struct nand_chip
*chip
= mtd
->priv
;
306 struct mxs_nand_info
*nand_info
= chip
->priv
;
307 struct mx28_gpmi_regs
*gpmi_regs
=
308 (struct mx28_gpmi_regs
*)MXS_GPMI_BASE
;
311 tmp
= readl(&gpmi_regs
->hw_gpmi_stat
);
312 tmp
>>= (GPMI_STAT_READY_BUSY_OFFSET
+ nand_info
->cur_chip
);
318 * Select the NAND chip.
320 static void mxs_nand_select_chip(struct mtd_info
*mtd
, int chip
)
322 struct nand_chip
*nand
= mtd
->priv
;
323 struct mxs_nand_info
*nand_info
= nand
->priv
;
325 nand_info
->cur_chip
= chip
;
329 * Handle block mark swapping.
331 * Note that, when this function is called, it doesn't know whether it's
332 * swapping the block mark, or swapping it *back* -- but it doesn't matter
333 * because the the operation is the same.
335 static void mxs_nand_swap_block_mark(struct mtd_info
*mtd
,
336 uint8_t *data_buf
, uint8_t *oob_buf
)
344 bit_offset
= mxs_nand_mark_bit_offset(mtd
);
345 buf_offset
= mxs_nand_mark_byte_offset(mtd
);
348 * Get the byte from the data area that overlays the block mark. Since
349 * the ECC engine applies its own view to the bits in the page, the
350 * physical block mark won't (in general) appear on a byte boundary in
353 src
= data_buf
[buf_offset
] >> bit_offset
;
354 src
|= data_buf
[buf_offset
+ 1] << (8 - bit_offset
);
360 data_buf
[buf_offset
] &= ~(0xff << bit_offset
);
361 data_buf
[buf_offset
+ 1] &= 0xff << bit_offset
;
363 data_buf
[buf_offset
] |= dst
<< bit_offset
;
364 data_buf
[buf_offset
+ 1] |= dst
>> (8 - bit_offset
);
368 * Read data from NAND.
370 static void mxs_nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int length
)
372 struct nand_chip
*nand
= mtd
->priv
;
373 struct mxs_nand_info
*nand_info
= nand
->priv
;
374 struct mxs_dma_desc
*d
;
375 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
378 if (length
> NAND_MAX_PAGESIZE
) {
379 printf("MXS NAND: DMA buffer too big\n");
384 printf("MXS NAND: DMA buffer is NULL\n");
388 /* Compile the DMA descriptor - a descriptor that reads data. */
389 d
= mxs_nand_get_dma_desc(nand_info
);
391 MXS_DMA_DESC_COMMAND_DMA_WRITE
| MXS_DMA_DESC_IRQ
|
392 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
393 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
394 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
396 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
398 d
->cmd
.pio_words
[0] =
399 GPMI_CTRL0_COMMAND_MODE_READ
|
400 GPMI_CTRL0_WORD_LENGTH
|
401 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
402 GPMI_CTRL0_ADDRESS_NAND_DATA
|
405 mxs_dma_desc_append(channel
, d
);
408 * A DMA descriptor that waits for the command to end and the chip to
411 * I think we actually should *not* be waiting for the chip to become
412 * ready because, after all, we don't care. I think the original code
413 * did that and no one has re-thought it yet.
415 d
= mxs_nand_get_dma_desc(nand_info
);
417 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
418 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_DEC_SEM
|
419 MXS_DMA_DESC_WAIT4END
| (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
423 d
->cmd
.pio_words
[0] =
424 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
425 GPMI_CTRL0_WORD_LENGTH
|
426 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
427 GPMI_CTRL0_ADDRESS_NAND_DATA
;
429 mxs_dma_desc_append(channel
, d
);
431 /* Execute the DMA chain. */
432 ret
= mxs_dma_go(channel
);
434 printf("MXS NAND: DMA read error\n");
438 memcpy(buf
, nand_info
->data_buf
, length
);
441 mxs_nand_return_dma_descs(nand_info
);
445 * Write data to NAND.
447 static void mxs_nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
450 struct nand_chip
*nand
= mtd
->priv
;
451 struct mxs_nand_info
*nand_info
= nand
->priv
;
452 struct mxs_dma_desc
*d
;
453 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
456 if (length
> NAND_MAX_PAGESIZE
) {
457 printf("MXS NAND: DMA buffer too big\n");
462 printf("MXS NAND: DMA buffer is NULL\n");
466 memcpy(nand_info
->data_buf
, buf
, length
);
468 /* Compile the DMA descriptor - a descriptor that writes data. */
469 d
= mxs_nand_get_dma_desc(nand_info
);
471 MXS_DMA_DESC_COMMAND_DMA_READ
| MXS_DMA_DESC_IRQ
|
472 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
473 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET
) |
474 (length
<< MXS_DMA_DESC_BYTES_OFFSET
);
476 d
->cmd
.address
= (dma_addr_t
)nand_info
->data_buf
;
478 d
->cmd
.pio_words
[0] =
479 GPMI_CTRL0_COMMAND_MODE_WRITE
|
480 GPMI_CTRL0_WORD_LENGTH
|
481 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
482 GPMI_CTRL0_ADDRESS_NAND_DATA
|
485 mxs_dma_desc_append(channel
, d
);
487 /* Execute the DMA chain. */
488 ret
= mxs_dma_go(channel
);
490 printf("MXS NAND: DMA write error\n");
492 mxs_nand_return_dma_descs(nand_info
);
496 * Read a single byte from NAND.
498 static uint8_t mxs_nand_read_byte(struct mtd_info
*mtd
)
501 mxs_nand_read_buf(mtd
, &buf
, 1);
506 * Read a page from NAND.
508 static int mxs_nand_ecc_read_page(struct mtd_info
*mtd
, struct nand_chip
*nand
,
509 uint8_t *buf
, int page
)
511 struct mxs_nand_info
*nand_info
= nand
->priv
;
512 struct mxs_dma_desc
*d
;
513 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
514 uint32_t corrected
= 0, failed
= 0;
518 /* Compile the DMA descriptor - wait for ready. */
519 d
= mxs_nand_get_dma_desc(nand_info
);
521 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
522 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
523 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
527 d
->cmd
.pio_words
[0] =
528 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
529 GPMI_CTRL0_WORD_LENGTH
|
530 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
531 GPMI_CTRL0_ADDRESS_NAND_DATA
;
533 mxs_dma_desc_append(channel
, d
);
535 /* Compile the DMA descriptor - enable the BCH block and read. */
536 d
= mxs_nand_get_dma_desc(nand_info
);
538 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
539 MXS_DMA_DESC_WAIT4END
| (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
543 d
->cmd
.pio_words
[0] =
544 GPMI_CTRL0_COMMAND_MODE_READ
|
545 GPMI_CTRL0_WORD_LENGTH
|
546 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
547 GPMI_CTRL0_ADDRESS_NAND_DATA
|
548 (mtd
->writesize
+ mtd
->oobsize
);
549 d
->cmd
.pio_words
[1] = 0;
550 d
->cmd
.pio_words
[2] =
551 GPMI_ECCCTRL_ENABLE_ECC
|
552 GPMI_ECCCTRL_ECC_CMD_DECODE
|
553 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
554 d
->cmd
.pio_words
[3] = mtd
->writesize
+ mtd
->oobsize
;
555 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
556 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
558 mxs_dma_desc_append(channel
, d
);
560 /* Compile the DMA descriptor - disable the BCH block. */
561 d
= mxs_nand_get_dma_desc(nand_info
);
563 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_CHAIN
|
564 MXS_DMA_DESC_NAND_WAIT_4_READY
| MXS_DMA_DESC_WAIT4END
|
565 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
569 d
->cmd
.pio_words
[0] =
570 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY
|
571 GPMI_CTRL0_WORD_LENGTH
|
572 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
573 GPMI_CTRL0_ADDRESS_NAND_DATA
|
574 (mtd
->writesize
+ mtd
->oobsize
);
575 d
->cmd
.pio_words
[1] = 0;
576 d
->cmd
.pio_words
[2] = 0;
578 mxs_dma_desc_append(channel
, d
);
580 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
581 d
= mxs_nand_get_dma_desc(nand_info
);
583 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
584 MXS_DMA_DESC_DEC_SEM
;
588 mxs_dma_desc_append(channel
, d
);
590 /* Execute the DMA chain. */
591 ret
= mxs_dma_go(channel
);
593 printf("MXS NAND: DMA read error\n");
597 ret
= mxs_nand_wait_for_bch_complete();
599 printf("MXS NAND: BCH read timeout\n");
603 /* Read DMA completed, now do the mark swapping. */
604 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
606 /* Loop over status bytes, accumulating ECC status. */
607 status
= nand_info
->oob_buf
+ mxs_nand_aux_status_offset();
608 for (i
= 0; i
< mxs_nand_ecc_chunk_cnt(mtd
->writesize
); i
++) {
609 if (status
[i
] == 0x00)
612 if (status
[i
] == 0xff)
615 if (status
[i
] == 0xfe) {
620 corrected
+= status
[i
];
623 /* Propagate ECC status to the owning MTD. */
624 mtd
->ecc_stats
.failed
+= failed
;
625 mtd
->ecc_stats
.corrected
+= corrected
;
628 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
629 * details about our policy for delivering the OOB.
631 * We fill the caller's buffer with set bits, and then copy the block
632 * mark to the caller's buffer. Note that, if block mark swapping was
633 * necessary, it has already been done, so we can rely on the first
634 * byte of the auxiliary buffer to contain the block mark.
636 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
638 nand
->oob_poi
[0] = nand_info
->oob_buf
[0];
640 memcpy(buf
, nand_info
->data_buf
, mtd
->writesize
);
643 mxs_nand_return_dma_descs(nand_info
);
649 * Write a page to NAND.
651 static void mxs_nand_ecc_write_page(struct mtd_info
*mtd
,
652 struct nand_chip
*nand
, const uint8_t *buf
)
654 struct mxs_nand_info
*nand_info
= nand
->priv
;
655 struct mxs_dma_desc
*d
;
656 uint32_t channel
= MXS_DMA_CHANNEL_AHB_APBH_GPMI0
+ nand_info
->cur_chip
;
659 memcpy(nand_info
->data_buf
, buf
, mtd
->writesize
);
660 memcpy(nand_info
->oob_buf
, nand
->oob_poi
, mtd
->oobsize
);
662 /* Handle block mark swapping. */
663 mxs_nand_swap_block_mark(mtd
, nand_info
->data_buf
, nand_info
->oob_buf
);
665 /* Compile the DMA descriptor - write data. */
666 d
= mxs_nand_get_dma_desc(nand_info
);
668 MXS_DMA_DESC_COMMAND_NO_DMAXFER
| MXS_DMA_DESC_IRQ
|
669 MXS_DMA_DESC_DEC_SEM
| MXS_DMA_DESC_WAIT4END
|
670 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET
);
674 d
->cmd
.pio_words
[0] =
675 GPMI_CTRL0_COMMAND_MODE_WRITE
|
676 GPMI_CTRL0_WORD_LENGTH
|
677 (nand_info
->cur_chip
<< GPMI_CTRL0_CS_OFFSET
) |
678 GPMI_CTRL0_ADDRESS_NAND_DATA
;
679 d
->cmd
.pio_words
[1] = 0;
680 d
->cmd
.pio_words
[2] =
681 GPMI_ECCCTRL_ENABLE_ECC
|
682 GPMI_ECCCTRL_ECC_CMD_ENCODE
|
683 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE
;
684 d
->cmd
.pio_words
[3] = (mtd
->writesize
+ mtd
->oobsize
);
685 d
->cmd
.pio_words
[4] = (dma_addr_t
)nand_info
->data_buf
;
686 d
->cmd
.pio_words
[5] = (dma_addr_t
)nand_info
->oob_buf
;
688 mxs_dma_desc_append(channel
, d
);
690 /* Execute the DMA chain. */
691 ret
= mxs_dma_go(channel
);
693 printf("MXS NAND: DMA write error\n");
697 ret
= mxs_nand_wait_for_bch_complete();
699 printf("MXS NAND: BCH write timeout\n");
704 mxs_nand_return_dma_descs(nand_info
);
708 * Read OOB from NAND.
710 * This function is a veneer that replaces the function originally installed by
711 * the NAND Flash MTD code.
713 static int mxs_nand_hook_read_oob(struct mtd_info
*mtd
, loff_t from
,
714 struct mtd_oob_ops
*ops
)
716 struct nand_chip
*chip
= mtd
->priv
;
717 struct mxs_nand_info
*nand_info
= chip
->priv
;
720 if (ops
->mode
== MTD_OOB_RAW
)
721 nand_info
->raw_oob_mode
= 1;
723 nand_info
->raw_oob_mode
= 0;
725 ret
= nand_info
->hooked_read_oob(mtd
, from
, ops
);
727 nand_info
->raw_oob_mode
= 0;
735 * This function is a veneer that replaces the function originally installed by
736 * the NAND Flash MTD code.
738 static int mxs_nand_hook_write_oob(struct mtd_info
*mtd
, loff_t to
,
739 struct mtd_oob_ops
*ops
)
741 struct nand_chip
*chip
= mtd
->priv
;
742 struct mxs_nand_info
*nand_info
= chip
->priv
;
745 if (ops
->mode
== MTD_OOB_RAW
)
746 nand_info
->raw_oob_mode
= 1;
748 nand_info
->raw_oob_mode
= 0;
750 ret
= nand_info
->hooked_write_oob(mtd
, to
, ops
);
752 nand_info
->raw_oob_mode
= 0;
758 * Mark a block bad in NAND.
760 * This function is a veneer that replaces the function originally installed by
761 * the NAND Flash MTD code.
763 static int mxs_nand_hook_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
765 struct nand_chip
*chip
= mtd
->priv
;
766 struct mxs_nand_info
*nand_info
= chip
->priv
;
769 nand_info
->marking_block_bad
= 1;
771 ret
= nand_info
->hooked_block_markbad(mtd
, ofs
);
773 nand_info
->marking_block_bad
= 0;
779 * There are several places in this driver where we have to handle the OOB and
780 * block marks. This is the function where things are the most complicated, so
781 * this is where we try to explain it all. All the other places refer back to
784 * These are the rules, in order of decreasing importance:
786 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
787 * write operations take measures to protect it.
789 * 2) In read operations, the first byte of the OOB we return must reflect the
790 * true state of the block mark, no matter where that block mark appears in
793 * 3) ECC-based read operations return an OOB full of set bits (since we never
794 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
797 * 4) "Raw" read operations return a direct view of the physical bytes in the
798 * page, using the conventional definition of which bytes are data and which
799 * are OOB. This gives the caller a way to see the actual, physical bytes
800 * in the page, without the distortions applied by our ECC engine.
802 * What we do for this specific read operation depends on whether we're doing
803 * "raw" read, or an ECC-based read.
805 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
806 * easy. When reading a page, for example, the NAND Flash MTD code calls our
807 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
808 * ECC-based or raw view of the page is implicit in which function it calls
809 * (there is a similar pair of ECC-based/raw functions for writing).
811 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
812 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
813 * caller wants an ECC-based or raw view of the page is not propagated down to
816 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
817 * ecc.read_oob and ecc.write_oob function pointers in the owning
818 * struct mtd_info with our own functions. These hook functions set the
819 * raw_oob_mode field so that, when control finally arrives here, we'll know
822 static int mxs_nand_ecc_read_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
825 struct mxs_nand_info
*nand_info
= nand
->priv
;
828 * First, fill in the OOB buffer. If we're doing a raw read, we need to
829 * get the bytes from the physical page. If we're not doing a raw read,
830 * we need to fill the buffer with set bits.
832 if (nand_info
->raw_oob_mode
) {
834 * If control arrives here, we're doing a "raw" read. Send the
835 * command to read the conventional OOB and read it.
837 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
838 nand
->read_buf(mtd
, nand
->oob_poi
, mtd
->oobsize
);
841 * If control arrives here, we're not doing a "raw" read. Fill
842 * the OOB buffer with set bits and correct the block mark.
844 memset(nand
->oob_poi
, 0xff, mtd
->oobsize
);
846 nand
->cmdfunc(mtd
, NAND_CMD_READ0
, mtd
->writesize
, page
);
847 mxs_nand_read_buf(mtd
, nand
->oob_poi
, 1);
855 * Write OOB data to NAND.
857 static int mxs_nand_ecc_write_oob(struct mtd_info
*mtd
, struct nand_chip
*nand
,
860 struct mxs_nand_info
*nand_info
= nand
->priv
;
861 uint8_t block_mark
= 0;
864 * There are fundamental incompatibilities between the i.MX GPMI NFC and
865 * the NAND Flash MTD model that make it essentially impossible to write
866 * the out-of-band bytes.
868 * We permit *ONE* exception. If the *intent* of writing the OOB is to
869 * mark a block bad, we can do that.
872 if (!nand_info
->marking_block_bad
) {
873 printf("NXS NAND: Writing OOB isn't supported\n");
877 /* Write the block mark. */
878 nand
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
879 nand
->write_buf(mtd
, &block_mark
, 1);
880 nand
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
882 /* Check if it worked. */
883 if (nand
->waitfunc(mtd
, nand
) & NAND_STATUS_FAIL
)
890 * Claims all blocks are good.
892 * In principle, this function is *only* called when the NAND Flash MTD system
893 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
894 * the driver for bad block information.
896 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
897 * this function is *only* called when we take it away.
899 * Thus, this function is only called when we want *all* blocks to look good,
900 * so it *always* return success.
902 static int mxs_nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
908 * Nominally, the purpose of this function is to look for or create the bad
909 * block table. In fact, since the we call this function at the very end of
910 * the initialization process started by nand_scan(), and we doesn't have a
911 * more formal mechanism, we "hook" this function to continue init process.
913 * At this point, the physical NAND Flash chips have been identified and
914 * counted, so we know the physical geometry. This enables us to make some
915 * important configuration decisions.
917 * The return value of this function propogates directly back to this driver's
918 * call to nand_scan(). Anything other than zero will cause this driver to
919 * tear everything down and declare failure.
921 static int mxs_nand_scan_bbt(struct mtd_info
*mtd
)
923 struct nand_chip
*nand
= mtd
->priv
;
924 struct mxs_nand_info
*nand_info
= nand
->priv
;
925 struct mx28_bch_regs
*bch_regs
= (struct mx28_bch_regs
*)MXS_BCH_BASE
;
928 /* Configure BCH and set NFC geometry */
929 mx28_reset_block(&bch_regs
->hw_bch_ctrl_reg
);
931 /* Configure layout 0 */
932 tmp
= (mxs_nand_ecc_chunk_cnt(mtd
->writesize
) - 1)
933 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET
;
934 tmp
|= MXS_NAND_METADATA_SIZE
<< BCH_FLASHLAYOUT0_META_SIZE_OFFSET
;
935 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
936 << BCH_FLASHLAYOUT0_ECC0_OFFSET
;
937 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
938 writel(tmp
, &bch_regs
->hw_bch_flash0layout0
);
940 tmp
= (mtd
->writesize
+ mtd
->oobsize
)
941 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET
;
942 tmp
|= (mxs_nand_get_ecc_strength(mtd
->writesize
, mtd
->oobsize
) >> 1)
943 << BCH_FLASHLAYOUT1_ECCN_OFFSET
;
944 tmp
|= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
;
945 writel(tmp
, &bch_regs
->hw_bch_flash0layout1
);
947 /* Set *all* chip selects to use layout 0 */
948 writel(0, &bch_regs
->hw_bch_layoutselect
);
950 /* Enable BCH complete interrupt */
951 writel(BCH_CTRL_COMPLETE_IRQ_EN
, &bch_regs
->hw_bch_ctrl_set
);
953 /* Hook some operations at the MTD level. */
954 if (mtd
->read_oob
!= mxs_nand_hook_read_oob
) {
955 nand_info
->hooked_read_oob
= mtd
->read_oob
;
956 mtd
->read_oob
= mxs_nand_hook_read_oob
;
959 if (mtd
->write_oob
!= mxs_nand_hook_write_oob
) {
960 nand_info
->hooked_write_oob
= mtd
->write_oob
;
961 mtd
->write_oob
= mxs_nand_hook_write_oob
;
964 if (mtd
->block_markbad
!= mxs_nand_hook_block_markbad
) {
965 nand_info
->hooked_block_markbad
= mtd
->block_markbad
;
966 mtd
->block_markbad
= mxs_nand_hook_block_markbad
;
969 /* We use the reference implementation for bad block management. */
970 return nand_default_bbt(mtd
);
974 * Allocate DMA buffers
976 int mxs_nand_alloc_buffers(struct mxs_nand_info
*nand_info
)
979 const int size
= NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
;
982 buf
= memalign(MXS_DMA_ALIGNMENT
, size
);
984 printf("MXS NAND: Error allocating DMA buffers\n");
988 memset(buf
, 0, size
);
990 nand_info
->data_buf
= buf
;
991 nand_info
->oob_buf
= buf
+ NAND_MAX_PAGESIZE
;
993 /* Command buffers */
994 nand_info
->cmd_buf
= memalign(MXS_DMA_ALIGNMENT
,
995 MXS_NAND_COMMAND_BUFFER_SIZE
);
996 if (!nand_info
->cmd_buf
) {
998 printf("MXS NAND: Error allocating command buffers\n");
1001 memset(nand_info
->cmd_buf
, 0, MXS_NAND_COMMAND_BUFFER_SIZE
);
1002 nand_info
->cmd_queue_len
= 0;
1008 * Initializes the NFC hardware.
1010 int mxs_nand_init(struct mxs_nand_info
*info
)
1012 struct mx28_gpmi_regs
*gpmi_regs
=
1013 (struct mx28_gpmi_regs
*)MXS_GPMI_BASE
;
1016 info
->desc
= malloc(sizeof(struct mxs_dma_desc
*) *
1017 MXS_NAND_DMA_DESCRIPTOR_COUNT
);
1021 /* Allocate the DMA descriptors. */
1022 for (i
= 0; i
< MXS_NAND_DMA_DESCRIPTOR_COUNT
; i
++) {
1023 info
->desc
[i
] = mxs_dma_desc_alloc();
1028 /* Init the DMA controller. */
1031 /* Reset the GPMI block. */
1032 mx28_reset_block(&gpmi_regs
->hw_gpmi_ctrl0_reg
);
1035 * Choose NAND mode, set IRQ polarity, disable write protection and
1038 clrsetbits_le32(&gpmi_regs
->hw_gpmi_ctrl1
,
1039 GPMI_CTRL1_GPMI_MODE
,
1040 GPMI_CTRL1_ATA_IRQRDY_POLARITY
| GPMI_CTRL1_DEV_RESET
|
1041 GPMI_CTRL1_BCH_MODE
);
1048 for (--i
; i
>= 0; i
--)
1049 mxs_dma_desc_free(info
->desc
[i
]);
1050 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1055 * This function is called during the driver binding process.
1057 * @param pdev the device structure used to store device specific
1058 * information that is used by the suspend, resume and
1061 * @return The function always returns 0.
1063 int board_nand_init(struct nand_chip
*nand
)
1065 struct mxs_nand_info
*nand_info
;
1068 nand_info
= malloc(sizeof(struct mxs_nand_info
));
1070 printf("MXS NAND: Failed to allocate private data\n");
1073 memset(nand_info
, 0, sizeof(struct mxs_nand_info
));
1075 err
= mxs_nand_alloc_buffers(nand_info
);
1079 err
= mxs_nand_init(nand_info
);
1083 memset(&fake_ecc_layout
, 0, sizeof(fake_ecc_layout
));
1085 nand
->priv
= nand_info
;
1086 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1088 nand
->cmd_ctrl
= mxs_nand_cmd_ctrl
;
1090 nand
->dev_ready
= mxs_nand_device_ready
;
1091 nand
->select_chip
= mxs_nand_select_chip
;
1092 nand
->block_bad
= mxs_nand_block_bad
;
1093 nand
->scan_bbt
= mxs_nand_scan_bbt
;
1095 nand
->read_byte
= mxs_nand_read_byte
;
1097 nand
->read_buf
= mxs_nand_read_buf
;
1098 nand
->write_buf
= mxs_nand_write_buf
;
1100 nand
->ecc
.read_page
= mxs_nand_ecc_read_page
;
1101 nand
->ecc
.write_page
= mxs_nand_ecc_write_page
;
1102 nand
->ecc
.read_oob
= mxs_nand_ecc_read_oob
;
1103 nand
->ecc
.write_oob
= mxs_nand_ecc_write_oob
;
1105 nand
->ecc
.layout
= &fake_ecc_layout
;
1106 nand
->ecc
.mode
= NAND_ECC_HW
;
1107 nand
->ecc
.bytes
= 9;
1108 nand
->ecc
.size
= 512;
1113 free(nand_info
->data_buf
);
1114 free(nand_info
->cmd_buf
);