drivers/mtd/nand/nand_ids.c

   1 /*
   2  *  drivers/mtd/nandids.c
   3  *
   4  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
   5  *
   6  * $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  */
  13
  14 #include <common.h>
  15
  16 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
  17
  18 #include <linux/mtd/nand.h>
  19 /*
  20 *       Chip ID list
  21 *
  22 *       Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
  23 *       options
  24 *
  25 *       Pagesize; 0, 256, 512
  26 *       0       get this information from the extended chip ID
  27 +       256     256 Byte page size
  28 *       512     512 Byte page size
  29 */
  30 struct nand_flash_dev nand_flash_ids[] = {
  31
  32 #ifdef CONFIG_MTD_NAND_MUSEUM_IDS
  33         {"NAND 1MiB 5V 8-bit",          0x6e, 256, 1, 0x1000, 0},
  34         {"NAND 2MiB 5V 8-bit",          0x64, 256, 2, 0x1000, 0},
  35         {"NAND 4MiB 5V 8-bit",          0x6b, 512, 4, 0x2000, 0},
  36         {"NAND 1MiB 3,3V 8-bit",        0xe8, 256, 1, 0x1000, 0},
  37         {"NAND 1MiB 3,3V 8-bit",        0xec, 256, 1, 0x1000, 0},
  38         {"NAND 2MiB 3,3V 8-bit",        0xea, 256, 2, 0x1000, 0},
  39         {"NAND 4MiB 3,3V 8-bit",        0xd5, 512, 4, 0x2000, 0},
  40         {"NAND 4MiB 3,3V 8-bit",        0xe3, 512, 4, 0x2000, 0},
  41         {"NAND 4MiB 3,3V 8-bit",        0xe5, 512, 4, 0x2000, 0},
  42         {"NAND 8MiB 3,3V 8-bit",        0xd6, 512, 8, 0x2000, 0},
  43
  44         {"NAND 8MiB 1,8V 8-bit",        0x39, 512, 8, 0x2000, 0},
  45         {"NAND 8MiB 3,3V 8-bit",        0xe6, 512, 8, 0x2000, 0},
  46         {"NAND 8MiB 1,8V 16-bit",       0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
  47         {"NAND 8MiB 3,3V 16-bit",       0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
  48 #endif
  49
  50         {"NAND 16MiB 1,8V 8-bit",       0x33, 512, 16, 0x4000, 0},
  51         {"NAND 16MiB 3,3V 8-bit",       0x73, 512, 16, 0x4000, 0},
  52         {"NAND 16MiB 1,8V 16-bit",      0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
  53         {"NAND 16MiB 3,3V 16-bit",      0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
  54
  55         {"NAND 32MiB 1,8V 8-bit",       0x35, 512, 32, 0x4000, 0},
  56         {"NAND 32MiB 3,3V 8-bit",       0x75, 512, 32, 0x4000, 0},
  57         {"NAND 32MiB 1,8V 16-bit",      0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
  58         {"NAND 32MiB 3,3V 16-bit",      0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
  59
  60         {"NAND 64MiB 1,8V 8-bit",       0x36, 512, 64, 0x4000, 0},
  61         {"NAND 64MiB 3,3V 8-bit",       0x76, 512, 64, 0x4000, 0},
  62         {"NAND 64MiB 1,8V 16-bit",      0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
  63         {"NAND 64MiB 3,3V 16-bit",      0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
  64
  65         {"NAND 128MiB 1,8V 8-bit",      0x78, 512, 128, 0x4000, 0},
  66         {"NAND 128MiB 1,8V 8-bit",      0x39, 512, 128, 0x4000, 0},
  67         {"NAND 128MiB 3,3V 8-bit",      0x79, 512, 128, 0x4000, 0},
  68         {"NAND 128MiB 1,8V 16-bit",     0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  69         {"NAND 128MiB 1,8V 16-bit",     0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  70         {"NAND 128MiB 3,3V 16-bit",     0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  71         {"NAND 128MiB 3,3V 16-bit",     0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
  72
  73         {"NAND 256MiB 3,3V 8-bit",      0x71, 512, 256, 0x4000, 0},
  74
  75         /*
  76          * These are the new chips with large page size. The pagesize and the
  77          * erasesize is determined from the extended id bytes
  78          */
  79 #define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
  80 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
  81
  82         /*512 Megabit */
  83         {"NAND 64MiB 1,8V 8-bit",       0xA2, 0,  64, 0, LP_OPTIONS},
  84         {"NAND 64MiB 3,3V 8-bit",       0xF2, 0,  64, 0, LP_OPTIONS},
  85         {"NAND 64MiB 1,8V 16-bit",      0xB2, 0,  64, 0, LP_OPTIONS16},
  86         {"NAND 64MiB 3,3V 16-bit",      0xC2, 0,  64, 0, LP_OPTIONS16},
  87
  88         /* 1 Gigabit */
  89         {"NAND 128MiB 1,8V 8-bit",      0xA1, 0, 128, 0, LP_OPTIONS},
  90         {"NAND 128MiB 3,3V 8-bit",      0xF1, 0, 128, 0, LP_OPTIONS},
  91         {"NAND 128MiB 1,8V 16-bit",     0xB1, 0, 128, 0, LP_OPTIONS16},
  92         {"NAND 128MiB 3,3V 16-bit",     0xC1, 0, 128, 0, LP_OPTIONS16},
  93
  94         /* 2 Gigabit */
  95         {"NAND 256MiB 1,8V 8-bit",      0xAA, 0, 256, 0, LP_OPTIONS},
  96         {"NAND 256MiB 3,3V 8-bit",      0xDA, 0, 256, 0, LP_OPTIONS},
  97         {"NAND 256MiB 1,8V 16-bit",     0xBA, 0, 256, 0, LP_OPTIONS16},
  98         {"NAND 256MiB 3,3V 16-bit",     0xCA, 0, 256, 0, LP_OPTIONS16},
  99
 100         /* 4 Gigabit */
 101         {"NAND 512MiB 1,8V 8-bit",      0xAC, 0, 512, 0, LP_OPTIONS},
 102         {"NAND 512MiB 3,3V 8-bit",      0xDC, 0, 512, 0, LP_OPTIONS},
 103         {"NAND 512MiB 1,8V 16-bit",     0xBC, 0, 512, 0, LP_OPTIONS16},
 104         {"NAND 512MiB 3,3V 16-bit",     0xCC, 0, 512, 0, LP_OPTIONS16},
 105
 106         /* 8 Gigabit */
 107         {"NAND 1GiB 1,8V 8-bit",        0xA3, 0, 1024, 0, LP_OPTIONS},
 108         {"NAND 1GiB 3,3V 8-bit",        0xD3, 0, 1024, 0, LP_OPTIONS},
 109         {"NAND 1GiB 1,8V 16-bit",       0xB3, 0, 1024, 0, LP_OPTIONS16},
 110         {"NAND 1GiB 3,3V 16-bit",       0xC3, 0, 1024, 0, LP_OPTIONS16},
 111
 112         /* 16 Gigabit */
 113         {"NAND 2GiB 1,8V 8-bit",        0xA5, 0, 2048, 0, LP_OPTIONS},
 114         {"NAND 2GiB 3,3V 8-bit",        0xD5, 0, 2048, 0, LP_OPTIONS},
 115         {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, LP_OPTIONS16},
 116         {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, LP_OPTIONS16},
 117
 118         /*
 119          * Renesas AND 1 Gigabit. Those chips do not support extended id and
 120          * have a strange page/block layout !  The chosen minimum erasesize is
 121          * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
 122          * planes 1 block = 2 pages, but due to plane arrangement the blocks
 123          * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
 124          * increase the eraseblock size so we chose a combined one which can be
 125          * erased in one go There are more speed improvements for reads and
 126          * writes possible, but not implemented now
 127          */
 128         {"AND 128MiB 3,3V 8-bit",       0x01, 2048, 128, 0x4000,
 129          NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
 130          BBT_AUTO_REFRESH
 131         },
 132
 133         {NULL,}
 134 };
 135
 136 /*
 137 *       Manufacturer ID list
 138 */
 139 struct nand_manufacturers nand_manuf_ids[] = {
 140         {NAND_MFR_TOSHIBA, "Toshiba"},
 141         {NAND_MFR_SAMSUNG, "Samsung"},
 142         {NAND_MFR_FUJITSU, "Fujitsu"},
 143         {NAND_MFR_NATIONAL, "National"},
 144         {NAND_MFR_RENESAS, "Renesas"},
 145         {NAND_MFR_STMICRO, "ST Micro"},
 146         {NAND_MFR_HYNIX, "Hynix"},
 147         {NAND_MFR_MICRON, "Micron"},
 148         {0x0, "Unknown"}
 149 };
 150 #endif