drivers/mtd/nand/nand_spl_simple.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24 #include <linux/mtd/nand_ecc.h>
  25
  26 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  27 static nand_info_t mtd;
  28 static struct nand_chip nand_chip;
  29
  30 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  31 /*
  32  * NAND command for small page NAND devices (512)
  33  */
  34 static int nand_command(int block, int page, uint32_t offs,
  35         u8 cmd)
  36 {
  37         struct nand_chip *this = mtd.priv;
  38         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  39
  40         while (!this->dev_ready(&mtd))
  41                 ;
  42
  43         /* Begin command latch cycle */
  44         this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  45         /* Set ALE and clear CLE to start address cycle */
  46         /* Column address */
  47         this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  48         this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  49         this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
  50                        NAND_CTRL_ALE); /* A[24:17] */
  51 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  52         /* One more address cycle for devices > 32MiB */
  53         this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
  54                        NAND_CTRL_ALE); /* A[28:25] */
  55 #endif
  56         /* Latch in address */
  57         this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  58
  59         /*
  60          * Wait a while for the data to be ready
  61          */
  62         while (!this->dev_ready(&mtd))
  63                 ;
  64
  65         return 0;
  66 }
  67 #else
  68 /*
  69  * NAND command for large page NAND devices (2k)
  70  */
  71 static int nand_command(int block, int page, uint32_t offs,
  72         u8 cmd)
  73 {
  74         struct nand_chip *this = mtd.priv;
  75         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  76         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  77                         unsigned int ctrl) = this->cmd_ctrl;
  78
  79         while (!this->dev_ready(&mtd))
  80                 ;
  81
  82         /* Emulate NAND_CMD_READOOB */
  83         if (cmd == NAND_CMD_READOOB) {
  84                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  85                 cmd = NAND_CMD_READ0;
  86         }
  87
  88         /* Shift the offset from byte addressing to word addressing. */
  89         if (this->options & NAND_BUSWIDTH_16)
  90                 offs >>= 1;
  91
  92         /* Begin command latch cycle */
  93         hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  94         /* Set ALE and clear CLE to start address cycle */
  95         /* Column address */
  96         hwctrl(&mtd, offs & 0xff,
  97                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  98         hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  99         /* Row address */
 100         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
 101         hwctrl(&mtd, ((page_addr >> 8) & 0xff),
 102                        NAND_CTRL_ALE); /* A[27:20] */
 103 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 104         /* One more address cycle for devices > 128MiB */
 105         hwctrl(&mtd, (page_addr >> 16) & 0x0f,
 106                        NAND_CTRL_ALE); /* A[31:28] */
 107 #endif
 108         /* Latch in address */
 109         hwctrl(&mtd, NAND_CMD_READSTART,
 110                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 111         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 112
 113         /*
 114          * Wait a while for the data to be ready
 115          */
 116         while (!this->dev_ready(&mtd))
 117                 ;
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 static int nand_is_bad_block(int block)
 124 {
 125         struct nand_chip *this = mtd.priv;
 126
 127         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 128                 NAND_CMD_READOOB);
 129
 130         /*
 131          * Read one byte (or two if it's a 16 bit chip).
 132          */
 133         if (this->options & NAND_BUSWIDTH_16) {
 134                 if (readw(this->IO_ADDR_R) != 0xffff)
 135                         return 1;
 136         } else {
 137                 if (readb(this->IO_ADDR_R) != 0xff)
 138                         return 1;
 139         }
 140
 141         return 0;
 142 }
 143
 144 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
 145 static int nand_read_page(int block, int page, uchar *dst)
 146 {
 147         struct nand_chip *this = mtd.priv;
 148         u_char *ecc_calc;
 149         u_char *ecc_code;
 150         u_char *oob_data;
 151         int i;
 152         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 153         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 154         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 155         uint8_t *p = dst;
 156
 157         /*
 158          * No malloc available for now, just use some temporary locations
 159          * in SDRAM
 160          */
 161         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 162         ecc_code = ecc_calc + 0x100;
 163         oob_data = ecc_calc + 0x200;
 164
 165         nand_command(block, page, 0, NAND_CMD_READOOB);
 166         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 167         nand_command(block, page, 0, NAND_CMD_READ0);
 168
 169         /* Pick the ECC bytes out of the oob data */
 170         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 171                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 172
 173
 174         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 175                 this->ecc.hwctl(&mtd, NAND_ECC_READ);
 176                 this->read_buf(&mtd, p, eccsize);
 177                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
 178                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
 179         }
 180
 181         return 0;
 182 }
 183 #else
 184 static int nand_read_page(int block, int page, void *dst)
 185 {
 186         struct nand_chip *this = mtd.priv;
 187         u_char *ecc_calc;
 188         u_char *ecc_code;
 189         u_char *oob_data;
 190         int i;
 191         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 192         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 193         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 194         uint8_t *p = dst;
 195
 196         nand_command(block, page, 0, NAND_CMD_READ0);
 197
 198         /* No malloc available for now, just use some temporary locations
 199          * in SDRAM
 200          */
 201         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 202         ecc_code = ecc_calc + 0x100;
 203         oob_data = ecc_calc + 0x200;
 204
 205         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 206                 if (this->ecc.mode != NAND_ECC_SOFT)
 207                         this->ecc.hwctl(&mtd, NAND_ECC_READ);
 208                 this->read_buf(&mtd, p, eccsize);
 209                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
 210         }
 211         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 212
 213         /* Pick the ECC bytes out of the oob data */
 214         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 215                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 216
 217         eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 218         p = dst;
 219
 220         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 221                 /* No chance to do something with the possible error message
 222                  * from correct_data(). We just hope that all possible errors
 223                  * are corrected by this routine.
 224                  */
 225                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
 226         }
 227
 228         return 0;
 229 }
 230 #endif
 231
 232 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 233 {
 234         unsigned int block, lastblock;
 235         unsigned int page;
 236
 237         /*
 238          * offs has to be aligned to a page address!
 239          */
 240         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 241         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 242         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 243
 244         while (block <= lastblock) {
 245                 if (!nand_is_bad_block(block)) {
 246                         /*
 247                          * Skip bad blocks
 248                          */
 249                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 250                                 nand_read_page(block, page, dst);
 251                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 252                                 page++;
 253                         }
 254
 255                         page = 0;
 256                 } else {
 257                         lastblock++;
 258                 }
 259
 260                 block++;
 261         }
 262
 263         return 0;
 264 }
 265
 266 /* nand_init() - initialize data to make nand usable by SPL */
 267 void nand_init(void)
 268 {
 269         /*
 270          * Init board specific nand support
 271          */
 272         mtd.priv = &nand_chip;
 273         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 274                 (void  __iomem *)CONFIG_SYS_NAND_BASE;
 275         board_nand_init(&nand_chip);
 276
 277 #ifdef CONFIG_SPL_NAND_SOFTECC
 278         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
 279                 nand_chip.ecc.calculate = nand_calculate_ecc;
 280                 nand_chip.ecc.correct = nand_correct_data;
 281         }
 282 #endif
 283
 284         if (nand_chip.select_chip)
 285                 nand_chip.select_chip(&mtd, 0);
 286 }
 287
 288 /* Unselect after operation */
 289 void nand_deselect(void)
 290 {
 291         if (nand_chip.select_chip)
 292                 nand_chip.select_chip(&mtd, -1);
 293 }