drivers/mtd/nand/nand_spl_simple.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24
  25 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  26 static nand_info_t mtd;
  27 static struct nand_chip nand_chip;
  28
  29 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  30 /*
  31  * NAND command for small page NAND devices (512)
  32  */
  33 static int nand_command(int block, int page, uint32_t offs,
  34         u8 cmd)
  35 {
  36         struct nand_chip *this = mtd.priv;
  37         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  38
  39         while (!this->dev_ready(&mtd))
  40                 ;
  41
  42         /* Begin command latch cycle */
  43         this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  44         /* Set ALE and clear CLE to start address cycle */
  45         /* Column address */
  46         this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  47         this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  48         this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
  49                        NAND_CTRL_ALE); /* A[24:17] */
  50 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  51         /* One more address cycle for devices > 32MiB */
  52         this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
  53                        NAND_CTRL_ALE); /* A[28:25] */
  54 #endif
  55         /* Latch in address */
  56         this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  57
  58         /*
  59          * Wait a while for the data to be ready
  60          */
  61         while (!this->dev_ready(&mtd))
  62                 ;
  63
  64         return 0;
  65 }
  66 #else
  67 /*
  68  * NAND command for large page NAND devices (2k)
  69  */
  70 static int nand_command(int block, int page, uint32_t offs,
  71         u8 cmd)
  72 {
  73         struct nand_chip *this = mtd.priv;
  74         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  75         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  76                         unsigned int ctrl) = this->cmd_ctrl;
  77
  78         while (!this->dev_ready(&mtd))
  79                 ;
  80
  81         /* Emulate NAND_CMD_READOOB */
  82         if (cmd == NAND_CMD_READOOB) {
  83                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  84                 cmd = NAND_CMD_READ0;
  85         }
  86
  87         /* Shift the offset from byte addressing to word addressing. */
  88         if (this->options & NAND_BUSWIDTH_16)
  89                 offs >>= 1;
  90
  91         /* Begin command latch cycle */
  92         hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  93         /* Set ALE and clear CLE to start address cycle */
  94         /* Column address */
  95         hwctrl(&mtd, offs & 0xff,
  96                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  97         hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  98         /* Row address */
  99         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
 100         hwctrl(&mtd, ((page_addr >> 8) & 0xff),
 101                        NAND_CTRL_ALE); /* A[27:20] */
 102 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 103         /* One more address cycle for devices > 128MiB */
 104         hwctrl(&mtd, (page_addr >> 16) & 0x0f,
 105                        NAND_CTRL_ALE); /* A[31:28] */
 106 #endif
 107         /* Latch in address */
 108         hwctrl(&mtd, NAND_CMD_READSTART,
 109                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 110         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 111
 112         /*
 113          * Wait a while for the data to be ready
 114          */
 115         while (!this->dev_ready(&mtd))
 116                 ;
 117
 118         return 0;
 119 }
 120 #endif
 121
 122 static int nand_is_bad_block(int block)
 123 {
 124         struct nand_chip *this = mtd.priv;
 125
 126         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 127                 NAND_CMD_READOOB);
 128
 129         /*
 130          * Read one byte (or two if it's a 16 bit chip).
 131          */
 132         if (this->options & NAND_BUSWIDTH_16) {
 133                 if (readw(this->IO_ADDR_R) != 0xffff)
 134                         return 1;
 135         } else {
 136                 if (readb(this->IO_ADDR_R) != 0xff)
 137                         return 1;
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int nand_read_page(int block, int page, void *dst)
 144 {
 145         struct nand_chip *this = mtd.priv;
 146         u_char *ecc_calc;
 147         u_char *ecc_code;
 148         u_char *oob_data;
 149         int i;
 150         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 151         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 152         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 153         uint8_t *p = dst;
 154         int stat;
 155
 156         nand_command(block, page, 0, NAND_CMD_READ0);
 157
 158         /* No malloc available for now, just use some temporary locations
 159          * in SDRAM
 160          */
 161         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 162         ecc_code = ecc_calc + 0x100;
 163         oob_data = ecc_calc + 0x200;
 164
 165         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 166                 this->ecc.hwctl(&mtd, NAND_ECC_READ);
 167                 this->read_buf(&mtd, p, eccsize);
 168                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
 169         }
 170         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 171
 172         /* Pick the ECC bytes out of the oob data */
 173         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 174                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 175
 176         eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 177         p = dst;
 178
 179         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 180                 /* No chance to do something with the possible error message
 181                  * from correct_data(). We just hope that all possible errors
 182                  * are corrected by this routine.
 183                  */
 184                 stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
 185         }
 186
 187         return 0;
 188 }
 189
 190 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 191 {
 192         unsigned int block, lastblock;
 193         unsigned int page;
 194
 195         /*
 196          * offs has to be aligned to a page address!
 197          */
 198         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 199         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 200         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 201
 202         while (block <= lastblock) {
 203                 if (!nand_is_bad_block(block)) {
 204                         /*
 205                          * Skip bad blocks
 206                          */
 207                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 208                                 nand_read_page(block, page, dst);
 209                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 210                                 page++;
 211                         }
 212
 213                         page = 0;
 214                 } else {
 215                         lastblock++;
 216                 }
 217
 218                 block++;
 219         }
 220
 221         return 0;
 222 }
 223
 224 /* nand_init() - initialize data to make nand usable by SPL */
 225 void nand_init(void)
 226 {
 227         /*
 228          * Init board specific nand support
 229          */
 230         mtd.priv = &nand_chip;
 231         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 232                 (void  __iomem *)CONFIG_SYS_NAND_BASE;
 233         nand_chip.options = 0;
 234         board_nand_init(&nand_chip);
 235
 236         if (nand_chip.select_chip)
 237                 nand_chip.select_chip(&mtd, 0);
 238 }
 239
 240 /* Unselect after operation */
 241 void nand_deselect(void)
 242 {
 243         if (nand_chip.select_chip)
 244                 nand_chip.select_chip(&mtd, -1);
 245 }