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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/nand/ndfc.c
3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into IBM/AMCC PPC4xx cores
6 * (C) Copyright 2006-2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <linux/mtd/ndfc.h>
35 #include <linux/mtd/nand_ecc.h>
36 #include <asm/processor.h>
38 #include <asm/ppc4xx.h>
40 #ifndef CONFIG_SYS_NAND_BCR
41 #define CONFIG_SYS_NAND_BCR 0x80002222
43 #ifndef CONFIG_SYS_NDFC_EBC0_CFG
44 #define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
48 * We need to store the info, which chip-select (CS) is used for the
49 * chip number. For example on Sequoia NAND chip #0 uses
52 static int ndfc_cs
[NDFC_MAX_BANKS
];
54 static void ndfc_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
56 struct nand_chip
*this = mtd
->priv
;
57 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
59 if (cmd
== NAND_CMD_NONE
)
63 out_8((u8
*)(base
+ NDFC_CMD
), cmd
& 0xFF);
65 out_8((u8
*)(base
+ NDFC_ALE
), cmd
& 0xFF);
68 static int ndfc_dev_ready(struct mtd_info
*mtdinfo
)
70 struct nand_chip
*this = mtdinfo
->priv
;
71 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
73 return (in_be32((u32
*)(base
+ NDFC_STAT
)) & NDFC_STAT_IS_READY
);
76 static void ndfc_enable_hwecc(struct mtd_info
*mtdinfo
, int mode
)
78 struct nand_chip
*this = mtdinfo
->priv
;
79 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
82 ccr
= in_be32((u32
*)(base
+ NDFC_CCR
));
83 ccr
|= NDFC_CCR_RESET_ECC
;
84 out_be32((u32
*)(base
+ NDFC_CCR
), ccr
);
87 static int ndfc_calculate_ecc(struct mtd_info
*mtdinfo
,
88 const u_char
*dat
, u_char
*ecc_code
)
90 struct nand_chip
*this = mtdinfo
->priv
;
91 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
95 ecc
= in_be32((u32
*)(base
+ NDFC_ECC
));
97 /* The NDFC uses Smart Media (SMC) bytes order
107 * Speedups for buffer read/write/verify
109 * NDFC allows 32bit read/write of data. So we can speed up the buffer
110 * functions. No further checking, as nand_base will always read/write
113 static void ndfc_read_buf(struct mtd_info
*mtdinfo
, uint8_t *buf
, int len
)
115 struct nand_chip
*this = mtdinfo
->priv
;
116 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
117 uint32_t *p
= (uint32_t *) buf
;
119 for (;len
> 0; len
-= 4)
120 *p
++ = in_be32((u32
*)(base
+ NDFC_DATA
));
123 #ifndef CONFIG_NAND_SPL
125 * Don't use these speedup functions in NAND boot image, since the image
126 * has to fit into 4kByte.
128 static void ndfc_write_buf(struct mtd_info
*mtdinfo
, const uint8_t *buf
, int len
)
130 struct nand_chip
*this = mtdinfo
->priv
;
131 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
132 uint32_t *p
= (uint32_t *) buf
;
134 for (; len
> 0; len
-= 4)
135 out_be32((u32
*)(base
+ NDFC_DATA
), *p
++);
138 static int ndfc_verify_buf(struct mtd_info
*mtdinfo
, const uint8_t *buf
, int len
)
140 struct nand_chip
*this = mtdinfo
->priv
;
141 ulong base
= (ulong
) this->IO_ADDR_W
& 0xffffff00;
142 uint32_t *p
= (uint32_t *) buf
;
144 for (; len
> 0; len
-= 4)
145 if (*p
++ != in_be32((u32
*)(base
+ NDFC_DATA
)))
152 * Read a byte from the NDFC.
154 static uint8_t ndfc_read_byte(struct mtd_info
*mtd
)
157 struct nand_chip
*chip
= mtd
->priv
;
159 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
160 return (uint8_t) readw(chip
->IO_ADDR_R
);
162 return readb(chip
->IO_ADDR_R
);
167 #endif /* #ifndef CONFIG_NAND_SPL */
169 void board_nand_select_device(struct nand_chip
*nand
, int chip
)
172 * Don't use "chip" to address the NAND device,
173 * generate the cs from the address where it is encoded.
175 ulong base
= (ulong
)nand
->IO_ADDR_W
& 0xffffff00;
176 int cs
= ndfc_cs
[chip
];
178 /* Set NandFlash Core Configuration Register */
180 out_be32((u32
*)(base
+ NDFC_CCR
), 0x00000000 | (cs
<< 24));
181 out_be32((u32
*)(base
+ NDFC_BCFG0
+ (cs
<< 2)), CONFIG_SYS_NAND_BCR
);
184 static void ndfc_select_chip(struct mtd_info
*mtd
, int chip
)
187 * Nothing to do here!
191 int board_nand_init(struct nand_chip
*nand
)
193 int cs
= (ulong
)nand
->IO_ADDR_W
& 0x00000003;
194 ulong base
= (ulong
)nand
->IO_ADDR_W
& 0xffffff00;
198 * Save chip-select for this chip #
203 * Select required NAND chip in NDFC
205 board_nand_select_device(nand
, chip
);
207 nand
->IO_ADDR_R
= (void __iomem
*)(base
+ NDFC_DATA
);
208 nand
->IO_ADDR_W
= (void __iomem
*)(base
+ NDFC_DATA
);
209 nand
->cmd_ctrl
= ndfc_hwcontrol
;
210 nand
->chip_delay
= 50;
211 nand
->read_buf
= ndfc_read_buf
;
212 nand
->dev_ready
= ndfc_dev_ready
;
213 nand
->ecc
.correct
= nand_correct_data
;
214 nand
->ecc
.hwctl
= ndfc_enable_hwecc
;
215 nand
->ecc
.calculate
= ndfc_calculate_ecc
;
216 nand
->ecc
.mode
= NAND_ECC_HW
;
217 nand
->ecc
.size
= 256;
219 nand
->ecc
.strength
= 1;
220 nand
->select_chip
= ndfc_select_chip
;
222 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
223 nand
->options
|= NAND_BUSWIDTH_16
;
226 #ifndef CONFIG_NAND_SPL
227 nand
->write_buf
= ndfc_write_buf
;
228 nand
->verify_buf
= ndfc_verify_buf
;
229 nand
->read_byte
= ndfc_read_byte
;
234 * Setup EBC (CS0 only right now)
236 mtebc(EBC0_CFG
, CONFIG_SYS_NDFC_EBC0_CFG
);
238 mtebc(PB0CR
, CONFIG_SYS_EBC_PB0CR
);
239 mtebc(PB0AP
, CONFIG_SYS_EBC_PB0AP
);