drivers/mtd/nand/ndfc.c

   1 /*
   2  * Overview:
   3  *   Platform independend driver for NDFC (NanD Flash Controller)
   4  *   integrated into IBM/AMCC PPC4xx cores
   5  *
   6  * (C) Copyright 2006-2009
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * Based on original work by
  10  *      Thomas Gleixner
  11  *      Copyright 2006 IBM
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #include <common.h>
  33 #include <nand.h>
  34 #include <linux/mtd/ndfc.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <ppc4xx.h>
  39
  40 /*
  41  * We need to store the info, which chip-select (CS) is used for the
  42  * chip number. For example on Sequoia NAND chip #0 uses
  43  * CS #3.
  44  */
  45 static int ndfc_cs[NDFC_MAX_BANKS];
  46
  47 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  48 {
  49         struct nand_chip *this = mtd->priv;
  50         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  51
  52         if (cmd == NAND_CMD_NONE)
  53                 return;
  54
  55         if (ctrl & NAND_CLE)
  56                 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
  57         else
  58                 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
  59 }
  60
  61 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
  62 {
  63         struct nand_chip *this = mtdinfo->priv;
  64         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  65
  66         return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
  67 }
  68
  69 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
  70 {
  71         struct nand_chip *this = mtdinfo->priv;
  72         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  73         u32 ccr;
  74
  75         ccr = in_be32((u32 *)(base + NDFC_CCR));
  76         ccr |= NDFC_CCR_RESET_ECC;
  77         out_be32((u32 *)(base + NDFC_CCR), ccr);
  78 }
  79
  80 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
  81                               const u_char *dat, u_char *ecc_code)
  82 {
  83         struct nand_chip *this = mtdinfo->priv;
  84         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
  85         u32 ecc;
  86         u8 *p = (u8 *)&ecc;
  87
  88         ecc = in_be32((u32 *)(base + NDFC_ECC));
  89
  90         /* The NDFC uses Smart Media (SMC) bytes order
  91          */
  92         ecc_code[0] = p[1];
  93         ecc_code[1] = p[2];
  94         ecc_code[2] = p[3];
  95
  96         return 0;
  97 }
  98
  99 /*
 100  * Speedups for buffer read/write/verify
 101  *
 102  * NDFC allows 32bit read/write of data. So we can speed up the buffer
 103  * functions. No further checking, as nand_base will always read/write
 104  * page aligned.
 105  */
 106 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 107 {
 108         struct nand_chip *this = mtdinfo->priv;
 109         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 110         uint32_t *p = (uint32_t *) buf;
 111
 112         for (;len > 0; len -= 4)
 113                 *p++ = in_be32((u32 *)(base + NDFC_DATA));
 114 }
 115
 116 #ifndef CONFIG_NAND_SPL
 117 /*
 118  * Don't use these speedup functions in NAND boot image, since the image
 119  * has to fit into 4kByte.
 120  */
 121 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 122 {
 123         struct nand_chip *this = mtdinfo->priv;
 124         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 125         uint32_t *p = (uint32_t *) buf;
 126
 127         for (; len > 0; len -= 4)
 128                 out_be32((u32 *)(base + NDFC_DATA), *p++);
 129 }
 130
 131 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 132 {
 133         struct nand_chip *this = mtdinfo->priv;
 134         ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 135         uint32_t *p = (uint32_t *) buf;
 136
 137         for (; len > 0; len -= 4)
 138                 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
 139                         return -1;
 140
 141         return 0;
 142 }
 143 #endif /* #ifndef CONFIG_NAND_SPL */
 144
 145 #ifndef CONFIG_SYS_NAND_BCR
 146 #define CONFIG_SYS_NAND_BCR 0x80002222
 147 #endif
 148
 149 void board_nand_select_device(struct nand_chip *nand, int chip)
 150 {
 151         /*
 152          * Don't use "chip" to address the NAND device,
 153          * generate the cs from the address where it is encoded.
 154          */
 155         ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
 156         int cs = ndfc_cs[chip];
 157
 158         /* Set NandFlash Core Configuration Register */
 159         /* 1 col x 2 rows */
 160         out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
 161         out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
 162 }
 163
 164 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
 165 {
 166         /*
 167          * Nothing to do here!
 168          */
 169 }
 170
 171 int board_nand_init(struct nand_chip *nand)
 172 {
 173         int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 174         ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
 175         static int chip = 0;
 176
 177         /*
 178          * Save chip-select for this chip #
 179          */
 180         ndfc_cs[chip] = cs;
 181
 182         /*
 183          * Select required NAND chip in NDFC
 184          */
 185         board_nand_select_device(nand, chip);
 186
 187         nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
 188         nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
 189         nand->cmd_ctrl = ndfc_hwcontrol;
 190         nand->chip_delay = 50;
 191         nand->read_buf = ndfc_read_buf;
 192         nand->dev_ready = ndfc_dev_ready;
 193         nand->ecc.correct = nand_correct_data;
 194         nand->ecc.hwctl = ndfc_enable_hwecc;
 195         nand->ecc.calculate = ndfc_calculate_ecc;
 196         nand->ecc.mode = NAND_ECC_HW;
 197         nand->ecc.size = 256;
 198         nand->ecc.bytes = 3;
 199         nand->select_chip = ndfc_select_chip;
 200
 201 #ifndef CONFIG_NAND_SPL
 202         nand->write_buf  = ndfc_write_buf;
 203         nand->verify_buf = ndfc_verify_buf;
 204 #else
 205         /*
 206          * Setup EBC (CS0 only right now)
 207          */
 208         mtebc(EBC0_CFG, 0xb8400000);
 209
 210         mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
 211         mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
 212 #endif
 213
 214         chip++;
 215
 216         return 0;
 217 }