2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/errno.h>
11 #include <asm/arch/mem.h>
12 #include <linux/mtd/omap_gpmc.h>
13 #include <linux/mtd/nand_ecc.h>
14 #include <linux/bch.h>
15 #include <linux/compiler.h>
17 #include <linux/mtd/omap_elm.h>
19 #define BADBLOCK_MARKER_LENGTH 2
20 #define SECTOR_BYTES 512
21 #define ECCCLEAR (0x1 << 8)
22 #define ECCRESULTREG1 (0x1 << 0)
23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
24 #define BCH4_BIT_PAD 4
27 static u8 bch8_polynomial
[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
28 0x97, 0x79, 0xe5, 0x24, 0xb5};
30 static uint8_t cs_next
;
31 static __maybe_unused
struct nand_ecclayout omap_ecclayout
;
33 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
34 static const int8_t wscfg
[CONFIG_SYS_MAX_NAND_DEVICE
] =
35 { CONFIG_NAND_OMAP_GPMC_WSCFG
};
37 /* wscfg is preset to zero since its a static variable */
38 static const int8_t wscfg
[CONFIG_SYS_MAX_NAND_DEVICE
];
42 * Driver configurations
44 struct omap_nand_info
{
45 struct bch_control
*control
;
46 enum omap_ecc ecc_scheme
;
48 uint8_t ws
; /* wait status pin (0,1) */
51 /* We are wasting a bit of memory but al least we are safe */
52 static struct omap_nand_info omap_nand_info
[GPMC_MAX_CS
];
55 * omap_nand_hwcontrol - Set the address pointers corretly for the
56 * following address/data/command operation
58 static void omap_nand_hwcontrol(struct mtd_info
*mtd
, int32_t cmd
,
61 register struct nand_chip
*this = mtd_to_nand(mtd
);
62 struct omap_nand_info
*info
= nand_get_controller_data(this);
66 * Point the IO_ADDR to DATA and ADDRESS registers instead
70 case NAND_CTRL_CHANGE
| NAND_CTRL_CLE
:
71 this->IO_ADDR_W
= (void __iomem
*)&gpmc_cfg
->cs
[cs
].nand_cmd
;
73 case NAND_CTRL_CHANGE
| NAND_CTRL_ALE
:
74 this->IO_ADDR_W
= (void __iomem
*)&gpmc_cfg
->cs
[cs
].nand_adr
;
76 case NAND_CTRL_CHANGE
| NAND_NCE
:
77 this->IO_ADDR_W
= (void __iomem
*)&gpmc_cfg
->cs
[cs
].nand_dat
;
81 if (cmd
!= NAND_CMD_NONE
)
82 writeb(cmd
, this->IO_ADDR_W
);
85 /* Check wait pin as dev ready indicator */
86 static int omap_dev_ready(struct mtd_info
*mtd
)
88 register struct nand_chip
*this = mtd_to_nand(mtd
);
89 struct omap_nand_info
*info
= nand_get_controller_data(this);
90 return gpmc_cfg
->status
& (1 << (8 + info
->ws
));
94 * gen_true_ecc - This function will generate true ECC value, which
95 * can be used when correcting data read from NAND flash memory core
97 * @ecc_buf: buffer to store ecc code
99 * @return: re-formatted ECC value
101 static uint32_t gen_true_ecc(uint8_t *ecc_buf
)
103 return ecc_buf
[0] | (ecc_buf
[1] << 16) | ((ecc_buf
[2] & 0xF0) << 20) |
104 ((ecc_buf
[2] & 0x0F) << 8);
108 * omap_correct_data - Compares the ecc read from nand spare area with ECC
109 * registers values and corrects one bit error if it has occurred
110 * Further details can be had from OMAP TRM and the following selected links:
111 * http://en.wikipedia.org/wiki/Hamming_code
112 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
114 * @mtd: MTD device structure
116 * @read_ecc: ecc read from nand flash
117 * @calc_ecc: ecc read from ECC registers
119 * @return 0 if data is OK or corrected, else returns -1
121 static int __maybe_unused
omap_correct_data(struct mtd_info
*mtd
, uint8_t *dat
,
122 uint8_t *read_ecc
, uint8_t *calc_ecc
)
124 uint32_t orig_ecc
, new_ecc
, res
, hm
;
125 uint16_t parity_bits
, byte
;
128 /* Regenerate the orginal ECC */
129 orig_ecc
= gen_true_ecc(read_ecc
);
130 new_ecc
= gen_true_ecc(calc_ecc
);
131 /* Get the XOR of real ecc */
132 res
= orig_ecc
^ new_ecc
;
134 /* Get the hamming width */
136 /* Single bit errors can be corrected! */
138 /* Correctable data! */
139 parity_bits
= res
>> 16;
140 bit
= (parity_bits
& 0x7);
141 byte
= (parity_bits
>> 3) & 0x1FF;
142 /* Flip the bit to correct */
143 dat
[byte
] ^= (0x1 << bit
);
144 } else if (hm
== 1) {
145 printf("Error: Ecc is wrong\n");
146 /* ECC itself is corrupted */
150 * hm distance != parity pairs OR one, could mean 2 bit
151 * error OR potentially be on a blank page..
152 * orig_ecc: contains spare area data from nand flash.
153 * new_ecc: generated ecc while reading data area.
154 * Note: if the ecc = 0, all data bits from which it was
155 * generated are 0xFF.
156 * The 3 byte(24 bits) ecc is generated per 512byte
157 * chunk of a page. If orig_ecc(from spare area)
158 * is 0xFF && new_ecc(computed now from data area)=0x0,
159 * this means that data area is 0xFF and spare area is
160 * 0xFF. A sure sign of a erased page!
162 if ((orig_ecc
== 0x0FFF0FFF) && (new_ecc
== 0x00000000))
164 printf("Error: Bad compare! failed\n");
165 /* detected 2 bit error */
173 * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
174 * @mtd: MTD device structure
175 * @mode: Read/Write mode
178 static void omap_enable_hwecc(struct mtd_info
*mtd
, int32_t mode
)
180 struct nand_chip
*nand
= mtd_to_nand(mtd
);
181 struct omap_nand_info
*info
= nand_get_controller_data(nand
);
182 unsigned int dev_width
= (nand
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
183 unsigned int ecc_algo
= 0;
184 unsigned int bch_type
= 0;
185 unsigned int eccsize1
= 0x00, eccsize0
= 0x00, bch_wrapmode
= 0x00;
186 u32 ecc_size_config_val
= 0;
187 u32 ecc_config_val
= 0;
190 /* configure GPMC for specific ecc-scheme */
191 switch (info
->ecc_scheme
) {
192 case OMAP_ECC_HAM1_CODE_SW
:
194 case OMAP_ECC_HAM1_CODE_HW
:
201 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
202 case OMAP_ECC_BCH8_CODE_HW
:
205 if (mode
== NAND_ECC_WRITE
) {
207 eccsize0
= 0; /* extra bits in nibbles per sector */
208 eccsize1
= 28; /* OOB bits in nibbles per sector */
211 eccsize0
= 26; /* ECC bits in nibbles per sector */
212 eccsize1
= 2; /* non-ECC bits in nibbles per sector */
215 case OMAP_ECC_BCH16_CODE_HW
:
218 if (mode
== NAND_ECC_WRITE
) {
220 eccsize0
= 0; /* extra bits in nibbles per sector */
221 eccsize1
= 52; /* OOB bits in nibbles per sector */
224 eccsize0
= 52; /* ECC bits in nibbles per sector */
225 eccsize1
= 0; /* non-ECC bits in nibbles per sector */
231 /* Clear ecc and enable bits */
232 writel(ECCCLEAR
| ECCRESULTREG1
, &gpmc_cfg
->ecc_control
);
233 /* Configure ecc size for BCH */
234 ecc_size_config_val
= (eccsize1
<< 22) | (eccsize0
<< 12);
235 writel(ecc_size_config_val
, &gpmc_cfg
->ecc_size_config
);
237 /* Configure device details for BCH engine */
238 ecc_config_val
= ((ecc_algo
<< 16) | /* HAM1 | BCHx */
239 (bch_type
<< 12) | /* BCH4/BCH8/BCH16 */
240 (bch_wrapmode
<< 8) | /* wrap mode */
241 (dev_width
<< 7) | /* bus width */
242 (0x0 << 4) | /* number of sectors */
243 (cs
<< 1) | /* ECC CS */
244 (0x1)); /* enable ECC */
245 writel(ecc_config_val
, &gpmc_cfg
->ecc_config
);
249 * omap_calculate_ecc - Read ECC result
250 * @mtd: MTD structure
252 * @ecc_code: ecc_code buffer
253 * Using noninverted ECC can be considered ugly since writing a blank
254 * page ie. padding will clear the ECC bytes. This is no problem as
255 * long nobody is trying to write data on the seemingly unused page.
256 * Reading an erased page will produce an ECC mismatch between
257 * generated and read ECC bytes that has to be dealt with separately.
258 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
259 * is used, the result of read will be 0x0 while the ECC offsets of the
260 * spare area will be 0xFF which will result in an ECC mismatch.
262 static int omap_calculate_ecc(struct mtd_info
*mtd
, const uint8_t *dat
,
265 struct nand_chip
*chip
= mtd_to_nand(mtd
);
266 struct omap_nand_info
*info
= nand_get_controller_data(chip
);
271 switch (info
->ecc_scheme
) {
272 case OMAP_ECC_HAM1_CODE_HW
:
273 val
= readl(&gpmc_cfg
->ecc1_result
);
274 ecc_code
[0] = val
& 0xFF;
275 ecc_code
[1] = (val
>> 16) & 0xFF;
276 ecc_code
[2] = ((val
>> 8) & 0x0F) | ((val
>> 20) & 0xF0);
279 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
281 case OMAP_ECC_BCH8_CODE_HW
:
282 ptr
= &gpmc_cfg
->bch_result_0_3
[0].bch_result_x
[3];
284 ecc_code
[i
++] = (val
>> 0) & 0xFF;
286 for (j
= 0; j
< 3; j
++) {
288 ecc_code
[i
++] = (val
>> 24) & 0xFF;
289 ecc_code
[i
++] = (val
>> 16) & 0xFF;
290 ecc_code
[i
++] = (val
>> 8) & 0xFF;
291 ecc_code
[i
++] = (val
>> 0) & 0xFF;
295 case OMAP_ECC_BCH16_CODE_HW
:
296 val
= readl(&gpmc_cfg
->bch_result_4_6
[0].bch_result_x
[2]);
297 ecc_code
[i
++] = (val
>> 8) & 0xFF;
298 ecc_code
[i
++] = (val
>> 0) & 0xFF;
299 val
= readl(&gpmc_cfg
->bch_result_4_6
[0].bch_result_x
[1]);
300 ecc_code
[i
++] = (val
>> 24) & 0xFF;
301 ecc_code
[i
++] = (val
>> 16) & 0xFF;
302 ecc_code
[i
++] = (val
>> 8) & 0xFF;
303 ecc_code
[i
++] = (val
>> 0) & 0xFF;
304 val
= readl(&gpmc_cfg
->bch_result_4_6
[0].bch_result_x
[0]);
305 ecc_code
[i
++] = (val
>> 24) & 0xFF;
306 ecc_code
[i
++] = (val
>> 16) & 0xFF;
307 ecc_code
[i
++] = (val
>> 8) & 0xFF;
308 ecc_code
[i
++] = (val
>> 0) & 0xFF;
309 for (j
= 3; j
>= 0; j
--) {
310 val
= readl(&gpmc_cfg
->bch_result_0_3
[0].bch_result_x
[j
]
312 ecc_code
[i
++] = (val
>> 24) & 0xFF;
313 ecc_code
[i
++] = (val
>> 16) & 0xFF;
314 ecc_code
[i
++] = (val
>> 8) & 0xFF;
315 ecc_code
[i
++] = (val
>> 0) & 0xFF;
321 /* ECC scheme specific syndrome customizations */
322 switch (info
->ecc_scheme
) {
323 case OMAP_ECC_HAM1_CODE_HW
:
326 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
328 for (i
= 0; i
< chip
->ecc
.bytes
; i
++)
329 *(ecc_code
+ i
) = *(ecc_code
+ i
) ^
333 case OMAP_ECC_BCH8_CODE_HW
:
334 ecc_code
[chip
->ecc
.bytes
- 1] = 0x00;
336 case OMAP_ECC_BCH16_CODE_HW
:
344 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
346 #define PREFETCH_CONFIG1_CS_SHIFT 24
347 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
348 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
349 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
350 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
351 #define ENABLE_PREFETCH (1 << 7)
354 * omap_prefetch_enable - configures and starts prefetch transfer
355 * @fifo_th: fifo threshold to be used for read/ write
356 * @count: number of bytes to be transferred
357 * @is_write: prefetch read(0) or write post(1) mode
358 * @cs: chip select to use
360 static int omap_prefetch_enable(int fifo_th
, unsigned int count
, int is_write
, int cs
)
364 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
)
367 if (readl(&gpmc_cfg
->prefetch_control
))
370 /* Set the amount of bytes to be prefetched */
371 writel(count
, &gpmc_cfg
->prefetch_config2
);
373 val
= (cs
<< PREFETCH_CONFIG1_CS_SHIFT
) | (is_write
& 1) |
374 PREFETCH_FIFOTHRESHOLD(fifo_th
) | ENABLE_PREFETCH
;
375 writel(val
, &gpmc_cfg
->prefetch_config1
);
377 /* Start the prefetch engine */
378 writel(1, &gpmc_cfg
->prefetch_control
);
384 * omap_prefetch_reset - disables and stops the prefetch engine
386 static void omap_prefetch_reset(void)
388 writel(0, &gpmc_cfg
->prefetch_control
);
389 writel(0, &gpmc_cfg
->prefetch_config1
);
392 static int __read_prefetch_aligned(struct nand_chip
*chip
, uint32_t *buf
, int len
)
396 struct omap_nand_info
*info
= nand_get_controller_data(chip
);
398 ret
= omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX
, len
, 0, info
->cs
);
405 cnt
= readl(&gpmc_cfg
->prefetch_status
);
406 cnt
= PREFETCH_STATUS_FIFO_CNT(cnt
);
408 for (i
= 0; i
< cnt
/ 4; i
++) {
409 *buf
++ = readl(CONFIG_SYS_NAND_BASE
);
414 omap_prefetch_reset();
419 static inline void omap_nand_read(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
421 struct nand_chip
*chip
= mtd_to_nand(mtd
);
423 if (chip
->options
& NAND_BUSWIDTH_16
)
424 nand_read_buf16(mtd
, buf
, len
);
426 nand_read_buf(mtd
, buf
, len
);
429 static void omap_nand_read_prefetch(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
433 struct nand_chip
*chip
= mtd_to_nand(mtd
);
436 * If the destination buffer is unaligned, start with reading
437 * the overlap byte-wise.
439 head
= ((uint32_t) buf
) % 4;
441 omap_nand_read(mtd
, buf
, head
);
447 * Only transfer multiples of 4 bytes in a pre-fetched fashion.
448 * If there's a residue, care for it byte-wise afterwards.
452 ret
= __read_prefetch_aligned(chip
, (uint32_t *)buf
, len
- tail
);
454 /* fallback in case the prefetch engine is busy */
455 omap_nand_read(mtd
, buf
, len
);
458 omap_nand_read(mtd
, buf
, tail
);
461 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
463 #ifdef CONFIG_NAND_OMAP_ELM
465 * omap_reverse_list - re-orders list elements in reverse order [internal]
466 * @list: pointer to start of list
467 * @length: length of list
469 static void omap_reverse_list(u8
*list
, unsigned int length
)
472 unsigned int half_length
= length
/ 2;
474 for (i
= 0, j
= length
- 1; i
< half_length
; i
++, j
--) {
482 * omap_correct_data_bch - Compares the ecc read from nand spare area
483 * with ECC registers values and corrects one bit error if it has occurred
485 * @mtd: MTD device structure
487 * @read_ecc: ecc read from nand flash (ignored)
488 * @calc_ecc: ecc read from ECC registers
490 * @return 0 if data is OK or corrected, else returns -1
492 static int omap_correct_data_bch(struct mtd_info
*mtd
, uint8_t *dat
,
493 uint8_t *read_ecc
, uint8_t *calc_ecc
)
495 struct nand_chip
*chip
= mtd_to_nand(mtd
);
496 struct omap_nand_info
*info
= nand_get_controller_data(chip
);
497 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
498 uint32_t error_count
= 0, error_max
;
499 uint32_t error_loc
[ELM_MAX_ERROR_COUNT
];
500 enum bch_level bch_type
;
501 uint32_t i
, ecc_flag
= 0;
503 uint32_t byte_pos
, bit_pos
;
506 /* check calculated ecc */
507 for (i
= 0; i
< ecc
->bytes
&& !ecc_flag
; i
++) {
508 if (calc_ecc
[i
] != 0x00)
514 /* check for whether its a erased-page */
516 for (i
= 0; i
< ecc
->bytes
&& !ecc_flag
; i
++) {
517 if (read_ecc
[i
] != 0xff)
524 * while reading ECC result we read it in big endian.
525 * Hence while loading to ELM we have rotate to get the right endian.
527 switch (info
->ecc_scheme
) {
528 case OMAP_ECC_BCH8_CODE_HW
:
529 bch_type
= BCH_8_BIT
;
530 omap_reverse_list(calc_ecc
, ecc
->bytes
- 1);
532 case OMAP_ECC_BCH16_CODE_HW
:
533 bch_type
= BCH_16_BIT
;
534 omap_reverse_list(calc_ecc
, ecc
->bytes
);
539 /* use elm module to check for errors */
540 elm_config(bch_type
);
541 err
= elm_check_error(calc_ecc
, bch_type
, &error_count
, error_loc
);
545 /* correct bch error */
546 for (count
= 0; count
< error_count
; count
++) {
547 switch (info
->ecc_scheme
) {
548 case OMAP_ECC_BCH8_CODE_HW
:
549 /* 14th byte in ECC is reserved to match ROM layout */
550 error_max
= SECTOR_BYTES
+ (ecc
->bytes
- 1);
552 case OMAP_ECC_BCH16_CODE_HW
:
553 error_max
= SECTOR_BYTES
+ ecc
->bytes
;
558 byte_pos
= error_max
- (error_loc
[count
] / 8) - 1;
559 bit_pos
= error_loc
[count
] % 8;
560 if (byte_pos
< SECTOR_BYTES
) {
561 dat
[byte_pos
] ^= 1 << bit_pos
;
562 debug("nand: bit-flip corrected @data=%d\n", byte_pos
);
563 } else if (byte_pos
< error_max
) {
564 read_ecc
[byte_pos
- SECTOR_BYTES
] ^= 1 << bit_pos
;
565 debug("nand: bit-flip corrected @oob=%d\n", byte_pos
-
569 printf("nand: error: invalid bit-flip location\n");
572 return (err
) ? err
: error_count
;
576 * omap_read_page_bch - hardware ecc based page read function
577 * @mtd: mtd info structure
578 * @chip: nand chip info structure
579 * @buf: buffer to store read data
580 * @oob_required: caller expects OOB data read to chip->oob_poi
581 * @page: page number to read
584 static int omap_read_page_bch(struct mtd_info
*mtd
, struct nand_chip
*chip
,
585 uint8_t *buf
, int oob_required
, int page
)
587 int i
, eccsize
= chip
->ecc
.size
;
588 int eccbytes
= chip
->ecc
.bytes
;
589 int eccsteps
= chip
->ecc
.steps
;
591 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
592 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
593 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
594 uint8_t *oob
= chip
->oob_poi
;
600 oob_pos
= (eccsize
* eccsteps
) + chip
->ecc
.layout
->eccpos
[0];
601 oob
+= chip
->ecc
.layout
->eccpos
[0];
603 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
,
605 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
607 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_pos
, -1);
608 chip
->read_buf(mtd
, p
, eccsize
);
610 /* read respective ecc from oob area */
611 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_pos
, -1);
612 chip
->read_buf(mtd
, oob
, eccbytes
);
614 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
620 for (i
= 0; i
< chip
->ecc
.total
; i
++)
621 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
623 eccsteps
= chip
->ecc
.steps
;
626 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
629 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
631 mtd
->ecc_stats
.failed
++;
633 mtd
->ecc_stats
.corrected
+= stat
;
637 #endif /* CONFIG_NAND_OMAP_ELM */
640 * OMAP3 BCH8 support (with BCH library)
644 * omap_correct_data_bch_sw - Decode received data and correct errors
645 * @mtd: MTD device structure
647 * @read_ecc: ecc read from nand flash
648 * @calc_ecc: ecc read from HW ECC registers
650 static int omap_correct_data_bch_sw(struct mtd_info
*mtd
, u_char
*data
,
651 u_char
*read_ecc
, u_char
*calc_ecc
)
654 /* cannot correct more than 8 errors */
655 unsigned int errloc
[8];
656 struct nand_chip
*chip
= mtd_to_nand(mtd
);
657 struct omap_nand_info
*info
= nand_get_controller_data(chip
);
659 count
= decode_bch(info
->control
, NULL
, 512, read_ecc
, calc_ecc
,
663 for (i
= 0; i
< count
; i
++) {
664 /* correct data only, not ecc bytes */
665 if (errloc
[i
] < 8*512)
666 data
[errloc
[i
]/8] ^= 1 << (errloc
[i
] & 7);
667 debug("corrected bitflip %u\n", errloc
[i
]);
671 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
674 for (i
= 0; i
< 13; i
++)
675 printf("%02x ", read_ecc
[i
]);
678 for (i
= 0; i
< 13; i
++)
679 printf("%02x ", calc_ecc
[i
]);
683 } else if (count
< 0) {
684 puts("ecc unrecoverable error\n");
690 * omap_free_bch - Release BCH ecc resources
691 * @mtd: MTD device structure
693 static void __maybe_unused
omap_free_bch(struct mtd_info
*mtd
)
695 struct nand_chip
*chip
= mtd_to_nand(mtd
);
696 struct omap_nand_info
*info
= nand_get_controller_data(chip
);
699 free_bch(info
->control
);
700 info
->control
= NULL
;
703 #endif /* CONFIG_BCH */
706 * omap_select_ecc_scheme - configures driver for particular ecc-scheme
707 * @nand: NAND chip device structure
708 * @ecc_scheme: ecc scheme to configure
709 * @pagesize: number of main-area bytes per page of NAND device
710 * @oobsize: number of OOB/spare bytes per page of NAND device
712 static int omap_select_ecc_scheme(struct nand_chip
*nand
,
713 enum omap_ecc ecc_scheme
, unsigned int pagesize
, unsigned int oobsize
) {
714 struct omap_nand_info
*info
= nand_get_controller_data(nand
);
715 struct nand_ecclayout
*ecclayout
= &omap_ecclayout
;
716 int eccsteps
= pagesize
/ SECTOR_BYTES
;
719 switch (ecc_scheme
) {
720 case OMAP_ECC_HAM1_CODE_SW
:
721 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
722 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
723 * initialized in nand_scan_tail(), so just set ecc.mode */
724 info
->control
= NULL
;
725 nand
->ecc
.mode
= NAND_ECC_SOFT
;
726 nand
->ecc
.layout
= NULL
;
730 case OMAP_ECC_HAM1_CODE_HW
:
731 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
732 /* check ecc-scheme requirements before updating ecc info */
733 if ((3 * eccsteps
) + BADBLOCK_MARKER_LENGTH
> oobsize
) {
734 printf("nand: error: insufficient OOB: require=%d\n", (
735 (3 * eccsteps
) + BADBLOCK_MARKER_LENGTH
));
738 info
->control
= NULL
;
739 /* populate ecc specific fields */
740 memset(&nand
->ecc
, 0, sizeof(struct nand_ecc_ctrl
));
741 nand
->ecc
.mode
= NAND_ECC_HW
;
742 nand
->ecc
.strength
= 1;
743 nand
->ecc
.size
= SECTOR_BYTES
;
745 nand
->ecc
.hwctl
= omap_enable_hwecc
;
746 nand
->ecc
.correct
= omap_correct_data
;
747 nand
->ecc
.calculate
= omap_calculate_ecc
;
748 /* define ecc-layout */
749 ecclayout
->eccbytes
= nand
->ecc
.bytes
* eccsteps
;
750 for (i
= 0; i
< ecclayout
->eccbytes
; i
++) {
751 if (nand
->options
& NAND_BUSWIDTH_16
)
752 ecclayout
->eccpos
[i
] = i
+ 2;
754 ecclayout
->eccpos
[i
] = i
+ 1;
756 ecclayout
->oobfree
[0].offset
= i
+ BADBLOCK_MARKER_LENGTH
;
757 ecclayout
->oobfree
[0].length
= oobsize
- ecclayout
->eccbytes
-
758 BADBLOCK_MARKER_LENGTH
;
761 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
763 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
764 /* check ecc-scheme requirements before updating ecc info */
765 if ((13 * eccsteps
) + BADBLOCK_MARKER_LENGTH
> oobsize
) {
766 printf("nand: error: insufficient OOB: require=%d\n", (
767 (13 * eccsteps
) + BADBLOCK_MARKER_LENGTH
));
770 /* check if BCH S/W library can be used for error detection */
771 info
->control
= init_bch(13, 8, 0x201b);
772 if (!info
->control
) {
773 printf("nand: error: could not init_bch()\n");
776 /* populate ecc specific fields */
777 memset(&nand
->ecc
, 0, sizeof(struct nand_ecc_ctrl
));
778 nand
->ecc
.mode
= NAND_ECC_HW
;
779 nand
->ecc
.strength
= 8;
780 nand
->ecc
.size
= SECTOR_BYTES
;
781 nand
->ecc
.bytes
= 13;
782 nand
->ecc
.hwctl
= omap_enable_hwecc
;
783 nand
->ecc
.correct
= omap_correct_data_bch_sw
;
784 nand
->ecc
.calculate
= omap_calculate_ecc
;
785 /* define ecc-layout */
786 ecclayout
->eccbytes
= nand
->ecc
.bytes
* eccsteps
;
787 ecclayout
->eccpos
[0] = BADBLOCK_MARKER_LENGTH
;
788 for (i
= 1; i
< ecclayout
->eccbytes
; i
++) {
789 if (i
% nand
->ecc
.bytes
)
790 ecclayout
->eccpos
[i
] =
791 ecclayout
->eccpos
[i
- 1] + 1;
793 ecclayout
->eccpos
[i
] =
794 ecclayout
->eccpos
[i
- 1] + 2;
796 ecclayout
->oobfree
[0].offset
= i
+ BADBLOCK_MARKER_LENGTH
;
797 ecclayout
->oobfree
[0].length
= oobsize
- ecclayout
->eccbytes
-
798 BADBLOCK_MARKER_LENGTH
;
801 printf("nand: error: CONFIG_BCH required for ECC\n");
805 case OMAP_ECC_BCH8_CODE_HW
:
806 #ifdef CONFIG_NAND_OMAP_ELM
807 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
808 /* check ecc-scheme requirements before updating ecc info */
809 if ((14 * eccsteps
) + BADBLOCK_MARKER_LENGTH
> oobsize
) {
810 printf("nand: error: insufficient OOB: require=%d\n", (
811 (14 * eccsteps
) + BADBLOCK_MARKER_LENGTH
));
814 /* intialize ELM for ECC error detection */
816 info
->control
= NULL
;
817 /* populate ecc specific fields */
818 memset(&nand
->ecc
, 0, sizeof(struct nand_ecc_ctrl
));
819 nand
->ecc
.mode
= NAND_ECC_HW
;
820 nand
->ecc
.strength
= 8;
821 nand
->ecc
.size
= SECTOR_BYTES
;
822 nand
->ecc
.bytes
= 14;
823 nand
->ecc
.hwctl
= omap_enable_hwecc
;
824 nand
->ecc
.correct
= omap_correct_data_bch
;
825 nand
->ecc
.calculate
= omap_calculate_ecc
;
826 nand
->ecc
.read_page
= omap_read_page_bch
;
827 /* define ecc-layout */
828 ecclayout
->eccbytes
= nand
->ecc
.bytes
* eccsteps
;
829 for (i
= 0; i
< ecclayout
->eccbytes
; i
++)
830 ecclayout
->eccpos
[i
] = i
+ BADBLOCK_MARKER_LENGTH
;
831 ecclayout
->oobfree
[0].offset
= i
+ BADBLOCK_MARKER_LENGTH
;
832 ecclayout
->oobfree
[0].length
= oobsize
- ecclayout
->eccbytes
-
833 BADBLOCK_MARKER_LENGTH
;
836 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
840 case OMAP_ECC_BCH16_CODE_HW
:
841 #ifdef CONFIG_NAND_OMAP_ELM
842 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
843 /* check ecc-scheme requirements before updating ecc info */
844 if ((26 * eccsteps
) + BADBLOCK_MARKER_LENGTH
> oobsize
) {
845 printf("nand: error: insufficient OOB: require=%d\n", (
846 (26 * eccsteps
) + BADBLOCK_MARKER_LENGTH
));
849 /* intialize ELM for ECC error detection */
851 /* populate ecc specific fields */
852 nand
->ecc
.mode
= NAND_ECC_HW
;
853 nand
->ecc
.size
= SECTOR_BYTES
;
854 nand
->ecc
.bytes
= 26;
855 nand
->ecc
.strength
= 16;
856 nand
->ecc
.hwctl
= omap_enable_hwecc
;
857 nand
->ecc
.correct
= omap_correct_data_bch
;
858 nand
->ecc
.calculate
= omap_calculate_ecc
;
859 nand
->ecc
.read_page
= omap_read_page_bch
;
860 /* define ecc-layout */
861 ecclayout
->eccbytes
= nand
->ecc
.bytes
* eccsteps
;
862 for (i
= 0; i
< ecclayout
->eccbytes
; i
++)
863 ecclayout
->eccpos
[i
] = i
+ BADBLOCK_MARKER_LENGTH
;
864 ecclayout
->oobfree
[0].offset
= i
+ BADBLOCK_MARKER_LENGTH
;
865 ecclayout
->oobfree
[0].length
= oobsize
- nand
->ecc
.bytes
-
866 BADBLOCK_MARKER_LENGTH
;
869 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
873 debug("nand: error: ecc scheme not enabled or supported\n");
877 /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
878 if (ecc_scheme
!= OMAP_ECC_HAM1_CODE_SW
)
879 nand
->ecc
.layout
= ecclayout
;
881 info
->ecc_scheme
= ecc_scheme
;
885 #ifndef CONFIG_SPL_BUILD
887 * omap_nand_switch_ecc - switch the ECC operation between different engines
888 * (h/w and s/w) and different algorithms (hamming and BCHx)
890 * @hardware - true if one of the HW engines should be used
891 * @eccstrength - the number of bits that could be corrected
892 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
894 int __maybe_unused
omap_nand_switch_ecc(uint32_t hardware
, uint32_t eccstrength
)
896 struct nand_chip
*nand
;
897 struct mtd_info
*mtd
;
900 if (nand_curr_device
< 0 ||
901 nand_curr_device
>= CONFIG_SYS_MAX_NAND_DEVICE
||
902 !nand_info
[nand_curr_device
]) {
903 printf("nand: error: no NAND devices found\n");
907 mtd
= nand_info
[nand_curr_device
];
908 nand
= mtd_to_nand(mtd
);
909 nand
->options
|= NAND_OWN_BUFFERS
;
910 nand
->options
&= ~NAND_SUBPAGE_READ
;
911 /* Setup the ecc configurations again */
913 if (eccstrength
== 1) {
914 err
= omap_select_ecc_scheme(nand
,
915 OMAP_ECC_HAM1_CODE_HW
,
916 mtd
->writesize
, mtd
->oobsize
);
917 } else if (eccstrength
== 8) {
918 err
= omap_select_ecc_scheme(nand
,
919 OMAP_ECC_BCH8_CODE_HW
,
920 mtd
->writesize
, mtd
->oobsize
);
921 } else if (eccstrength
== 16) {
922 err
= omap_select_ecc_scheme(nand
,
923 OMAP_ECC_BCH16_CODE_HW
,
924 mtd
->writesize
, mtd
->oobsize
);
926 printf("nand: error: unsupported ECC scheme\n");
930 if (eccstrength
== 1) {
931 err
= omap_select_ecc_scheme(nand
,
932 OMAP_ECC_HAM1_CODE_SW
,
933 mtd
->writesize
, mtd
->oobsize
);
934 } else if (eccstrength
== 8) {
935 err
= omap_select_ecc_scheme(nand
,
936 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
,
937 mtd
->writesize
, mtd
->oobsize
);
939 printf("nand: error: unsupported ECC scheme\n");
944 /* Update NAND handling after ECC mode switch */
946 err
= nand_scan_tail(mtd
);
949 #endif /* CONFIG_SPL_BUILD */
952 * Board-specific NAND initialization. The following members of the
953 * argument are board-specific:
954 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
955 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
956 * - cmd_ctrl: hardwarespecific function for accesing control-lines
957 * - waitfunc: hardwarespecific function for accesing device ready/busy line
958 * - ecc.hwctl: function to enable (reset) hardware ecc generator
959 * - ecc.mode: mode of ecc, see defines
960 * - chip_delay: chip dependent delay for transfering data from array to
962 * - options: various chip options. They can partly be set to inform
963 * nand_scan about special functionality. See the defines for further
966 int board_nand_init(struct nand_chip
*nand
)
968 int32_t gpmc_config
= 0;
972 * xloader/Uboot's gpmc configuration would have configured GPMC for
973 * nand type of memory. The following logic scans and latches on to the
974 * first CS with NAND type memory.
975 * TBD: need to make this logic generic to handle multiple CS NAND
978 while (cs
< GPMC_MAX_CS
) {
979 /* Check if NAND type is set */
980 if ((readl(&gpmc_cfg
->cs
[cs
].config1
) & 0xC00) == 0x800) {
986 if (cs
>= GPMC_MAX_CS
) {
987 printf("nand: error: Unable to find NAND settings in "
988 "GPMC Configuration - quitting\n");
992 gpmc_config
= readl(&gpmc_cfg
->config
);
993 /* Disable Write protect */
995 writel(gpmc_config
, &gpmc_cfg
->config
);
997 nand
->IO_ADDR_R
= (void __iomem
*)&gpmc_cfg
->cs
[cs
].nand_dat
;
998 nand
->IO_ADDR_W
= (void __iomem
*)&gpmc_cfg
->cs
[cs
].nand_cmd
;
999 omap_nand_info
[cs
].control
= NULL
;
1000 omap_nand_info
[cs
].cs
= cs
;
1001 omap_nand_info
[cs
].ws
= wscfg
[cs
];
1002 nand_set_controller_data(nand
, &omap_nand_info
[cs
]);
1003 nand
->cmd_ctrl
= omap_nand_hwcontrol
;
1004 nand
->options
|= NAND_NO_PADDING
| NAND_CACHEPRG
;
1005 nand
->chip_delay
= 100;
1006 nand
->ecc
.layout
= &omap_ecclayout
;
1008 /* configure driver and controller based on NAND device bus-width */
1009 gpmc_config
= readl(&gpmc_cfg
->cs
[cs
].config1
);
1010 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
1011 nand
->options
|= NAND_BUSWIDTH_16
;
1012 writel(gpmc_config
| (0x1 << 12), &gpmc_cfg
->cs
[cs
].config1
);
1014 nand
->options
&= ~NAND_BUSWIDTH_16
;
1015 writel(gpmc_config
& ~(0x1 << 12), &gpmc_cfg
->cs
[cs
].config1
);
1017 /* select ECC scheme */
1018 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1019 err
= omap_select_ecc_scheme(nand
, CONFIG_NAND_OMAP_ECCSCHEME
,
1020 CONFIG_SYS_NAND_PAGE_SIZE
, CONFIG_SYS_NAND_OOBSIZE
);
1022 /* pagesize and oobsize are not required to configure sw ecc-scheme */
1023 err
= omap_select_ecc_scheme(nand
, OMAP_ECC_HAM1_CODE_SW
,
1029 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
1030 nand
->read_buf
= omap_nand_read_prefetch
;
1032 if (nand
->options
& NAND_BUSWIDTH_16
)
1033 nand
->read_buf
= nand_read_buf16
;
1035 nand
->read_buf
= nand_read_buf
;
1038 nand
->dev_ready
= omap_dev_ready
;