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dm: core: Create a new header file for 'compat' features
[thirdparty/u-boot.git] / drivers / mtd / nand / raw / atmel_nand.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 *
9 * Add Programmable Multibit ECC support for various AT91 SoC
10 * (C) Copyright 2012 ATMEL, Hong Xu
11 */
12
13 #include <common.h>
14 #include <asm/gpio.h>
15 #include <asm/arch/gpio.h>
16 #include <dm/device_compat.h>
17 #include <dm/devres.h>
18
19 #include <malloc.h>
20 #include <nand.h>
21 #include <watchdog.h>
22 #include <linux/mtd/nand_ecc.h>
23
24 #ifdef CONFIG_ATMEL_NAND_HWECC
25
26 /* Register access macros */
27 #define ecc_readl(add, reg) \
28 readl(add + ATMEL_ECC_##reg)
29 #define ecc_writel(add, reg, value) \
30 writel((value), add + ATMEL_ECC_##reg)
31
32 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33
34 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35
36 #ifdef CONFIG_SPL_BUILD
37 #undef CONFIG_SYS_NAND_ONFI_DETECTION
38 #endif
39
40 struct atmel_nand_host {
41 struct pmecc_regs __iomem *pmecc;
42 struct pmecc_errloc_regs __iomem *pmerrloc;
43 void __iomem *pmecc_rom_base;
44
45 u8 pmecc_corr_cap;
46 u16 pmecc_sector_size;
47 u32 pmecc_index_table_offset;
48 u32 pmecc_version;
49
50 int pmecc_bytes_per_sector;
51 int pmecc_sector_number;
52 int pmecc_degree; /* Degree of remainders */
53 int pmecc_cw_len; /* Length of codeword */
54
55 /* lookup table for alpha_to and index_of */
56 void __iomem *pmecc_alpha_to;
57 void __iomem *pmecc_index_of;
58
59 /* data for pmecc computation */
60 int16_t *pmecc_smu;
61 int16_t *pmecc_partial_syn;
62 int16_t *pmecc_si;
63 int16_t *pmecc_lmu; /* polynomal order */
64 int *pmecc_mu;
65 int *pmecc_dmu;
66 int *pmecc_delta;
67 };
68
69 static struct atmel_nand_host pmecc_host;
70 static struct nand_ecclayout atmel_pmecc_oobinfo;
71
72 /*
73 * Return number of ecc bytes per sector according to sector size and
74 * correction capability
75 *
76 * Following table shows what at91 PMECC supported:
77 * Correction Capability Sector_512_bytes Sector_1024_bytes
78 * ===================== ================ =================
79 * 2-bits 4-bytes 4-bytes
80 * 4-bits 7-bytes 7-bytes
81 * 8-bits 13-bytes 14-bytes
82 * 12-bits 20-bytes 21-bytes
83 * 24-bits 39-bytes 42-bytes
84 * 32-bits 52-bytes 56-bytes
85 */
86 static int pmecc_get_ecc_bytes(int cap, int sector_size)
87 {
88 int m = 12 + sector_size / 512;
89 return (m * cap + 7) / 8;
90 }
91
92 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
93 int oobsize, int ecc_len)
94 {
95 int i;
96
97 layout->eccbytes = ecc_len;
98
99 /* ECC will occupy the last ecc_len bytes continuously */
100 for (i = 0; i < ecc_len; i++)
101 layout->eccpos[i] = oobsize - ecc_len + i;
102
103 layout->oobfree[0].offset = 2;
104 layout->oobfree[0].length =
105 oobsize - ecc_len - layout->oobfree[0].offset;
106 }
107
108 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
109 {
110 int table_size;
111
112 table_size = host->pmecc_sector_size == 512 ?
113 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
114
115 /* the ALPHA lookup table is right behind the INDEX lookup table. */
116 return host->pmecc_rom_base + host->pmecc_index_table_offset +
117 table_size * sizeof(int16_t);
118 }
119
120 static void pmecc_data_free(struct atmel_nand_host *host)
121 {
122 free(host->pmecc_partial_syn);
123 free(host->pmecc_si);
124 free(host->pmecc_lmu);
125 free(host->pmecc_smu);
126 free(host->pmecc_mu);
127 free(host->pmecc_dmu);
128 free(host->pmecc_delta);
129 }
130
131 static int pmecc_data_alloc(struct atmel_nand_host *host)
132 {
133 const int cap = host->pmecc_corr_cap;
134 int size;
135
136 size = (2 * cap + 1) * sizeof(int16_t);
137 host->pmecc_partial_syn = malloc(size);
138 host->pmecc_si = malloc(size);
139 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
140 host->pmecc_smu = malloc((cap + 2) * size);
141
142 size = (cap + 1) * sizeof(int);
143 host->pmecc_mu = malloc(size);
144 host->pmecc_dmu = malloc(size);
145 host->pmecc_delta = malloc(size);
146
147 if (host->pmecc_partial_syn &&
148 host->pmecc_si &&
149 host->pmecc_lmu &&
150 host->pmecc_smu &&
151 host->pmecc_mu &&
152 host->pmecc_dmu &&
153 host->pmecc_delta)
154 return 0;
155
156 /* error happened */
157 pmecc_data_free(host);
158 return -ENOMEM;
159
160 }
161
162 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
163 {
164 struct nand_chip *nand_chip = mtd_to_nand(mtd);
165 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
166 int i;
167 uint32_t value;
168
169 /* Fill odd syndromes */
170 for (i = 0; i < host->pmecc_corr_cap; i++) {
171 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
172 if (i & 1)
173 value >>= 16;
174 value &= 0xffff;
175 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
176 }
177 }
178
179 static void pmecc_substitute(struct mtd_info *mtd)
180 {
181 struct nand_chip *nand_chip = mtd_to_nand(mtd);
182 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
183 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
184 int16_t __iomem *index_of = host->pmecc_index_of;
185 int16_t *partial_syn = host->pmecc_partial_syn;
186 const int cap = host->pmecc_corr_cap;
187 int16_t *si;
188 int i, j;
189
190 /* si[] is a table that holds the current syndrome value,
191 * an element of that table belongs to the field
192 */
193 si = host->pmecc_si;
194
195 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
196
197 /* Computation 2t syndromes based on S(x) */
198 /* Odd syndromes */
199 for (i = 1; i < 2 * cap; i += 2) {
200 for (j = 0; j < host->pmecc_degree; j++) {
201 if (partial_syn[i] & (0x1 << j))
202 si[i] = readw(alpha_to + i * j) ^ si[i];
203 }
204 }
205 /* Even syndrome = (Odd syndrome) ** 2 */
206 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
207 if (si[j] == 0) {
208 si[i] = 0;
209 } else {
210 int16_t tmp;
211
212 tmp = readw(index_of + si[j]);
213 tmp = (tmp * 2) % host->pmecc_cw_len;
214 si[i] = readw(alpha_to + tmp);
215 }
216 }
217 }
218
219 /*
220 * This function defines a Berlekamp iterative procedure for
221 * finding the value of the error location polynomial.
222 * The input is si[], initialize by pmecc_substitute().
223 * The output is smu[][].
224 *
225 * This function is written according to chip datasheet Chapter:
226 * Find the Error Location Polynomial Sigma(x) of Section:
227 * Programmable Multibit ECC Control (PMECC).
228 */
229 static void pmecc_get_sigma(struct mtd_info *mtd)
230 {
231 struct nand_chip *nand_chip = mtd_to_nand(mtd);
232 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
233
234 int16_t *lmu = host->pmecc_lmu;
235 int16_t *si = host->pmecc_si;
236 int *mu = host->pmecc_mu;
237 int *dmu = host->pmecc_dmu; /* Discrepancy */
238 int *delta = host->pmecc_delta; /* Delta order */
239 int cw_len = host->pmecc_cw_len;
240 const int16_t cap = host->pmecc_corr_cap;
241 const int num = 2 * cap + 1;
242 int16_t __iomem *index_of = host->pmecc_index_of;
243 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
244 int i, j, k;
245 uint32_t dmu_0_count, tmp;
246 int16_t *smu = host->pmecc_smu;
247
248 /* index of largest delta */
249 int ro;
250 int largest;
251 int diff;
252
253 /* Init the Sigma(x) */
254 memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
255
256 dmu_0_count = 0;
257
258 /* First Row */
259
260 /* Mu */
261 mu[0] = -1;
262
263 smu[0] = 1;
264
265 /* discrepancy set to 1 */
266 dmu[0] = 1;
267 /* polynom order set to 0 */
268 lmu[0] = 0;
269 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
270 delta[0] = -1;
271
272 /* Second Row */
273
274 /* Mu */
275 mu[1] = 0;
276 /* Sigma(x) set to 1 */
277 smu[num] = 1;
278
279 /* discrepancy set to S1 */
280 dmu[1] = si[1];
281
282 /* polynom order set to 0 */
283 lmu[1] = 0;
284
285 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
286 delta[1] = 0;
287
288 for (i = 1; i <= cap; i++) {
289 mu[i + 1] = i << 1;
290 /* Begin Computing Sigma (Mu+1) and L(mu) */
291 /* check if discrepancy is set to 0 */
292 if (dmu[i] == 0) {
293 dmu_0_count++;
294
295 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
296 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
297 tmp += 2;
298 else
299 tmp += 1;
300
301 if (dmu_0_count == tmp) {
302 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
303 smu[(cap + 1) * num + j] =
304 smu[i * num + j];
305
306 lmu[cap + 1] = lmu[i];
307 return;
308 }
309
310 /* copy polynom */
311 for (j = 0; j <= lmu[i] >> 1; j++)
312 smu[(i + 1) * num + j] = smu[i * num + j];
313
314 /* copy previous polynom order to the next */
315 lmu[i + 1] = lmu[i];
316 } else {
317 ro = 0;
318 largest = -1;
319 /* find largest delta with dmu != 0 */
320 for (j = 0; j < i; j++) {
321 if ((dmu[j]) && (delta[j] > largest)) {
322 largest = delta[j];
323 ro = j;
324 }
325 }
326
327 /* compute difference */
328 diff = (mu[i] - mu[ro]);
329
330 /* Compute degree of the new smu polynomial */
331 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
332 lmu[i + 1] = lmu[i];
333 else
334 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
335
336 /* Init smu[i+1] with 0 */
337 for (k = 0; k < num; k++)
338 smu[(i + 1) * num + k] = 0;
339
340 /* Compute smu[i+1] */
341 for (k = 0; k <= lmu[ro] >> 1; k++) {
342 int16_t a, b, c;
343
344 if (!(smu[ro * num + k] && dmu[i]))
345 continue;
346 a = readw(index_of + dmu[i]);
347 b = readw(index_of + dmu[ro]);
348 c = readw(index_of + smu[ro * num + k]);
349 tmp = a + (cw_len - b) + c;
350 a = readw(alpha_to + tmp % cw_len);
351 smu[(i + 1) * num + (k + diff)] = a;
352 }
353
354 for (k = 0; k <= lmu[i] >> 1; k++)
355 smu[(i + 1) * num + k] ^= smu[i * num + k];
356 }
357
358 /* End Computing Sigma (Mu+1) and L(mu) */
359 /* In either case compute delta */
360 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
361
362 /* Do not compute discrepancy for the last iteration */
363 if (i >= cap)
364 continue;
365
366 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
367 tmp = 2 * (i - 1);
368 if (k == 0) {
369 dmu[i + 1] = si[tmp + 3];
370 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
371 int16_t a, b, c;
372 a = readw(index_of +
373 smu[(i + 1) * num + k]);
374 b = si[2 * (i - 1) + 3 - k];
375 c = readw(index_of + b);
376 tmp = a + c;
377 tmp %= cw_len;
378 dmu[i + 1] = readw(alpha_to + tmp) ^
379 dmu[i + 1];
380 }
381 }
382 }
383 }
384
385 static int pmecc_err_location(struct mtd_info *mtd)
386 {
387 struct nand_chip *nand_chip = mtd_to_nand(mtd);
388 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
389 const int cap = host->pmecc_corr_cap;
390 const int num = 2 * cap + 1;
391 int sector_size = host->pmecc_sector_size;
392 int err_nbr = 0; /* number of error */
393 int roots_nbr; /* number of roots */
394 int i;
395 uint32_t val;
396 int16_t *smu = host->pmecc_smu;
397 int timeout = PMECC_MAX_TIMEOUT_US;
398
399 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
400
401 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
402 pmecc_writel(host->pmerrloc, sigma[i],
403 smu[(cap + 1) * num + i]);
404 err_nbr++;
405 }
406
407 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
408 if (sector_size == 1024)
409 val |= PMERRLOC_ELCFG_SECTOR_1024;
410
411 pmecc_writel(host->pmerrloc, elcfg, val);
412 pmecc_writel(host->pmerrloc, elen,
413 sector_size * 8 + host->pmecc_degree * cap);
414
415 while (--timeout) {
416 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
417 break;
418 WATCHDOG_RESET();
419 udelay(1);
420 }
421
422 if (!timeout) {
423 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
424 return -1;
425 }
426
427 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
428 >> 8;
429 /* Number of roots == degree of smu hence <= cap */
430 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
431 return err_nbr - 1;
432
433 /* Number of roots does not match the degree of smu
434 * unable to correct error */
435 return -1;
436 }
437
438 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
439 int sector_num, int extra_bytes, int err_nbr)
440 {
441 struct nand_chip *nand_chip = mtd_to_nand(mtd);
442 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
443 int i = 0;
444 int byte_pos, bit_pos, sector_size, pos;
445 uint32_t tmp;
446 uint8_t err_byte;
447
448 sector_size = host->pmecc_sector_size;
449
450 while (err_nbr) {
451 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
452 byte_pos = tmp / 8;
453 bit_pos = tmp % 8;
454
455 if (byte_pos >= (sector_size + extra_bytes))
456 BUG(); /* should never happen */
457
458 if (byte_pos < sector_size) {
459 err_byte = *(buf + byte_pos);
460 *(buf + byte_pos) ^= (1 << bit_pos);
461
462 pos = sector_num * host->pmecc_sector_size + byte_pos;
463 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
464 pos, bit_pos, err_byte, *(buf + byte_pos));
465 } else {
466 /* Bit flip in OOB area */
467 tmp = sector_num * host->pmecc_bytes_per_sector
468 + (byte_pos - sector_size);
469 err_byte = ecc[tmp];
470 ecc[tmp] ^= (1 << bit_pos);
471
472 pos = tmp + nand_chip->ecc.layout->eccpos[0];
473 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
474 pos, bit_pos, err_byte, ecc[tmp]);
475 }
476
477 i++;
478 err_nbr--;
479 }
480
481 return;
482 }
483
484 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
485 u8 *ecc)
486 {
487 struct nand_chip *nand_chip = mtd_to_nand(mtd);
488 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
489 int i, err_nbr, eccbytes;
490 uint8_t *buf_pos;
491
492 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
493 if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
494 goto normal_check;
495
496 eccbytes = nand_chip->ecc.bytes;
497 for (i = 0; i < eccbytes; i++)
498 if (ecc[i] != 0xff)
499 goto normal_check;
500 /* Erased page, return OK */
501 return 0;
502
503 normal_check:
504 for (i = 0; i < host->pmecc_sector_number; i++) {
505 err_nbr = 0;
506 if (pmecc_stat & 0x1) {
507 buf_pos = buf + i * host->pmecc_sector_size;
508
509 pmecc_gen_syndrome(mtd, i);
510 pmecc_substitute(mtd);
511 pmecc_get_sigma(mtd);
512
513 err_nbr = pmecc_err_location(mtd);
514 if (err_nbr == -1) {
515 dev_err(host->dev, "PMECC: Too many errors\n");
516 mtd->ecc_stats.failed++;
517 return -EBADMSG;
518 } else {
519 pmecc_correct_data(mtd, buf_pos, ecc, i,
520 host->pmecc_bytes_per_sector, err_nbr);
521 mtd->ecc_stats.corrected += err_nbr;
522 }
523 }
524 pmecc_stat >>= 1;
525 }
526
527 return 0;
528 }
529
530 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
531 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
532 {
533 struct atmel_nand_host *host = nand_get_controller_data(chip);
534 int eccsize = chip->ecc.size;
535 uint8_t *oob = chip->oob_poi;
536 uint32_t *eccpos = chip->ecc.layout->eccpos;
537 uint32_t stat;
538 int timeout = PMECC_MAX_TIMEOUT_US;
539
540 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
541 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
542 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
543 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
544
545 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
546 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
547
548 chip->read_buf(mtd, buf, eccsize);
549 chip->read_buf(mtd, oob, mtd->oobsize);
550
551 while (--timeout) {
552 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
553 break;
554 WATCHDOG_RESET();
555 udelay(1);
556 }
557
558 if (!timeout) {
559 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
560 return -1;
561 }
562
563 stat = pmecc_readl(host->pmecc, isr);
564 if (stat != 0)
565 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
566 return -EBADMSG;
567
568 return 0;
569 }
570
571 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
572 struct nand_chip *chip, const uint8_t *buf,
573 int oob_required, int page)
574 {
575 struct atmel_nand_host *host = nand_get_controller_data(chip);
576 uint32_t *eccpos = chip->ecc.layout->eccpos;
577 int i, j;
578 int timeout = PMECC_MAX_TIMEOUT_US;
579
580 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
581 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
582
583 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
584 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
585
586 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
587 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
588
589 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
590
591 while (--timeout) {
592 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
593 break;
594 WATCHDOG_RESET();
595 udelay(1);
596 }
597
598 if (!timeout) {
599 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
600 goto out;
601 }
602
603 for (i = 0; i < host->pmecc_sector_number; i++) {
604 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
605 int pos;
606
607 pos = i * host->pmecc_bytes_per_sector + j;
608 chip->oob_poi[eccpos[pos]] =
609 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
610 }
611 }
612 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
613 out:
614 return 0;
615 }
616
617 static void atmel_pmecc_core_init(struct mtd_info *mtd)
618 {
619 struct nand_chip *nand_chip = mtd_to_nand(mtd);
620 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
621 uint32_t val = 0;
622 struct nand_ecclayout *ecc_layout;
623
624 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
625 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
626
627 switch (host->pmecc_corr_cap) {
628 case 2:
629 val = PMECC_CFG_BCH_ERR2;
630 break;
631 case 4:
632 val = PMECC_CFG_BCH_ERR4;
633 break;
634 case 8:
635 val = PMECC_CFG_BCH_ERR8;
636 break;
637 case 12:
638 val = PMECC_CFG_BCH_ERR12;
639 break;
640 case 24:
641 val = PMECC_CFG_BCH_ERR24;
642 break;
643 case 32:
644 val = PMECC_CFG_BCH_ERR32;
645 break;
646 }
647
648 if (host->pmecc_sector_size == 512)
649 val |= PMECC_CFG_SECTOR512;
650 else if (host->pmecc_sector_size == 1024)
651 val |= PMECC_CFG_SECTOR1024;
652
653 switch (host->pmecc_sector_number) {
654 case 1:
655 val |= PMECC_CFG_PAGE_1SECTOR;
656 break;
657 case 2:
658 val |= PMECC_CFG_PAGE_2SECTORS;
659 break;
660 case 4:
661 val |= PMECC_CFG_PAGE_4SECTORS;
662 break;
663 case 8:
664 val |= PMECC_CFG_PAGE_8SECTORS;
665 break;
666 }
667
668 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
669 | PMECC_CFG_AUTO_DISABLE);
670 pmecc_writel(host->pmecc, cfg, val);
671
672 ecc_layout = nand_chip->ecc.layout;
673 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
674 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
675 pmecc_writel(host->pmecc, eaddr,
676 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
677 /* See datasheet about PMECC Clock Control Register */
678 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
679 pmecc_writel(host->pmecc, idr, 0xff);
680 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
681 }
682
683 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
684 /*
685 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
686 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
687 * ONFI ECC parameters.
688 * @host: point to an atmel_nand_host structure.
689 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
690 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
691 * @chip: point to an nand_chip structure.
692 * @cap: store the ONFI ECC correct bits capbility
693 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
694 *
695 * Return 0 if success. otherwise return the error code.
696 */
697 static int pmecc_choose_ecc(struct atmel_nand_host *host,
698 struct nand_chip *chip,
699 int *cap, int *sector_size)
700 {
701 /* Get ECC requirement from ONFI parameters */
702 *cap = *sector_size = 0;
703 if (chip->onfi_version) {
704 *cap = chip->ecc_strength_ds;
705 *sector_size = chip->ecc_step_ds;
706 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
707 *cap, *sector_size);
708 }
709
710 if (*cap == 0 && *sector_size == 0) {
711 /* Non-ONFI compliant */
712 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
713 *cap = 2;
714 *sector_size = 512;
715 }
716
717 /* If head file doesn't specify then use the one in ONFI parameters */
718 if (host->pmecc_corr_cap == 0) {
719 /* use the most fitable ecc bits (the near bigger one ) */
720 if (*cap <= 2)
721 host->pmecc_corr_cap = 2;
722 else if (*cap <= 4)
723 host->pmecc_corr_cap = 4;
724 else if (*cap <= 8)
725 host->pmecc_corr_cap = 8;
726 else if (*cap <= 12)
727 host->pmecc_corr_cap = 12;
728 else if (*cap <= 24)
729 host->pmecc_corr_cap = 24;
730 else
731 #ifdef CONFIG_SAMA5D2
732 host->pmecc_corr_cap = 32;
733 #else
734 host->pmecc_corr_cap = 24;
735 #endif
736 }
737 if (host->pmecc_sector_size == 0) {
738 /* use the most fitable sector size (the near smaller one ) */
739 if (*sector_size >= 1024)
740 host->pmecc_sector_size = 1024;
741 else if (*sector_size >= 512)
742 host->pmecc_sector_size = 512;
743 else
744 return -EINVAL;
745 }
746 return 0;
747 }
748 #endif
749
750 #if defined(NO_GALOIS_TABLE_IN_ROM)
751 static uint16_t *pmecc_galois_table;
752 static inline int deg(unsigned int poly)
753 {
754 /* polynomial degree is the most-significant bit index */
755 return fls(poly) - 1;
756 }
757
758 static int build_gf_tables(int mm, unsigned int poly,
759 int16_t *index_of, int16_t *alpha_to)
760 {
761 unsigned int i, x = 1;
762 const unsigned int k = 1 << deg(poly);
763 unsigned int nn = (1 << mm) - 1;
764
765 /* primitive polynomial must be of degree m */
766 if (k != (1u << mm))
767 return -EINVAL;
768
769 for (i = 0; i < nn; i++) {
770 alpha_to[i] = x;
771 index_of[x] = i;
772 if (i && (x == 1))
773 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
774 return -EINVAL;
775 x <<= 1;
776 if (x & k)
777 x ^= poly;
778 }
779
780 alpha_to[nn] = 1;
781 index_of[0] = 0;
782
783 return 0;
784 }
785
786 static uint16_t *create_lookup_table(int sector_size)
787 {
788 int degree = (sector_size == 512) ?
789 PMECC_GF_DIMENSION_13 :
790 PMECC_GF_DIMENSION_14;
791 unsigned int poly = (sector_size == 512) ?
792 PMECC_GF_13_PRIMITIVE_POLY :
793 PMECC_GF_14_PRIMITIVE_POLY;
794 int table_size = (sector_size == 512) ?
795 PMECC_INDEX_TABLE_SIZE_512 :
796 PMECC_INDEX_TABLE_SIZE_1024;
797
798 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
799 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
800 return NULL;
801
802 return (uint16_t *)addr;
803 }
804 #endif
805
806 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
807 struct mtd_info *mtd)
808 {
809 struct atmel_nand_host *host;
810 int cap, sector_size;
811
812 host = &pmecc_host;
813 nand_set_controller_data(nand, host);
814
815 nand->ecc.mode = NAND_ECC_HW;
816 nand->ecc.calculate = NULL;
817 nand->ecc.correct = NULL;
818 nand->ecc.hwctl = NULL;
819
820 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
821 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
822
823 #ifdef CONFIG_PMECC_CAP
824 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
825 #endif
826 #ifdef CONFIG_PMECC_SECTOR_SIZE
827 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
828 #endif
829 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
830 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
831 * from ONFI.
832 */
833 if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
834 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
835 cap, sector_size);
836 return -EINVAL;
837 }
838
839 if (cap > host->pmecc_corr_cap)
840 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
841 host->pmecc_corr_cap, cap);
842 if (sector_size < host->pmecc_sector_size)
843 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
844 host->pmecc_sector_size, sector_size);
845 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
846 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
847 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
848 #endif
849
850 cap = host->pmecc_corr_cap;
851 sector_size = host->pmecc_sector_size;
852
853 /* TODO: need check whether cap & sector_size is validate */
854 #if defined(NO_GALOIS_TABLE_IN_ROM)
855 /*
856 * As pmecc_rom_base is the begin of the gallois field table, So the
857 * index offset just set as 0.
858 */
859 host->pmecc_index_table_offset = 0;
860 #else
861 if (host->pmecc_sector_size == 512)
862 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
863 else
864 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
865 #endif
866
867 pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
868 cap, sector_size);
869
870 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
871 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
872 ATMEL_BASE_PMERRLOC;
873 #if defined(NO_GALOIS_TABLE_IN_ROM)
874 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
875 if (!pmecc_galois_table) {
876 dev_err(host->dev, "out of memory\n");
877 return -ENOMEM;
878 }
879
880 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
881 #else
882 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
883 #endif
884
885 /* ECC is calculated for the whole page (1 step) */
886 nand->ecc.size = mtd->writesize;
887
888 /* set ECC page size and oob layout */
889 switch (mtd->writesize) {
890 case 2048:
891 case 4096:
892 case 8192:
893 host->pmecc_degree = (sector_size == 512) ?
894 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
895 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
896 host->pmecc_sector_number = mtd->writesize / sector_size;
897 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
898 cap, sector_size);
899 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
900 host->pmecc_index_of = host->pmecc_rom_base +
901 host->pmecc_index_table_offset;
902
903 nand->ecc.steps = 1;
904 nand->ecc.bytes = host->pmecc_bytes_per_sector *
905 host->pmecc_sector_number;
906
907 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
908 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
909 MTD_MAX_ECCPOS_ENTRIES_LARGE);
910 return -EINVAL;
911 }
912
913 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
914 dev_err(host->dev, "No room for ECC bytes\n");
915 return -EINVAL;
916 }
917 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
918 mtd->oobsize,
919 nand->ecc.bytes);
920 nand->ecc.layout = &atmel_pmecc_oobinfo;
921 break;
922 case 512:
923 case 1024:
924 /* TODO */
925 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
926 default:
927 /* page size not handled by HW ECC */
928 /* switching back to soft ECC */
929 nand->ecc.mode = NAND_ECC_SOFT;
930 nand->ecc.read_page = NULL;
931 nand->ecc.postpad = 0;
932 nand->ecc.prepad = 0;
933 nand->ecc.bytes = 0;
934 return 0;
935 }
936
937 /* Allocate data for PMECC computation */
938 if (pmecc_data_alloc(host)) {
939 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
940 return -ENOMEM;
941 }
942
943 nand->options |= NAND_NO_SUBPAGE_WRITE;
944 nand->ecc.read_page = atmel_nand_pmecc_read_page;
945 nand->ecc.write_page = atmel_nand_pmecc_write_page;
946 nand->ecc.strength = cap;
947
948 /* Check the PMECC ip version */
949 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
950 dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
951
952 atmel_pmecc_core_init(mtd);
953
954 return 0;
955 }
956
957 #else
958
959 /* oob layout for large page size
960 * bad block info is on bytes 0 and 1
961 * the bytes have to be consecutives to avoid
962 * several NAND_CMD_RNDOUT during read
963 */
964 static struct nand_ecclayout atmel_oobinfo_large = {
965 .eccbytes = 4,
966 .eccpos = {60, 61, 62, 63},
967 .oobfree = {
968 {2, 58}
969 },
970 };
971
972 /* oob layout for small page size
973 * bad block info is on bytes 4 and 5
974 * the bytes have to be consecutives to avoid
975 * several NAND_CMD_RNDOUT during read
976 */
977 static struct nand_ecclayout atmel_oobinfo_small = {
978 .eccbytes = 4,
979 .eccpos = {0, 1, 2, 3},
980 .oobfree = {
981 {6, 10}
982 },
983 };
984
985 /*
986 * Calculate HW ECC
987 *
988 * function called after a write
989 *
990 * mtd: MTD block structure
991 * dat: raw data (unused)
992 * ecc_code: buffer for ECC
993 */
994 static int atmel_nand_calculate(struct mtd_info *mtd,
995 const u_char *dat, unsigned char *ecc_code)
996 {
997 unsigned int ecc_value;
998
999 /* get the first 2 ECC bytes */
1000 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1001
1002 ecc_code[0] = ecc_value & 0xFF;
1003 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1004
1005 /* get the last 2 ECC bytes */
1006 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1007
1008 ecc_code[2] = ecc_value & 0xFF;
1009 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1010
1011 return 0;
1012 }
1013
1014 /*
1015 * HW ECC read page function
1016 *
1017 * mtd: mtd info structure
1018 * chip: nand chip info structure
1019 * buf: buffer to store read data
1020 * oob_required: caller expects OOB data read to chip->oob_poi
1021 */
1022 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1023 uint8_t *buf, int oob_required, int page)
1024 {
1025 int eccsize = chip->ecc.size;
1026 int eccbytes = chip->ecc.bytes;
1027 uint32_t *eccpos = chip->ecc.layout->eccpos;
1028 uint8_t *p = buf;
1029 uint8_t *oob = chip->oob_poi;
1030 uint8_t *ecc_pos;
1031 int stat;
1032
1033 /* read the page */
1034 chip->read_buf(mtd, p, eccsize);
1035
1036 /* move to ECC position if needed */
1037 if (eccpos[0] != 0) {
1038 /* This only works on large pages
1039 * because the ECC controller waits for
1040 * NAND_CMD_RNDOUTSTART after the
1041 * NAND_CMD_RNDOUT.
1042 * anyway, for small pages, the eccpos[0] == 0
1043 */
1044 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1045 mtd->writesize + eccpos[0], -1);
1046 }
1047
1048 /* the ECC controller needs to read the ECC just after the data */
1049 ecc_pos = oob + eccpos[0];
1050 chip->read_buf(mtd, ecc_pos, eccbytes);
1051
1052 /* check if there's an error */
1053 stat = chip->ecc.correct(mtd, p, oob, NULL);
1054
1055 if (stat < 0)
1056 mtd->ecc_stats.failed++;
1057 else
1058 mtd->ecc_stats.corrected += stat;
1059
1060 /* get back to oob start (end of page) */
1061 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1062
1063 /* read the oob */
1064 chip->read_buf(mtd, oob, mtd->oobsize);
1065
1066 return 0;
1067 }
1068
1069 /*
1070 * HW ECC Correction
1071 *
1072 * function called after a read
1073 *
1074 * mtd: MTD block structure
1075 * dat: raw data read from the chip
1076 * read_ecc: ECC from the chip (unused)
1077 * isnull: unused
1078 *
1079 * Detect and correct a 1 bit error for a page
1080 */
1081 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1082 u_char *read_ecc, u_char *isnull)
1083 {
1084 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1085 unsigned int ecc_status;
1086 unsigned int ecc_word, ecc_bit;
1087
1088 /* get the status from the Status Register */
1089 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1090
1091 /* if there's no error */
1092 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1093 return 0;
1094
1095 /* get error bit offset (4 bits) */
1096 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1097 /* get word address (12 bits) */
1098 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1099 ecc_word >>= 4;
1100
1101 /* if there are multiple errors */
1102 if (ecc_status & ATMEL_ECC_MULERR) {
1103 /* check if it is a freshly erased block
1104 * (filled with 0xff) */
1105 if ((ecc_bit == ATMEL_ECC_BITADDR)
1106 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1107 /* the block has just been erased, return OK */
1108 return 0;
1109 }
1110 /* it doesn't seems to be a freshly
1111 * erased block.
1112 * We can't correct so many errors */
1113 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1114 " Unable to correct.\n");
1115 return -EBADMSG;
1116 }
1117
1118 /* if there's a single bit error : we can correct it */
1119 if (ecc_status & ATMEL_ECC_ECCERR) {
1120 /* there's nothing much to do here.
1121 * the bit error is on the ECC itself.
1122 */
1123 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1124 " Nothing to correct\n");
1125 return 0;
1126 }
1127
1128 dev_warn(host->dev, "atmel_nand : one bit error on data."
1129 " (word offset in the page :"
1130 " 0x%x bit offset : 0x%x)\n",
1131 ecc_word, ecc_bit);
1132 /* correct the error */
1133 if (nand_chip->options & NAND_BUSWIDTH_16) {
1134 /* 16 bits words */
1135 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1136 } else {
1137 /* 8 bits words */
1138 dat[ecc_word] ^= (1 << ecc_bit);
1139 }
1140 dev_warn(host->dev, "atmel_nand : error corrected\n");
1141 return 1;
1142 }
1143
1144 /*
1145 * Enable HW ECC : unused on most chips
1146 */
1147 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1148 {
1149 }
1150
1151 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1152 {
1153 nand->ecc.mode = NAND_ECC_HW;
1154 nand->ecc.calculate = atmel_nand_calculate;
1155 nand->ecc.correct = atmel_nand_correct;
1156 nand->ecc.hwctl = atmel_nand_hwctl;
1157 nand->ecc.read_page = atmel_nand_read_page;
1158 nand->ecc.bytes = 4;
1159 nand->ecc.strength = 4;
1160
1161 if (nand->ecc.mode == NAND_ECC_HW) {
1162 /* ECC is calculated for the whole page (1 step) */
1163 nand->ecc.size = mtd->writesize;
1164
1165 /* set ECC page size and oob layout */
1166 switch (mtd->writesize) {
1167 case 512:
1168 nand->ecc.layout = &atmel_oobinfo_small;
1169 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1170 ATMEL_ECC_PAGESIZE_528);
1171 break;
1172 case 1024:
1173 nand->ecc.layout = &atmel_oobinfo_large;
1174 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1175 ATMEL_ECC_PAGESIZE_1056);
1176 break;
1177 case 2048:
1178 nand->ecc.layout = &atmel_oobinfo_large;
1179 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1180 ATMEL_ECC_PAGESIZE_2112);
1181 break;
1182 case 4096:
1183 nand->ecc.layout = &atmel_oobinfo_large;
1184 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1185 ATMEL_ECC_PAGESIZE_4224);
1186 break;
1187 default:
1188 /* page size not handled by HW ECC */
1189 /* switching back to soft ECC */
1190 nand->ecc.mode = NAND_ECC_SOFT;
1191 nand->ecc.calculate = NULL;
1192 nand->ecc.correct = NULL;
1193 nand->ecc.hwctl = NULL;
1194 nand->ecc.read_page = NULL;
1195 nand->ecc.postpad = 0;
1196 nand->ecc.prepad = 0;
1197 nand->ecc.bytes = 0;
1198 break;
1199 }
1200 }
1201
1202 return 0;
1203 }
1204
1205 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1206
1207 #endif /* CONFIG_ATMEL_NAND_HWECC */
1208
1209 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1210 int cmd, unsigned int ctrl)
1211 {
1212 struct nand_chip *this = mtd_to_nand(mtd);
1213
1214 if (ctrl & NAND_CTRL_CHANGE) {
1215 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1216 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1217 | CONFIG_SYS_NAND_MASK_CLE);
1218
1219 if (ctrl & NAND_CLE)
1220 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1221 if (ctrl & NAND_ALE)
1222 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1223
1224 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1225 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1226 !(ctrl & NAND_NCE));
1227 #endif
1228 this->IO_ADDR_W = (void *) IO_ADDR_W;
1229 }
1230
1231 if (cmd != NAND_CMD_NONE)
1232 writeb(cmd, this->IO_ADDR_W);
1233 }
1234
1235 #ifdef CONFIG_SYS_NAND_READY_PIN
1236 static int at91_nand_ready(struct mtd_info *mtd)
1237 {
1238 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1239 }
1240 #endif
1241
1242 #ifdef CONFIG_SPL_BUILD
1243 /* The following code is for SPL */
1244 static struct mtd_info *mtd;
1245 static struct nand_chip nand_chip;
1246
1247 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1248 {
1249 struct nand_chip *this = mtd_to_nand(mtd);
1250 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1251 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1252 unsigned int ctrl) = this->cmd_ctrl;
1253
1254 while (!this->dev_ready(mtd))
1255 ;
1256
1257 if (cmd == NAND_CMD_READOOB) {
1258 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1259 cmd = NAND_CMD_READ0;
1260 }
1261
1262 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1263
1264 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1265 offs >>= 1;
1266
1267 hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1268 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1269 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1270 hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1271 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1272 hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1273 #endif
1274 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1275
1276 hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1277 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1278
1279 while (!this->dev_ready(mtd))
1280 ;
1281
1282 return 0;
1283 }
1284
1285 static int nand_is_bad_block(int block)
1286 {
1287 struct nand_chip *this = mtd_to_nand(mtd);
1288
1289 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1290
1291 if (this->options & NAND_BUSWIDTH_16) {
1292 if (readw(this->IO_ADDR_R) != 0xffff)
1293 return 1;
1294 } else {
1295 if (readb(this->IO_ADDR_R) != 0xff)
1296 return 1;
1297 }
1298
1299 return 0;
1300 }
1301
1302 #ifdef CONFIG_SPL_NAND_ECC
1303 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1304 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1305 CONFIG_SYS_NAND_ECCSIZE)
1306 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1307
1308 static int nand_read_page(int block, int page, void *dst)
1309 {
1310 struct nand_chip *this = mtd_to_nand(mtd);
1311 u_char ecc_calc[ECCTOTAL];
1312 u_char ecc_code[ECCTOTAL];
1313 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1314 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1315 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1316 int eccsteps = ECCSTEPS;
1317 int i;
1318 uint8_t *p = dst;
1319 nand_command(block, page, 0, NAND_CMD_READ0);
1320
1321 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1322 if (this->ecc.mode != NAND_ECC_SOFT)
1323 this->ecc.hwctl(mtd, NAND_ECC_READ);
1324 this->read_buf(mtd, p, eccsize);
1325 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1326 }
1327 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1328
1329 for (i = 0; i < ECCTOTAL; i++)
1330 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1331
1332 eccsteps = ECCSTEPS;
1333 p = dst;
1334
1335 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1336 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1337
1338 return 0;
1339 }
1340
1341 int spl_nand_erase_one(int block, int page)
1342 {
1343 struct nand_chip *this = mtd_to_nand(mtd);
1344 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1345 unsigned int ctrl) = this->cmd_ctrl;
1346 int page_addr;
1347
1348 if (nand_chip.select_chip)
1349 nand_chip.select_chip(mtd, 0);
1350
1351 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1352 hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1353 /* Row address */
1354 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1355 hwctrl(mtd, ((page_addr >> 8) & 0xff),
1356 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1357 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1358 /* One more address cycle for devices > 128MiB */
1359 hwctrl(mtd, (page_addr >> 16) & 0x0f,
1360 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1361 #endif
1362 hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1363
1364 while (!this->dev_ready(mtd))
1365 ;
1366
1367 nand_deselect();
1368
1369 return 0;
1370 }
1371 #else
1372 static int nand_read_page(int block, int page, void *dst)
1373 {
1374 struct nand_chip *this = mtd_to_nand(mtd);
1375
1376 nand_command(block, page, 0, NAND_CMD_READ0);
1377 atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1378
1379 return 0;
1380 }
1381 #endif /* CONFIG_SPL_NAND_ECC */
1382
1383 int at91_nand_wait_ready(struct mtd_info *mtd)
1384 {
1385 struct nand_chip *this = mtd_to_nand(mtd);
1386
1387 udelay(this->chip_delay);
1388
1389 return 1;
1390 }
1391
1392 int board_nand_init(struct nand_chip *nand)
1393 {
1394 int ret = 0;
1395
1396 nand->ecc.mode = NAND_ECC_SOFT;
1397 #ifdef CONFIG_SYS_NAND_DBW_16
1398 nand->options = NAND_BUSWIDTH_16;
1399 nand->read_buf = nand_read_buf16;
1400 #else
1401 nand->read_buf = nand_read_buf;
1402 #endif
1403 nand->cmd_ctrl = at91_nand_hwcontrol;
1404 #ifdef CONFIG_SYS_NAND_READY_PIN
1405 nand->dev_ready = at91_nand_ready;
1406 #else
1407 nand->dev_ready = at91_nand_wait_ready;
1408 #endif
1409 nand->chip_delay = 20;
1410 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1411 nand->bbt_options |= NAND_BBT_USE_FLASH;
1412 #endif
1413
1414 #ifdef CONFIG_ATMEL_NAND_HWECC
1415 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1416 ret = atmel_pmecc_nand_init_params(nand, mtd);
1417 #endif
1418 #endif
1419
1420 return ret;
1421 }
1422
1423 void nand_init(void)
1424 {
1425 mtd = nand_to_mtd(&nand_chip);
1426 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1427 mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1428 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1429 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1430 board_nand_init(&nand_chip);
1431
1432 #ifdef CONFIG_SPL_NAND_ECC
1433 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1434 nand_chip.ecc.calculate = nand_calculate_ecc;
1435 nand_chip.ecc.correct = nand_correct_data;
1436 }
1437 #endif
1438
1439 if (nand_chip.select_chip)
1440 nand_chip.select_chip(mtd, 0);
1441 }
1442
1443 void nand_deselect(void)
1444 {
1445 if (nand_chip.select_chip)
1446 nand_chip.select_chip(mtd, -1);
1447 }
1448
1449 #include "nand_spl_loaders.c"
1450
1451 #else
1452
1453 #ifndef CONFIG_SYS_NAND_BASE_LIST
1454 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1455 #endif
1456 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1457 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1458
1459 int atmel_nand_chip_init(int devnum, ulong base_addr)
1460 {
1461 int ret;
1462 struct nand_chip *nand = &nand_chip[devnum];
1463 struct mtd_info *mtd = nand_to_mtd(nand);
1464
1465 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1466
1467 #ifdef CONFIG_NAND_ECC_BCH
1468 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1469 #else
1470 nand->ecc.mode = NAND_ECC_SOFT;
1471 #endif
1472 #ifdef CONFIG_SYS_NAND_DBW_16
1473 nand->options = NAND_BUSWIDTH_16;
1474 #endif
1475 nand->cmd_ctrl = at91_nand_hwcontrol;
1476 #ifdef CONFIG_SYS_NAND_READY_PIN
1477 nand->dev_ready = at91_nand_ready;
1478 #endif
1479 nand->chip_delay = 75;
1480 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1481 nand->bbt_options |= NAND_BBT_USE_FLASH;
1482 #endif
1483
1484 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1485 if (ret)
1486 return ret;
1487
1488 #ifdef CONFIG_ATMEL_NAND_HWECC
1489 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1490 ret = atmel_pmecc_nand_init_params(nand, mtd);
1491 #else
1492 ret = atmel_hwecc_nand_init_param(nand, mtd);
1493 #endif
1494 if (ret)
1495 return ret;
1496 #endif
1497
1498 ret = nand_scan_tail(mtd);
1499 if (!ret)
1500 nand_register(devnum, mtd);
1501
1502 return ret;
1503 }
1504
1505 void board_nand_init(void)
1506 {
1507 int i;
1508 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1509 if (atmel_nand_chip_init(i, base_addr[i]))
1510 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1511 i);
1512 }
1513 #endif /* CONFIG_SPL_BUILD */
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