1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
7 #include <linux/version.h>
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/platform_device.h>
13 #include <linux/err.h>
14 #include <linux/completion.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/ioport.h>
19 #include <linux/bug.h>
20 #include <linux/kernel.h>
21 #include <linux/bitops.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/list.h>
30 #include <linux/log2.h>
35 * This flag controls if WP stays on between erase/write commands to mitigate
36 * flash corruption due to power glitches. Values:
37 * 0: NAND_WP is not used or not available
38 * 1: NAND_WP is set by default, cleared for erase/write operations
39 * 2: NAND_WP is always cleared
42 module_param(wp_on
, int, 0444);
44 /***********************************************************************
46 ***********************************************************************/
48 #define DRV_NAME "brcmnand"
51 #define CMD_PAGE_READ 0x01
52 #define CMD_SPARE_AREA_READ 0x02
53 #define CMD_STATUS_READ 0x03
54 #define CMD_PROGRAM_PAGE 0x04
55 #define CMD_PROGRAM_SPARE_AREA 0x05
56 #define CMD_COPY_BACK 0x06
57 #define CMD_DEVICE_ID_READ 0x07
58 #define CMD_BLOCK_ERASE 0x08
59 #define CMD_FLASH_RESET 0x09
60 #define CMD_BLOCKS_LOCK 0x0a
61 #define CMD_BLOCKS_LOCK_DOWN 0x0b
62 #define CMD_BLOCKS_UNLOCK 0x0c
63 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
64 #define CMD_PARAMETER_READ 0x0e
65 #define CMD_PARAMETER_CHANGE_COL 0x0f
66 #define CMD_LOW_LEVEL_OP 0x10
68 struct brcm_nand_dma_desc
{
83 /* Bitfields for brcm_nand_dma_desc::status_valid */
84 #define FLASH_DMA_ECC_ERROR (1 << 8)
85 #define FLASH_DMA_CORR_ERROR (1 << 9)
87 /* Bitfields for DMA_MODE */
88 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
89 #define FLASH_DMA_MODE_MODE BIT(0) /* link list */
90 #define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \
93 /* 512B flash cache in the NAND controller HW */
96 #define FC_WORDS (FC_BYTES >> 2)
98 #define BRCMNAND_MIN_PAGESIZE 512
99 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
100 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
102 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
103 #define NAND_POLL_STATUS_TIMEOUT_MS 100
105 #define EDU_CMD_WRITE 0x00
106 #define EDU_CMD_READ 0x01
107 #define EDU_STATUS_ACTIVE BIT(0)
108 #define EDU_ERR_STATUS_ERRACK BIT(0)
109 #define EDU_DONE_MASK GENMASK(1, 0)
111 #define EDU_CONFIG_MODE_NAND BIT(0)
112 #define EDU_CONFIG_SWAP_BYTE BIT(1)
113 #ifdef CONFIG_CPU_BIG_ENDIAN
114 #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE
116 #define EDU_CONFIG_SWAP_CFG 0
132 static const u16 edu_regs
[] = {
134 [EDU_DRAM_ADDR
] = 0x04,
135 [EDU_EXT_ADDR
] = 0x08,
141 [EDU_ERR_STATUS
] = 0x20,
144 /* flash_dma registers */
146 FLASH_DMA_REVISION
= 0,
147 FLASH_DMA_FIRST_DESC
,
148 FLASH_DMA_FIRST_DESC_EXT
,
152 FLASH_DMA_INTERRUPT_DESC
,
153 FLASH_DMA_INTERRUPT_DESC_EXT
,
154 FLASH_DMA_ERROR_STATUS
,
155 FLASH_DMA_CURRENT_DESC
,
156 FLASH_DMA_CURRENT_DESC_EXT
,
159 /* flash_dma registers v0*/
160 static const u16 flash_dma_regs_v0
[] = {
161 [FLASH_DMA_REVISION
] = 0x00,
162 [FLASH_DMA_FIRST_DESC
] = 0x04,
163 [FLASH_DMA_CTRL
] = 0x08,
164 [FLASH_DMA_MODE
] = 0x0c,
165 [FLASH_DMA_STATUS
] = 0x10,
166 [FLASH_DMA_INTERRUPT_DESC
] = 0x14,
167 [FLASH_DMA_ERROR_STATUS
] = 0x18,
168 [FLASH_DMA_CURRENT_DESC
] = 0x1c,
171 /* flash_dma registers v1*/
172 static const u16 flash_dma_regs_v1
[] = {
173 [FLASH_DMA_REVISION
] = 0x00,
174 [FLASH_DMA_FIRST_DESC
] = 0x04,
175 [FLASH_DMA_FIRST_DESC_EXT
] = 0x08,
176 [FLASH_DMA_CTRL
] = 0x0c,
177 [FLASH_DMA_MODE
] = 0x10,
178 [FLASH_DMA_STATUS
] = 0x14,
179 [FLASH_DMA_INTERRUPT_DESC
] = 0x18,
180 [FLASH_DMA_INTERRUPT_DESC_EXT
] = 0x1c,
181 [FLASH_DMA_ERROR_STATUS
] = 0x20,
182 [FLASH_DMA_CURRENT_DESC
] = 0x24,
183 [FLASH_DMA_CURRENT_DESC_EXT
] = 0x28,
186 /* flash_dma registers v4 */
187 static const u16 flash_dma_regs_v4
[] = {
188 [FLASH_DMA_REVISION
] = 0x00,
189 [FLASH_DMA_FIRST_DESC
] = 0x08,
190 [FLASH_DMA_FIRST_DESC_EXT
] = 0x0c,
191 [FLASH_DMA_CTRL
] = 0x10,
192 [FLASH_DMA_MODE
] = 0x14,
193 [FLASH_DMA_STATUS
] = 0x18,
194 [FLASH_DMA_INTERRUPT_DESC
] = 0x20,
195 [FLASH_DMA_INTERRUPT_DESC_EXT
] = 0x24,
196 [FLASH_DMA_ERROR_STATUS
] = 0x28,
197 [FLASH_DMA_CURRENT_DESC
] = 0x30,
198 [FLASH_DMA_CURRENT_DESC_EXT
] = 0x34,
201 /* Controller feature flags */
203 BRCMNAND_HAS_1K_SECTORS
= BIT(0),
204 BRCMNAND_HAS_PREFETCH
= BIT(1),
205 BRCMNAND_HAS_CACHE_MODE
= BIT(2),
206 BRCMNAND_HAS_WP
= BIT(3),
209 struct brcmnand_host
;
211 struct brcmnand_controller
{
213 struct nand_controller controller
;
214 void __iomem
*nand_base
;
215 void __iomem
*nand_fc
; /* flash cache */
216 void __iomem
*flash_dma_base
;
218 unsigned int dma_irq
;
221 /* Some SoCs provide custom interrupt status register(s) */
222 struct brcmnand_soc
*soc
;
224 /* Some SoCs have a gateable clock for the controller */
230 struct completion done
;
231 struct completion dma_done
;
232 struct completion edu_done
;
234 /* List of NAND hosts (one for each chip-select) */
235 struct list_head host_list
;
237 /* EDU info, per-transaction */
238 const u16
*edu_offsets
;
239 void __iomem
*edu_base
;
248 const u16
*flash_dma_offsets
;
249 struct brcm_nand_dma_desc
*dma_desc
;
252 int (*dma_trans
)(struct brcmnand_host
*host
, u64 addr
, u32
*buf
,
253 u32 len
, u8 dma_cmd
);
255 /* in-memory cache of the FLASH_CACHE, used only for some commands */
256 u8 flash_cache
[FC_BYTES
];
258 /* Controller revision details */
259 const u16
*reg_offsets
;
260 unsigned int reg_spacing
; /* between CS1, CS2, ... regs */
261 const u8
*cs_offsets
; /* within each chip-select */
262 const u8
*cs0_offsets
; /* within CS0, if different */
263 unsigned int max_block_size
;
264 const unsigned int *block_sizes
;
265 unsigned int max_page_size
;
266 const unsigned int *page_sizes
;
267 unsigned int max_oob
;
270 /* for low-power standby/resume only */
271 u32 nand_cs_nand_select
;
272 u32 nand_cs_nand_xor
;
273 u32 corr_stat_threshold
;
279 struct brcmnand_cfg
{
281 unsigned int block_size
;
282 unsigned int page_size
;
283 unsigned int spare_area_size
;
284 unsigned int device_width
;
285 unsigned int col_adr_bytes
;
286 unsigned int blk_adr_bytes
;
287 unsigned int ful_adr_bytes
;
288 unsigned int sector_size_1k
;
289 unsigned int ecc_level
;
290 /* use for low-power standby/resume only */
298 struct brcmnand_host
{
299 struct list_head node
;
301 struct nand_chip chip
;
302 struct platform_device
*pdev
;
305 unsigned int last_cmd
;
306 unsigned int last_byte
;
308 struct brcmnand_cfg hwcfg
;
309 struct brcmnand_controller
*ctrl
;
313 BRCMNAND_CMD_START
= 0,
314 BRCMNAND_CMD_EXT_ADDRESS
,
315 BRCMNAND_CMD_ADDRESS
,
316 BRCMNAND_INTFC_STATUS
,
321 BRCMNAND_CS1_BASE
, /* CS1 regs, if non-contiguous */
322 BRCMNAND_CORR_THRESHOLD
,
323 BRCMNAND_CORR_THRESHOLD_EXT
,
324 BRCMNAND_UNCORR_COUNT
,
326 BRCMNAND_CORR_EXT_ADDR
,
328 BRCMNAND_UNCORR_EXT_ADDR
,
329 BRCMNAND_UNCORR_ADDR
,
334 BRCMNAND_OOB_READ_BASE
,
335 BRCMNAND_OOB_READ_10_BASE
, /* offset 0x10, if non-contiguous */
336 BRCMNAND_OOB_WRITE_BASE
,
337 BRCMNAND_OOB_WRITE_10_BASE
, /* offset 0x10, if non-contiguous */
342 static const u16 brcmnand_regs_v40
[] = {
343 [BRCMNAND_CMD_START
] = 0x04,
344 [BRCMNAND_CMD_EXT_ADDRESS
] = 0x08,
345 [BRCMNAND_CMD_ADDRESS
] = 0x0c,
346 [BRCMNAND_INTFC_STATUS
] = 0x6c,
347 [BRCMNAND_CS_SELECT
] = 0x14,
348 [BRCMNAND_CS_XOR
] = 0x18,
349 [BRCMNAND_LL_OP
] = 0x178,
350 [BRCMNAND_CS0_BASE
] = 0x40,
351 [BRCMNAND_CS1_BASE
] = 0xd0,
352 [BRCMNAND_CORR_THRESHOLD
] = 0x84,
353 [BRCMNAND_CORR_THRESHOLD_EXT
] = 0,
354 [BRCMNAND_UNCORR_COUNT
] = 0,
355 [BRCMNAND_CORR_COUNT
] = 0,
356 [BRCMNAND_CORR_EXT_ADDR
] = 0x70,
357 [BRCMNAND_CORR_ADDR
] = 0x74,
358 [BRCMNAND_UNCORR_EXT_ADDR
] = 0x78,
359 [BRCMNAND_UNCORR_ADDR
] = 0x7c,
360 [BRCMNAND_SEMAPHORE
] = 0x58,
361 [BRCMNAND_ID
] = 0x60,
362 [BRCMNAND_ID_EXT
] = 0x64,
363 [BRCMNAND_LL_RDATA
] = 0x17c,
364 [BRCMNAND_OOB_READ_BASE
] = 0x20,
365 [BRCMNAND_OOB_READ_10_BASE
] = 0x130,
366 [BRCMNAND_OOB_WRITE_BASE
] = 0x30,
367 [BRCMNAND_OOB_WRITE_10_BASE
] = 0,
368 [BRCMNAND_FC_BASE
] = 0x200,
372 static const u16 brcmnand_regs_v50
[] = {
373 [BRCMNAND_CMD_START
] = 0x04,
374 [BRCMNAND_CMD_EXT_ADDRESS
] = 0x08,
375 [BRCMNAND_CMD_ADDRESS
] = 0x0c,
376 [BRCMNAND_INTFC_STATUS
] = 0x6c,
377 [BRCMNAND_CS_SELECT
] = 0x14,
378 [BRCMNAND_CS_XOR
] = 0x18,
379 [BRCMNAND_LL_OP
] = 0x178,
380 [BRCMNAND_CS0_BASE
] = 0x40,
381 [BRCMNAND_CS1_BASE
] = 0xd0,
382 [BRCMNAND_CORR_THRESHOLD
] = 0x84,
383 [BRCMNAND_CORR_THRESHOLD_EXT
] = 0,
384 [BRCMNAND_UNCORR_COUNT
] = 0,
385 [BRCMNAND_CORR_COUNT
] = 0,
386 [BRCMNAND_CORR_EXT_ADDR
] = 0x70,
387 [BRCMNAND_CORR_ADDR
] = 0x74,
388 [BRCMNAND_UNCORR_EXT_ADDR
] = 0x78,
389 [BRCMNAND_UNCORR_ADDR
] = 0x7c,
390 [BRCMNAND_SEMAPHORE
] = 0x58,
391 [BRCMNAND_ID
] = 0x60,
392 [BRCMNAND_ID_EXT
] = 0x64,
393 [BRCMNAND_LL_RDATA
] = 0x17c,
394 [BRCMNAND_OOB_READ_BASE
] = 0x20,
395 [BRCMNAND_OOB_READ_10_BASE
] = 0x130,
396 [BRCMNAND_OOB_WRITE_BASE
] = 0x30,
397 [BRCMNAND_OOB_WRITE_10_BASE
] = 0x140,
398 [BRCMNAND_FC_BASE
] = 0x200,
401 /* BRCMNAND v6.0 - v7.1 */
402 static const u16 brcmnand_regs_v60
[] = {
403 [BRCMNAND_CMD_START
] = 0x04,
404 [BRCMNAND_CMD_EXT_ADDRESS
] = 0x08,
405 [BRCMNAND_CMD_ADDRESS
] = 0x0c,
406 [BRCMNAND_INTFC_STATUS
] = 0x14,
407 [BRCMNAND_CS_SELECT
] = 0x18,
408 [BRCMNAND_CS_XOR
] = 0x1c,
409 [BRCMNAND_LL_OP
] = 0x20,
410 [BRCMNAND_CS0_BASE
] = 0x50,
411 [BRCMNAND_CS1_BASE
] = 0,
412 [BRCMNAND_CORR_THRESHOLD
] = 0xc0,
413 [BRCMNAND_CORR_THRESHOLD_EXT
] = 0xc4,
414 [BRCMNAND_UNCORR_COUNT
] = 0xfc,
415 [BRCMNAND_CORR_COUNT
] = 0x100,
416 [BRCMNAND_CORR_EXT_ADDR
] = 0x10c,
417 [BRCMNAND_CORR_ADDR
] = 0x110,
418 [BRCMNAND_UNCORR_EXT_ADDR
] = 0x114,
419 [BRCMNAND_UNCORR_ADDR
] = 0x118,
420 [BRCMNAND_SEMAPHORE
] = 0x150,
421 [BRCMNAND_ID
] = 0x194,
422 [BRCMNAND_ID_EXT
] = 0x198,
423 [BRCMNAND_LL_RDATA
] = 0x19c,
424 [BRCMNAND_OOB_READ_BASE
] = 0x200,
425 [BRCMNAND_OOB_READ_10_BASE
] = 0,
426 [BRCMNAND_OOB_WRITE_BASE
] = 0x280,
427 [BRCMNAND_OOB_WRITE_10_BASE
] = 0,
428 [BRCMNAND_FC_BASE
] = 0x400,
432 static const u16 brcmnand_regs_v71
[] = {
433 [BRCMNAND_CMD_START
] = 0x04,
434 [BRCMNAND_CMD_EXT_ADDRESS
] = 0x08,
435 [BRCMNAND_CMD_ADDRESS
] = 0x0c,
436 [BRCMNAND_INTFC_STATUS
] = 0x14,
437 [BRCMNAND_CS_SELECT
] = 0x18,
438 [BRCMNAND_CS_XOR
] = 0x1c,
439 [BRCMNAND_LL_OP
] = 0x20,
440 [BRCMNAND_CS0_BASE
] = 0x50,
441 [BRCMNAND_CS1_BASE
] = 0,
442 [BRCMNAND_CORR_THRESHOLD
] = 0xdc,
443 [BRCMNAND_CORR_THRESHOLD_EXT
] = 0xe0,
444 [BRCMNAND_UNCORR_COUNT
] = 0xfc,
445 [BRCMNAND_CORR_COUNT
] = 0x100,
446 [BRCMNAND_CORR_EXT_ADDR
] = 0x10c,
447 [BRCMNAND_CORR_ADDR
] = 0x110,
448 [BRCMNAND_UNCORR_EXT_ADDR
] = 0x114,
449 [BRCMNAND_UNCORR_ADDR
] = 0x118,
450 [BRCMNAND_SEMAPHORE
] = 0x150,
451 [BRCMNAND_ID
] = 0x194,
452 [BRCMNAND_ID_EXT
] = 0x198,
453 [BRCMNAND_LL_RDATA
] = 0x19c,
454 [BRCMNAND_OOB_READ_BASE
] = 0x200,
455 [BRCMNAND_OOB_READ_10_BASE
] = 0,
456 [BRCMNAND_OOB_WRITE_BASE
] = 0x280,
457 [BRCMNAND_OOB_WRITE_10_BASE
] = 0,
458 [BRCMNAND_FC_BASE
] = 0x400,
462 static const u16 brcmnand_regs_v72
[] = {
463 [BRCMNAND_CMD_START
] = 0x04,
464 [BRCMNAND_CMD_EXT_ADDRESS
] = 0x08,
465 [BRCMNAND_CMD_ADDRESS
] = 0x0c,
466 [BRCMNAND_INTFC_STATUS
] = 0x14,
467 [BRCMNAND_CS_SELECT
] = 0x18,
468 [BRCMNAND_CS_XOR
] = 0x1c,
469 [BRCMNAND_LL_OP
] = 0x20,
470 [BRCMNAND_CS0_BASE
] = 0x50,
471 [BRCMNAND_CS1_BASE
] = 0,
472 [BRCMNAND_CORR_THRESHOLD
] = 0xdc,
473 [BRCMNAND_CORR_THRESHOLD_EXT
] = 0xe0,
474 [BRCMNAND_UNCORR_COUNT
] = 0xfc,
475 [BRCMNAND_CORR_COUNT
] = 0x100,
476 [BRCMNAND_CORR_EXT_ADDR
] = 0x10c,
477 [BRCMNAND_CORR_ADDR
] = 0x110,
478 [BRCMNAND_UNCORR_EXT_ADDR
] = 0x114,
479 [BRCMNAND_UNCORR_ADDR
] = 0x118,
480 [BRCMNAND_SEMAPHORE
] = 0x150,
481 [BRCMNAND_ID
] = 0x194,
482 [BRCMNAND_ID_EXT
] = 0x198,
483 [BRCMNAND_LL_RDATA
] = 0x19c,
484 [BRCMNAND_OOB_READ_BASE
] = 0x200,
485 [BRCMNAND_OOB_READ_10_BASE
] = 0,
486 [BRCMNAND_OOB_WRITE_BASE
] = 0x400,
487 [BRCMNAND_OOB_WRITE_10_BASE
] = 0,
488 [BRCMNAND_FC_BASE
] = 0x600,
491 enum brcmnand_cs_reg
{
492 BRCMNAND_CS_CFG_EXT
= 0,
494 BRCMNAND_CS_ACC_CONTROL
,
499 /* Per chip-select offsets for v7.1 */
500 static const u8 brcmnand_cs_offsets_v71
[] = {
501 [BRCMNAND_CS_ACC_CONTROL
] = 0x00,
502 [BRCMNAND_CS_CFG_EXT
] = 0x04,
503 [BRCMNAND_CS_CFG
] = 0x08,
504 [BRCMNAND_CS_TIMING1
] = 0x0c,
505 [BRCMNAND_CS_TIMING2
] = 0x10,
508 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
509 static const u8 brcmnand_cs_offsets
[] = {
510 [BRCMNAND_CS_ACC_CONTROL
] = 0x00,
511 [BRCMNAND_CS_CFG_EXT
] = 0x04,
512 [BRCMNAND_CS_CFG
] = 0x04,
513 [BRCMNAND_CS_TIMING1
] = 0x08,
514 [BRCMNAND_CS_TIMING2
] = 0x0c,
517 /* Per chip-select offset for <= v5.0 on CS0 only */
518 static const u8 brcmnand_cs_offsets_cs0
[] = {
519 [BRCMNAND_CS_ACC_CONTROL
] = 0x00,
520 [BRCMNAND_CS_CFG_EXT
] = 0x08,
521 [BRCMNAND_CS_CFG
] = 0x08,
522 [BRCMNAND_CS_TIMING1
] = 0x10,
523 [BRCMNAND_CS_TIMING2
] = 0x14,
527 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
528 * one config register, but once the bitfields overflowed, newer controllers
529 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
532 CFG_BLK_ADR_BYTES_SHIFT
= 8,
533 CFG_COL_ADR_BYTES_SHIFT
= 12,
534 CFG_FUL_ADR_BYTES_SHIFT
= 16,
535 CFG_BUS_WIDTH_SHIFT
= 23,
536 CFG_BUS_WIDTH
= BIT(CFG_BUS_WIDTH_SHIFT
),
537 CFG_DEVICE_SIZE_SHIFT
= 24,
539 /* Only for pre-v7.1 (with no CFG_EXT register) */
540 CFG_PAGE_SIZE_SHIFT
= 20,
541 CFG_BLK_SIZE_SHIFT
= 28,
543 /* Only for v7.1+ (with CFG_EXT register) */
544 CFG_EXT_PAGE_SIZE_SHIFT
= 0,
545 CFG_EXT_BLK_SIZE_SHIFT
= 4,
548 /* BRCMNAND_INTFC_STATUS */
550 INTFC_FLASH_STATUS
= GENMASK(7, 0),
552 INTFC_ERASED
= BIT(27),
553 INTFC_OOB_VALID
= BIT(28),
554 INTFC_CACHE_VALID
= BIT(29),
555 INTFC_FLASH_READY
= BIT(30),
556 INTFC_CTLR_READY
= BIT(31),
559 static inline u32
nand_readreg(struct brcmnand_controller
*ctrl
, u32 offs
)
561 return brcmnand_readl(ctrl
->nand_base
+ offs
);
564 static inline void nand_writereg(struct brcmnand_controller
*ctrl
, u32 offs
,
567 brcmnand_writel(val
, ctrl
->nand_base
+ offs
);
570 static int brcmnand_revision_init(struct brcmnand_controller
*ctrl
)
572 static const unsigned int block_sizes_v6
[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
573 static const unsigned int block_sizes_v4
[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
574 static const unsigned int page_sizes
[] = { 512, 2048, 4096, 8192, 0 };
576 ctrl
->nand_version
= nand_readreg(ctrl
, 0) & 0xffff;
578 /* Only support v4.0+? */
579 if (ctrl
->nand_version
< 0x0400) {
580 dev_err(ctrl
->dev
, "version %#x not supported\n",
585 /* Register offsets */
586 if (ctrl
->nand_version
>= 0x0702)
587 ctrl
->reg_offsets
= brcmnand_regs_v72
;
588 else if (ctrl
->nand_version
== 0x0701)
589 ctrl
->reg_offsets
= brcmnand_regs_v71
;
590 else if (ctrl
->nand_version
>= 0x0600)
591 ctrl
->reg_offsets
= brcmnand_regs_v60
;
592 else if (ctrl
->nand_version
>= 0x0500)
593 ctrl
->reg_offsets
= brcmnand_regs_v50
;
594 else if (ctrl
->nand_version
>= 0x0400)
595 ctrl
->reg_offsets
= brcmnand_regs_v40
;
597 /* Chip-select stride */
598 if (ctrl
->nand_version
>= 0x0701)
599 ctrl
->reg_spacing
= 0x14;
601 ctrl
->reg_spacing
= 0x10;
603 /* Per chip-select registers */
604 if (ctrl
->nand_version
>= 0x0701) {
605 ctrl
->cs_offsets
= brcmnand_cs_offsets_v71
;
607 ctrl
->cs_offsets
= brcmnand_cs_offsets
;
609 /* v5.0 and earlier has a different CS0 offset layout */
610 if (ctrl
->nand_version
<= 0x0500)
611 ctrl
->cs0_offsets
= brcmnand_cs_offsets_cs0
;
614 /* Page / block sizes */
615 if (ctrl
->nand_version
>= 0x0701) {
616 /* >= v7.1 use nice power-of-2 values! */
617 ctrl
->max_page_size
= 16 * 1024;
618 ctrl
->max_block_size
= 2 * 1024 * 1024;
620 ctrl
->page_sizes
= page_sizes
;
621 if (ctrl
->nand_version
>= 0x0600)
622 ctrl
->block_sizes
= block_sizes_v6
;
624 ctrl
->block_sizes
= block_sizes_v4
;
626 if (ctrl
->nand_version
< 0x0400) {
627 ctrl
->max_page_size
= 4096;
628 ctrl
->max_block_size
= 512 * 1024;
632 /* Maximum spare area sector size (per 512B) */
633 if (ctrl
->nand_version
== 0x0702)
635 else if (ctrl
->nand_version
>= 0x0600)
637 else if (ctrl
->nand_version
>= 0x0500)
642 /* v6.0 and newer (except v6.1) have prefetch support */
643 if (ctrl
->nand_version
>= 0x0600 && ctrl
->nand_version
!= 0x0601)
644 ctrl
->features
|= BRCMNAND_HAS_PREFETCH
;
647 * v6.x has cache mode, but it's implemented differently. Ignore it for
650 if (ctrl
->nand_version
>= 0x0700)
651 ctrl
->features
|= BRCMNAND_HAS_CACHE_MODE
;
653 if (ctrl
->nand_version
>= 0x0500)
654 ctrl
->features
|= BRCMNAND_HAS_1K_SECTORS
;
656 if (ctrl
->nand_version
>= 0x0700)
657 ctrl
->features
|= BRCMNAND_HAS_WP
;
658 else if (of_property_read_bool(ctrl
->dev
->of_node
, "brcm,nand-has-wp"))
659 ctrl
->features
|= BRCMNAND_HAS_WP
;
664 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller
*ctrl
)
666 /* flash_dma register offsets */
667 if (ctrl
->nand_version
>= 0x0703)
668 ctrl
->flash_dma_offsets
= flash_dma_regs_v4
;
669 else if (ctrl
->nand_version
== 0x0602)
670 ctrl
->flash_dma_offsets
= flash_dma_regs_v0
;
672 ctrl
->flash_dma_offsets
= flash_dma_regs_v1
;
675 static inline u32
brcmnand_read_reg(struct brcmnand_controller
*ctrl
,
676 enum brcmnand_reg reg
)
678 u16 offs
= ctrl
->reg_offsets
[reg
];
681 return nand_readreg(ctrl
, offs
);
686 static inline void brcmnand_write_reg(struct brcmnand_controller
*ctrl
,
687 enum brcmnand_reg reg
, u32 val
)
689 u16 offs
= ctrl
->reg_offsets
[reg
];
692 nand_writereg(ctrl
, offs
, val
);
695 static inline void brcmnand_rmw_reg(struct brcmnand_controller
*ctrl
,
696 enum brcmnand_reg reg
, u32 mask
, unsigned
699 u32 tmp
= brcmnand_read_reg(ctrl
, reg
);
703 brcmnand_write_reg(ctrl
, reg
, tmp
);
706 static inline u32
brcmnand_read_fc(struct brcmnand_controller
*ctrl
, int word
)
708 return __raw_readl(ctrl
->nand_fc
+ word
* 4);
711 static inline void brcmnand_write_fc(struct brcmnand_controller
*ctrl
,
714 __raw_writel(val
, ctrl
->nand_fc
+ word
* 4);
717 static inline void edu_writel(struct brcmnand_controller
*ctrl
,
718 enum edu_reg reg
, u32 val
)
720 u16 offs
= ctrl
->edu_offsets
[reg
];
722 brcmnand_writel(val
, ctrl
->edu_base
+ offs
);
725 static inline u32
edu_readl(struct brcmnand_controller
*ctrl
,
728 u16 offs
= ctrl
->edu_offsets
[reg
];
730 return brcmnand_readl(ctrl
->edu_base
+ offs
);
733 static void brcmnand_clear_ecc_addr(struct brcmnand_controller
*ctrl
)
736 /* Clear error addresses */
737 brcmnand_write_reg(ctrl
, BRCMNAND_UNCORR_ADDR
, 0);
738 brcmnand_write_reg(ctrl
, BRCMNAND_CORR_ADDR
, 0);
739 brcmnand_write_reg(ctrl
, BRCMNAND_UNCORR_EXT_ADDR
, 0);
740 brcmnand_write_reg(ctrl
, BRCMNAND_CORR_EXT_ADDR
, 0);
743 static u64
brcmnand_get_uncorrecc_addr(struct brcmnand_controller
*ctrl
)
747 err_addr
= brcmnand_read_reg(ctrl
, BRCMNAND_UNCORR_ADDR
);
748 err_addr
|= ((u64
)(brcmnand_read_reg(ctrl
,
749 BRCMNAND_UNCORR_EXT_ADDR
)
755 static u64
brcmnand_get_correcc_addr(struct brcmnand_controller
*ctrl
)
759 err_addr
= brcmnand_read_reg(ctrl
, BRCMNAND_CORR_ADDR
);
760 err_addr
|= ((u64
)(brcmnand_read_reg(ctrl
,
761 BRCMNAND_CORR_EXT_ADDR
)
767 static void brcmnand_set_cmd_addr(struct mtd_info
*mtd
, u64 addr
)
769 struct nand_chip
*chip
= mtd_to_nand(mtd
);
770 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
771 struct brcmnand_controller
*ctrl
= host
->ctrl
;
773 brcmnand_write_reg(ctrl
, BRCMNAND_CMD_EXT_ADDRESS
,
774 (host
->cs
<< 16) | ((addr
>> 32) & 0xffff));
775 (void)brcmnand_read_reg(ctrl
, BRCMNAND_CMD_EXT_ADDRESS
);
776 brcmnand_write_reg(ctrl
, BRCMNAND_CMD_ADDRESS
,
777 lower_32_bits(addr
));
778 (void)brcmnand_read_reg(ctrl
, BRCMNAND_CMD_ADDRESS
);
781 static inline u16
brcmnand_cs_offset(struct brcmnand_controller
*ctrl
, int cs
,
782 enum brcmnand_cs_reg reg
)
784 u16 offs_cs0
= ctrl
->reg_offsets
[BRCMNAND_CS0_BASE
];
785 u16 offs_cs1
= ctrl
->reg_offsets
[BRCMNAND_CS1_BASE
];
788 if (cs
== 0 && ctrl
->cs0_offsets
)
789 cs_offs
= ctrl
->cs0_offsets
[reg
];
791 cs_offs
= ctrl
->cs_offsets
[reg
];
794 return offs_cs1
+ (cs
- 1) * ctrl
->reg_spacing
+ cs_offs
;
796 return offs_cs0
+ cs
* ctrl
->reg_spacing
+ cs_offs
;
799 static inline u32
brcmnand_count_corrected(struct brcmnand_controller
*ctrl
)
801 if (ctrl
->nand_version
< 0x0600)
803 return brcmnand_read_reg(ctrl
, BRCMNAND_CORR_COUNT
);
806 static void brcmnand_wr_corr_thresh(struct brcmnand_host
*host
, u8 val
)
808 struct brcmnand_controller
*ctrl
= host
->ctrl
;
809 unsigned int shift
= 0, bits
;
810 enum brcmnand_reg reg
= BRCMNAND_CORR_THRESHOLD
;
813 if (ctrl
->nand_version
== 0x0702)
815 else if (ctrl
->nand_version
>= 0x0600)
817 else if (ctrl
->nand_version
>= 0x0500)
822 if (ctrl
->nand_version
>= 0x0702) {
824 reg
= BRCMNAND_CORR_THRESHOLD_EXT
;
825 shift
= (cs
% 4) * bits
;
826 } else if (ctrl
->nand_version
>= 0x0600) {
828 reg
= BRCMNAND_CORR_THRESHOLD_EXT
;
829 shift
= (cs
% 5) * bits
;
831 brcmnand_rmw_reg(ctrl
, reg
, (bits
- 1) << shift
, shift
, val
);
834 static inline int brcmnand_cmd_shift(struct brcmnand_controller
*ctrl
)
836 if (ctrl
->nand_version
< 0x0602)
841 /***********************************************************************
842 * NAND ACC CONTROL bitfield
844 * Some bits have remained constant throughout hardware revision, while
845 * others have shifted around.
846 ***********************************************************************/
848 /* Constant for all versions (where supported) */
850 /* See BRCMNAND_HAS_CACHE_MODE */
851 ACC_CONTROL_CACHE_MODE
= BIT(22),
853 /* See BRCMNAND_HAS_PREFETCH */
854 ACC_CONTROL_PREFETCH
= BIT(23),
856 ACC_CONTROL_PAGE_HIT
= BIT(24),
857 ACC_CONTROL_WR_PREEMPT
= BIT(25),
858 ACC_CONTROL_PARTIAL_PAGE
= BIT(26),
859 ACC_CONTROL_RD_ERASED
= BIT(27),
860 ACC_CONTROL_FAST_PGM_RDIN
= BIT(28),
861 ACC_CONTROL_WR_ECC
= BIT(30),
862 ACC_CONTROL_RD_ECC
= BIT(31),
865 static inline u32
brcmnand_spare_area_mask(struct brcmnand_controller
*ctrl
)
867 if (ctrl
->nand_version
== 0x0702)
868 return GENMASK(7, 0);
869 else if (ctrl
->nand_version
>= 0x0600)
870 return GENMASK(6, 0);
872 return GENMASK(5, 0);
875 #define NAND_ACC_CONTROL_ECC_SHIFT 16
876 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
878 static inline u32
brcmnand_ecc_level_mask(struct brcmnand_controller
*ctrl
)
880 u32 mask
= (ctrl
->nand_version
>= 0x0600) ? 0x1f : 0x0f;
882 mask
<<= NAND_ACC_CONTROL_ECC_SHIFT
;
884 /* v7.2 includes additional ECC levels */
885 if (ctrl
->nand_version
>= 0x0702)
886 mask
|= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT
;
891 static void brcmnand_set_ecc_enabled(struct brcmnand_host
*host
, int en
)
893 struct brcmnand_controller
*ctrl
= host
->ctrl
;
894 u16 offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_ACC_CONTROL
);
895 u32 acc_control
= nand_readreg(ctrl
, offs
);
896 u32 ecc_flags
= ACC_CONTROL_WR_ECC
| ACC_CONTROL_RD_ECC
;
899 acc_control
|= ecc_flags
; /* enable RD/WR ECC */
900 acc_control
|= host
->hwcfg
.ecc_level
901 << NAND_ACC_CONTROL_ECC_SHIFT
;
903 acc_control
&= ~ecc_flags
; /* disable RD/WR ECC */
904 acc_control
&= ~brcmnand_ecc_level_mask(ctrl
);
907 nand_writereg(ctrl
, offs
, acc_control
);
910 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller
*ctrl
)
912 if (ctrl
->nand_version
>= 0x0702)
914 else if (ctrl
->nand_version
>= 0x0600)
916 else if (ctrl
->nand_version
>= 0x0500)
922 static int brcmnand_get_sector_size_1k(struct brcmnand_host
*host
)
924 struct brcmnand_controller
*ctrl
= host
->ctrl
;
925 int shift
= brcmnand_sector_1k_shift(ctrl
);
926 u16 acc_control_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
927 BRCMNAND_CS_ACC_CONTROL
);
932 return (nand_readreg(ctrl
, acc_control_offs
) >> shift
) & 0x1;
935 static void brcmnand_set_sector_size_1k(struct brcmnand_host
*host
, int val
)
937 struct brcmnand_controller
*ctrl
= host
->ctrl
;
938 int shift
= brcmnand_sector_1k_shift(ctrl
);
939 u16 acc_control_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
940 BRCMNAND_CS_ACC_CONTROL
);
946 tmp
= nand_readreg(ctrl
, acc_control_offs
);
947 tmp
&= ~(1 << shift
);
948 tmp
|= (!!val
) << shift
;
949 nand_writereg(ctrl
, acc_control_offs
, tmp
);
952 /***********************************************************************
954 ***********************************************************************/
957 CS_SELECT_NAND_WP
= BIT(29),
958 CS_SELECT_AUTO_DEVICE_ID_CFG
= BIT(30),
961 static int bcmnand_ctrl_poll_status(struct brcmnand_controller
*ctrl
,
962 u32 mask
, u32 expected_val
,
963 unsigned long timeout_ms
)
969 timeout_ms
= NAND_POLL_STATUS_TIMEOUT_MS
;
971 limit
= jiffies
+ msecs_to_jiffies(timeout_ms
);
973 val
= brcmnand_read_reg(ctrl
, BRCMNAND_INTFC_STATUS
);
974 if ((val
& mask
) == expected_val
)
978 } while (time_after(limit
, jiffies
));
980 dev_warn(ctrl
->dev
, "timeout on status poll (expected %x got %x)\n",
981 expected_val
, val
& mask
);
986 static inline void brcmnand_set_wp(struct brcmnand_controller
*ctrl
, bool en
)
988 u32 val
= en
? CS_SELECT_NAND_WP
: 0;
990 brcmnand_rmw_reg(ctrl
, BRCMNAND_CS_SELECT
, CS_SELECT_NAND_WP
, 0, val
);
993 /***********************************************************************
995 ***********************************************************************/
997 static inline bool has_flash_dma(struct brcmnand_controller
*ctrl
)
999 return ctrl
->flash_dma_base
;
1002 static inline bool has_edu(struct brcmnand_controller
*ctrl
)
1004 return ctrl
->edu_base
;
1007 static inline bool use_dma(struct brcmnand_controller
*ctrl
)
1009 return has_flash_dma(ctrl
) || has_edu(ctrl
);
1012 static inline void disable_ctrl_irqs(struct brcmnand_controller
*ctrl
)
1014 if (ctrl
->pio_poll_mode
)
1017 if (has_flash_dma(ctrl
)) {
1018 ctrl
->flash_dma_base
= NULL
;
1019 disable_irq(ctrl
->dma_irq
);
1022 disable_irq(ctrl
->irq
);
1023 ctrl
->pio_poll_mode
= true;
1026 static inline bool flash_dma_buf_ok(const void *buf
)
1028 return buf
&& !is_vmalloc_addr(buf
) &&
1029 likely(IS_ALIGNED((uintptr_t)buf
, 4));
1032 static inline void flash_dma_writel(struct brcmnand_controller
*ctrl
,
1033 enum flash_dma_reg dma_reg
, u32 val
)
1035 u16 offs
= ctrl
->flash_dma_offsets
[dma_reg
];
1037 brcmnand_writel(val
, ctrl
->flash_dma_base
+ offs
);
1040 static inline u32
flash_dma_readl(struct brcmnand_controller
*ctrl
,
1041 enum flash_dma_reg dma_reg
)
1043 u16 offs
= ctrl
->flash_dma_offsets
[dma_reg
];
1045 return brcmnand_readl(ctrl
->flash_dma_base
+ offs
);
1048 /* Low-level operation types: command, address, write, or read */
1049 enum brcmnand_llop_type
{
1056 /***********************************************************************
1057 * Internal support functions
1058 ***********************************************************************/
1060 static inline bool is_hamming_ecc(struct brcmnand_controller
*ctrl
,
1061 struct brcmnand_cfg
*cfg
)
1063 if (ctrl
->nand_version
<= 0x0701)
1064 return cfg
->sector_size_1k
== 0 && cfg
->spare_area_size
== 16 &&
1065 cfg
->ecc_level
== 15;
1067 return cfg
->sector_size_1k
== 0 && ((cfg
->spare_area_size
== 16 &&
1068 cfg
->ecc_level
== 15) ||
1069 (cfg
->spare_area_size
== 28 && cfg
->ecc_level
== 16));
1073 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1074 * the layout/configuration.
1075 * Returns -ERRCODE on failure.
1077 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1078 struct mtd_oob_region
*oobregion
)
1080 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1081 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1082 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
1083 int sas
= cfg
->spare_area_size
<< cfg
->sector_size_1k
;
1084 int sectors
= cfg
->page_size
/ (512 << cfg
->sector_size_1k
);
1086 if (section
>= sectors
)
1089 oobregion
->offset
= (section
* sas
) + 6;
1090 oobregion
->length
= 3;
1095 static int brcmnand_hamming_ooblayout_free(struct mtd_info
*mtd
, int section
,
1096 struct mtd_oob_region
*oobregion
)
1098 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1099 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1100 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
1101 int sas
= cfg
->spare_area_size
<< cfg
->sector_size_1k
;
1102 int sectors
= cfg
->page_size
/ (512 << cfg
->sector_size_1k
);
1104 if (section
>= sectors
* 2)
1107 oobregion
->offset
= (section
/ 2) * sas
;
1110 oobregion
->offset
+= 9;
1111 oobregion
->length
= 7;
1113 oobregion
->length
= 6;
1115 /* First sector of each page may have BBI */
1118 * Small-page NAND use byte 6 for BBI while large-page
1121 if (cfg
->page_size
> 512)
1122 oobregion
->offset
++;
1123 oobregion
->length
--;
1130 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops
= {
1131 .ecc
= brcmnand_hamming_ooblayout_ecc
,
1132 .free
= brcmnand_hamming_ooblayout_free
,
1135 static int brcmnand_bch_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1136 struct mtd_oob_region
*oobregion
)
1138 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1139 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1140 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
1141 int sas
= cfg
->spare_area_size
<< cfg
->sector_size_1k
;
1142 int sectors
= cfg
->page_size
/ (512 << cfg
->sector_size_1k
);
1144 if (section
>= sectors
)
1147 oobregion
->offset
= ((section
+ 1) * sas
) - chip
->ecc
.bytes
;
1148 oobregion
->length
= chip
->ecc
.bytes
;
1153 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info
*mtd
, int section
,
1154 struct mtd_oob_region
*oobregion
)
1156 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1157 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1158 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
1159 int sas
= cfg
->spare_area_size
<< cfg
->sector_size_1k
;
1160 int sectors
= cfg
->page_size
/ (512 << cfg
->sector_size_1k
);
1162 if (section
>= sectors
)
1165 if (sas
<= chip
->ecc
.bytes
)
1168 oobregion
->offset
= section
* sas
;
1169 oobregion
->length
= sas
- chip
->ecc
.bytes
;
1172 oobregion
->offset
++;
1173 oobregion
->length
--;
1179 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info
*mtd
, int section
,
1180 struct mtd_oob_region
*oobregion
)
1182 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1183 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1184 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
1185 int sas
= cfg
->spare_area_size
<< cfg
->sector_size_1k
;
1187 if (section
> 1 || sas
- chip
->ecc
.bytes
< 6 ||
1188 (section
&& sas
- chip
->ecc
.bytes
== 6))
1192 oobregion
->offset
= 0;
1193 oobregion
->length
= 5;
1195 oobregion
->offset
= 6;
1196 oobregion
->length
= sas
- chip
->ecc
.bytes
- 6;
1202 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops
= {
1203 .ecc
= brcmnand_bch_ooblayout_ecc
,
1204 .free
= brcmnand_bch_ooblayout_free_lp
,
1207 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops
= {
1208 .ecc
= brcmnand_bch_ooblayout_ecc
,
1209 .free
= brcmnand_bch_ooblayout_free_sp
,
1212 static int brcmstb_choose_ecc_layout(struct brcmnand_host
*host
)
1214 struct brcmnand_cfg
*p
= &host
->hwcfg
;
1215 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
1216 struct nand_ecc_ctrl
*ecc
= &host
->chip
.ecc
;
1217 unsigned int ecc_level
= p
->ecc_level
;
1218 int sas
= p
->spare_area_size
<< p
->sector_size_1k
;
1219 int sectors
= p
->page_size
/ (512 << p
->sector_size_1k
);
1221 if (p
->sector_size_1k
)
1224 if (is_hamming_ecc(host
->ctrl
, p
)) {
1225 ecc
->bytes
= 3 * sectors
;
1226 mtd_set_ooblayout(mtd
, &brcmnand_hamming_ooblayout_ops
);
1231 * CONTROLLER_VERSION:
1232 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1233 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1234 * But we will just be conservative.
1236 ecc
->bytes
= DIV_ROUND_UP(ecc_level
* 14, 8);
1237 if (p
->page_size
== 512)
1238 mtd_set_ooblayout(mtd
, &brcmnand_bch_sp_ooblayout_ops
);
1240 mtd_set_ooblayout(mtd
, &brcmnand_bch_lp_ooblayout_ops
);
1242 if (ecc
->bytes
>= sas
) {
1243 dev_err(&host
->pdev
->dev
,
1244 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1252 static void brcmnand_wp(struct mtd_info
*mtd
, int wp
)
1254 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1255 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1256 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1258 if ((ctrl
->features
& BRCMNAND_HAS_WP
) && wp_on
== 1) {
1259 static int old_wp
= -1;
1263 dev_dbg(ctrl
->dev
, "WP %s\n", wp
? "on" : "off");
1268 * make sure ctrl/flash ready before and after
1269 * changing state of #WP pin
1271 ret
= bcmnand_ctrl_poll_status(ctrl
, NAND_CTRL_RDY
|
1274 NAND_STATUS_READY
, 0);
1278 brcmnand_set_wp(ctrl
, wp
);
1279 nand_status_op(chip
, NULL
);
1280 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1281 ret
= bcmnand_ctrl_poll_status(ctrl
,
1287 (wp
? 0 : NAND_STATUS_WP
), 0);
1290 dev_err_ratelimited(&host
->pdev
->dev
,
1291 "nand #WP expected %s\n",
1296 /* Helper functions for reading and writing OOB registers */
1297 static inline u8
oob_reg_read(struct brcmnand_controller
*ctrl
, u32 offs
)
1299 u16 offset0
, offset10
, reg_offs
;
1301 offset0
= ctrl
->reg_offsets
[BRCMNAND_OOB_READ_BASE
];
1302 offset10
= ctrl
->reg_offsets
[BRCMNAND_OOB_READ_10_BASE
];
1304 if (offs
>= ctrl
->max_oob
)
1307 if (offs
>= 16 && offset10
)
1308 reg_offs
= offset10
+ ((offs
- 0x10) & ~0x03);
1310 reg_offs
= offset0
+ (offs
& ~0x03);
1312 return nand_readreg(ctrl
, reg_offs
) >> (24 - ((offs
& 0x03) << 3));
1315 static inline void oob_reg_write(struct brcmnand_controller
*ctrl
, u32 offs
,
1318 u16 offset0
, offset10
, reg_offs
;
1320 offset0
= ctrl
->reg_offsets
[BRCMNAND_OOB_WRITE_BASE
];
1321 offset10
= ctrl
->reg_offsets
[BRCMNAND_OOB_WRITE_10_BASE
];
1323 if (offs
>= ctrl
->max_oob
)
1326 if (offs
>= 16 && offset10
)
1327 reg_offs
= offset10
+ ((offs
- 0x10) & ~0x03);
1329 reg_offs
= offset0
+ (offs
& ~0x03);
1331 nand_writereg(ctrl
, reg_offs
, data
);
1335 * read_oob_from_regs - read data from OOB registers
1336 * @ctrl: NAND controller
1337 * @i: sub-page sector index
1338 * @oob: buffer to read to
1339 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1340 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1342 static int read_oob_from_regs(struct brcmnand_controller
*ctrl
, int i
, u8
*oob
,
1343 int sas
, int sector_1k
)
1345 int tbytes
= sas
<< sector_1k
;
1348 /* Adjust OOB values for 1K sector size */
1349 if (sector_1k
&& (i
& 0x01))
1350 tbytes
= max(0, tbytes
- (int)ctrl
->max_oob
);
1351 tbytes
= min_t(int, tbytes
, ctrl
->max_oob
);
1353 for (j
= 0; j
< tbytes
; j
++)
1354 oob
[j
] = oob_reg_read(ctrl
, j
);
1359 * write_oob_to_regs - write data to OOB registers
1360 * @i: sub-page sector index
1361 * @oob: buffer to write from
1362 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1363 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1365 static int write_oob_to_regs(struct brcmnand_controller
*ctrl
, int i
,
1366 const u8
*oob
, int sas
, int sector_1k
)
1368 int tbytes
= sas
<< sector_1k
;
1371 /* Adjust OOB values for 1K sector size */
1372 if (sector_1k
&& (i
& 0x01))
1373 tbytes
= max(0, tbytes
- (int)ctrl
->max_oob
);
1374 tbytes
= min_t(int, tbytes
, ctrl
->max_oob
);
1376 for (j
= 0; j
< tbytes
; j
+= 4)
1377 oob_reg_write(ctrl
, j
,
1378 (oob
[j
+ 0] << 24) |
1379 (oob
[j
+ 1] << 16) |
1385 static void brcmnand_edu_init(struct brcmnand_controller
*ctrl
)
1387 /* initialize edu */
1388 edu_writel(ctrl
, EDU_ERR_STATUS
, 0);
1389 edu_readl(ctrl
, EDU_ERR_STATUS
);
1390 edu_writel(ctrl
, EDU_DONE
, 0);
1391 edu_writel(ctrl
, EDU_DONE
, 0);
1392 edu_writel(ctrl
, EDU_DONE
, 0);
1393 edu_writel(ctrl
, EDU_DONE
, 0);
1394 edu_readl(ctrl
, EDU_DONE
);
1398 static irqreturn_t
brcmnand_edu_irq(int irq
, void *data
)
1400 struct brcmnand_controller
*ctrl
= data
;
1402 if (ctrl
->edu_count
) {
1404 while (!(edu_readl(ctrl
, EDU_DONE
) & EDU_DONE_MASK
))
1406 edu_writel(ctrl
, EDU_DONE
, 0);
1407 edu_readl(ctrl
, EDU_DONE
);
1410 if (ctrl
->edu_count
) {
1411 ctrl
->edu_dram_addr
+= FC_BYTES
;
1412 ctrl
->edu_ext_addr
+= FC_BYTES
;
1414 edu_writel(ctrl
, EDU_DRAM_ADDR
, (u32
)ctrl
->edu_dram_addr
);
1415 edu_readl(ctrl
, EDU_DRAM_ADDR
);
1416 edu_writel(ctrl
, EDU_EXT_ADDR
, ctrl
->edu_ext_addr
);
1417 edu_readl(ctrl
, EDU_EXT_ADDR
);
1419 mb(); /* flush previous writes */
1420 edu_writel(ctrl
, EDU_CMD
, ctrl
->edu_cmd
);
1421 edu_readl(ctrl
, EDU_CMD
);
1426 complete(&ctrl
->edu_done
);
1431 static irqreturn_t
brcmnand_ctlrdy_irq(int irq
, void *data
)
1433 struct brcmnand_controller
*ctrl
= data
;
1435 /* Discard all NAND_CTLRDY interrupts during DMA */
1436 if (ctrl
->dma_pending
)
1439 /* check if you need to piggy back on the ctrlrdy irq */
1440 if (ctrl
->edu_pending
) {
1441 if (irq
== ctrl
->irq
&& ((int)ctrl
->edu_irq
>= 0))
1442 /* Discard interrupts while using dedicated edu irq */
1445 /* no registered edu irq, call handler */
1446 return brcmnand_edu_irq(irq
, data
);
1449 complete(&ctrl
->done
);
1453 /* Handle SoC-specific interrupt hardware */
1454 static irqreturn_t
brcmnand_irq(int irq
, void *data
)
1456 struct brcmnand_controller
*ctrl
= data
;
1458 if (ctrl
->soc
->ctlrdy_ack(ctrl
->soc
))
1459 return brcmnand_ctlrdy_irq(irq
, data
);
1464 static irqreturn_t
brcmnand_dma_irq(int irq
, void *data
)
1466 struct brcmnand_controller
*ctrl
= data
;
1468 complete(&ctrl
->dma_done
);
1473 static void brcmnand_send_cmd(struct brcmnand_host
*host
, int cmd
)
1475 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1479 cmd_addr
= brcmnand_read_reg(ctrl
, BRCMNAND_CMD_ADDRESS
);
1481 dev_dbg(ctrl
->dev
, "send native cmd %d addr 0x%llx\n", cmd
, cmd_addr
);
1483 BUG_ON(ctrl
->cmd_pending
!= 0);
1484 ctrl
->cmd_pending
= cmd
;
1486 ret
= bcmnand_ctrl_poll_status(ctrl
, NAND_CTRL_RDY
, NAND_CTRL_RDY
, 0);
1489 mb(); /* flush previous writes */
1490 brcmnand_write_reg(ctrl
, BRCMNAND_CMD_START
,
1491 cmd
<< brcmnand_cmd_shift(ctrl
));
1494 /***********************************************************************
1495 * NAND MTD API: read/program/erase
1496 ***********************************************************************/
1498 static void brcmnand_cmd_ctrl(struct nand_chip
*chip
, int dat
,
1501 /* intentionally left blank */
1504 static bool brcmstb_nand_wait_for_completion(struct nand_chip
*chip
)
1506 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1507 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1508 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1512 if (mtd
->oops_panic_write
) {
1513 /* switch to interrupt polling and PIO mode */
1514 disable_ctrl_irqs(ctrl
);
1515 sts
= bcmnand_ctrl_poll_status(ctrl
, NAND_CTRL_RDY
,
1517 err
= (sts
< 0) ? true : false;
1519 unsigned long timeo
= msecs_to_jiffies(
1520 NAND_POLL_STATUS_TIMEOUT_MS
);
1521 /* wait for completion interrupt */
1522 sts
= wait_for_completion_timeout(&ctrl
->done
, timeo
);
1523 err
= (sts
<= 0) ? true : false;
1529 static int brcmnand_waitfunc(struct nand_chip
*chip
)
1531 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1532 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1535 dev_dbg(ctrl
->dev
, "wait on native cmd %d\n", ctrl
->cmd_pending
);
1536 if (ctrl
->cmd_pending
)
1537 err
= brcmstb_nand_wait_for_completion(chip
);
1540 u32 cmd
= brcmnand_read_reg(ctrl
, BRCMNAND_CMD_START
)
1541 >> brcmnand_cmd_shift(ctrl
);
1543 dev_err_ratelimited(ctrl
->dev
,
1544 "timeout waiting for command %#02x\n", cmd
);
1545 dev_err_ratelimited(ctrl
->dev
, "intfc status %08x\n",
1546 brcmnand_read_reg(ctrl
, BRCMNAND_INTFC_STATUS
));
1548 ctrl
->cmd_pending
= 0;
1549 return brcmnand_read_reg(ctrl
, BRCMNAND_INTFC_STATUS
) &
1558 LLOP_RETURN_IDLE
= BIT(31),
1560 LLOP_DATA_MASK
= GENMASK(15, 0),
1563 static int brcmnand_low_level_op(struct brcmnand_host
*host
,
1564 enum brcmnand_llop_type type
, u32 data
,
1567 struct nand_chip
*chip
= &host
->chip
;
1568 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1571 tmp
= data
& LLOP_DATA_MASK
;
1574 tmp
|= LLOP_WE
| LLOP_CLE
;
1578 tmp
|= LLOP_WE
| LLOP_ALE
;
1591 tmp
|= LLOP_RETURN_IDLE
;
1593 dev_dbg(ctrl
->dev
, "ll_op cmd %#x\n", tmp
);
1595 brcmnand_write_reg(ctrl
, BRCMNAND_LL_OP
, tmp
);
1596 (void)brcmnand_read_reg(ctrl
, BRCMNAND_LL_OP
);
1598 brcmnand_send_cmd(host
, CMD_LOW_LEVEL_OP
);
1599 return brcmnand_waitfunc(chip
);
1602 static void brcmnand_cmdfunc(struct nand_chip
*chip
, unsigned command
,
1603 int column
, int page_addr
)
1605 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1606 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1607 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1608 u64 addr
= (u64
)page_addr
<< chip
->page_shift
;
1611 if (command
== NAND_CMD_READID
|| command
== NAND_CMD_PARAM
||
1612 command
== NAND_CMD_RNDOUT
)
1614 /* Avoid propagating a negative, don't-care address */
1615 else if (page_addr
< 0)
1618 dev_dbg(ctrl
->dev
, "cmd 0x%x addr 0x%llx\n", command
,
1619 (unsigned long long)addr
);
1621 host
->last_cmd
= command
;
1622 host
->last_byte
= 0;
1623 host
->last_addr
= addr
;
1626 case NAND_CMD_RESET
:
1627 native_cmd
= CMD_FLASH_RESET
;
1629 case NAND_CMD_STATUS
:
1630 native_cmd
= CMD_STATUS_READ
;
1632 case NAND_CMD_READID
:
1633 native_cmd
= CMD_DEVICE_ID_READ
;
1635 case NAND_CMD_READOOB
:
1636 native_cmd
= CMD_SPARE_AREA_READ
;
1638 case NAND_CMD_ERASE1
:
1639 native_cmd
= CMD_BLOCK_ERASE
;
1640 brcmnand_wp(mtd
, 0);
1642 case NAND_CMD_PARAM
:
1643 native_cmd
= CMD_PARAMETER_READ
;
1645 case NAND_CMD_SET_FEATURES
:
1646 case NAND_CMD_GET_FEATURES
:
1647 brcmnand_low_level_op(host
, LL_OP_CMD
, command
, false);
1648 brcmnand_low_level_op(host
, LL_OP_ADDR
, column
, false);
1650 case NAND_CMD_RNDOUT
:
1651 native_cmd
= CMD_PARAMETER_CHANGE_COL
;
1652 addr
&= ~((u64
)(FC_BYTES
- 1));
1654 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1655 * NB: hwcfg.sector_size_1k may not be initialized yet
1657 if (brcmnand_get_sector_size_1k(host
)) {
1658 host
->hwcfg
.sector_size_1k
=
1659 brcmnand_get_sector_size_1k(host
);
1660 brcmnand_set_sector_size_1k(host
, 0);
1668 brcmnand_set_cmd_addr(mtd
, addr
);
1669 brcmnand_send_cmd(host
, native_cmd
);
1670 brcmnand_waitfunc(chip
);
1672 if (native_cmd
== CMD_PARAMETER_READ
||
1673 native_cmd
== CMD_PARAMETER_CHANGE_COL
) {
1674 /* Copy flash cache word-wise */
1675 u32
*flash_cache
= (u32
*)ctrl
->flash_cache
;
1678 brcmnand_soc_data_bus_prepare(ctrl
->soc
, true);
1681 * Must cache the FLASH_CACHE now, since changes in
1682 * SECTOR_SIZE_1K may invalidate it
1684 for (i
= 0; i
< FC_WORDS
; i
++)
1686 * Flash cache is big endian for parameter pages, at
1689 flash_cache
[i
] = be32_to_cpu(brcmnand_read_fc(ctrl
, i
));
1691 brcmnand_soc_data_bus_unprepare(ctrl
->soc
, true);
1693 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1694 if (host
->hwcfg
.sector_size_1k
)
1695 brcmnand_set_sector_size_1k(host
,
1696 host
->hwcfg
.sector_size_1k
);
1699 /* Re-enable protection is necessary only after erase */
1700 if (command
== NAND_CMD_ERASE1
)
1701 brcmnand_wp(mtd
, 1);
1704 static uint8_t brcmnand_read_byte(struct nand_chip
*chip
)
1706 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1707 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1711 switch (host
->last_cmd
) {
1712 case NAND_CMD_READID
:
1713 if (host
->last_byte
< 4)
1714 ret
= brcmnand_read_reg(ctrl
, BRCMNAND_ID
) >>
1715 (24 - (host
->last_byte
<< 3));
1716 else if (host
->last_byte
< 8)
1717 ret
= brcmnand_read_reg(ctrl
, BRCMNAND_ID_EXT
) >>
1718 (56 - (host
->last_byte
<< 3));
1721 case NAND_CMD_READOOB
:
1722 ret
= oob_reg_read(ctrl
, host
->last_byte
);
1725 case NAND_CMD_STATUS
:
1726 ret
= brcmnand_read_reg(ctrl
, BRCMNAND_INTFC_STATUS
) &
1728 if (wp_on
) /* hide WP status */
1729 ret
|= NAND_STATUS_WP
;
1732 case NAND_CMD_PARAM
:
1733 case NAND_CMD_RNDOUT
:
1734 addr
= host
->last_addr
+ host
->last_byte
;
1735 offs
= addr
& (FC_BYTES
- 1);
1737 /* At FC_BYTES boundary, switch to next column */
1738 if (host
->last_byte
> 0 && offs
== 0)
1739 nand_change_read_column_op(chip
, addr
, NULL
, 0, false);
1741 ret
= ctrl
->flash_cache
[offs
];
1743 case NAND_CMD_GET_FEATURES
:
1744 if (host
->last_byte
>= ONFI_SUBFEATURE_PARAM_LEN
) {
1747 bool last
= host
->last_byte
==
1748 ONFI_SUBFEATURE_PARAM_LEN
- 1;
1749 brcmnand_low_level_op(host
, LL_OP_RD
, 0, last
);
1750 ret
= brcmnand_read_reg(ctrl
, BRCMNAND_LL_RDATA
) & 0xff;
1754 dev_dbg(ctrl
->dev
, "read byte = 0x%02x\n", ret
);
1760 static void brcmnand_read_buf(struct nand_chip
*chip
, uint8_t *buf
, int len
)
1764 for (i
= 0; i
< len
; i
++, buf
++)
1765 *buf
= brcmnand_read_byte(chip
);
1768 static void brcmnand_write_buf(struct nand_chip
*chip
, const uint8_t *buf
,
1772 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1774 switch (host
->last_cmd
) {
1775 case NAND_CMD_SET_FEATURES
:
1776 for (i
= 0; i
< len
; i
++)
1777 brcmnand_low_level_op(host
, LL_OP_WR
, buf
[i
],
1789 static int brcmnand_edu_trans(struct brcmnand_host
*host
, u64 addr
, u32
*buf
,
1792 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1793 unsigned long timeo
= msecs_to_jiffies(200);
1795 int dir
= (cmd
== CMD_PAGE_READ
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
1796 u8 edu_cmd
= (cmd
== CMD_PAGE_READ
? EDU_CMD_READ
: EDU_CMD_WRITE
);
1797 unsigned int trans
= len
>> FC_SHIFT
;
1800 pa
= dma_map_single(ctrl
->dev
, buf
, len
, dir
);
1801 if (dma_mapping_error(ctrl
->dev
, pa
)) {
1802 dev_err(ctrl
->dev
, "unable to map buffer for EDU DMA\n");
1806 ctrl
->edu_pending
= true;
1807 ctrl
->edu_dram_addr
= pa
;
1808 ctrl
->edu_ext_addr
= addr
;
1809 ctrl
->edu_cmd
= edu_cmd
;
1810 ctrl
->edu_count
= trans
;
1812 edu_writel(ctrl
, EDU_DRAM_ADDR
, (u32
)ctrl
->edu_dram_addr
);
1813 edu_readl(ctrl
, EDU_DRAM_ADDR
);
1814 edu_writel(ctrl
, EDU_EXT_ADDR
, ctrl
->edu_ext_addr
);
1815 edu_readl(ctrl
, EDU_EXT_ADDR
);
1816 edu_writel(ctrl
, EDU_LENGTH
, FC_BYTES
);
1817 edu_readl(ctrl
, EDU_LENGTH
);
1819 /* Start edu engine */
1820 mb(); /* flush previous writes */
1821 edu_writel(ctrl
, EDU_CMD
, ctrl
->edu_cmd
);
1822 edu_readl(ctrl
, EDU_CMD
);
1824 if (wait_for_completion_timeout(&ctrl
->edu_done
, timeo
) <= 0) {
1826 "timeout waiting for EDU; status %#x, error status %#x\n",
1827 edu_readl(ctrl
, EDU_STATUS
),
1828 edu_readl(ctrl
, EDU_ERR_STATUS
));
1831 dma_unmap_single(ctrl
->dev
, pa
, len
, dir
);
1833 /* for program page check NAND status */
1834 if (((brcmnand_read_reg(ctrl
, BRCMNAND_INTFC_STATUS
) &
1835 INTFC_FLASH_STATUS
) & NAND_STATUS_FAIL
) &&
1836 edu_cmd
== EDU_CMD_WRITE
) {
1837 dev_info(ctrl
->dev
, "program failed at %llx\n",
1838 (unsigned long long)addr
);
1842 /* Make sure the EDU status is clean */
1843 if (edu_readl(ctrl
, EDU_STATUS
) & EDU_STATUS_ACTIVE
)
1844 dev_warn(ctrl
->dev
, "EDU still active: %#x\n",
1845 edu_readl(ctrl
, EDU_STATUS
));
1847 if (unlikely(edu_readl(ctrl
, EDU_ERR_STATUS
) & EDU_ERR_STATUS_ERRACK
)) {
1848 dev_warn(ctrl
->dev
, "EDU RBUS error at addr %llx\n",
1849 (unsigned long long)addr
);
1853 ctrl
->edu_pending
= false;
1854 brcmnand_edu_init(ctrl
);
1855 edu_writel(ctrl
, EDU_STOP
, 0); /* force stop */
1856 edu_readl(ctrl
, EDU_STOP
);
1862 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1863 * following ahead of time:
1864 * - Is this descriptor the beginning or end of a linked list?
1865 * - What is the (DMA) address of the next descriptor in the linked list?
1867 static int brcmnand_fill_dma_desc(struct brcmnand_host
*host
,
1868 struct brcm_nand_dma_desc
*desc
, u64 addr
,
1869 dma_addr_t buf
, u32 len
, u8 dma_cmd
,
1870 bool begin
, bool end
,
1871 dma_addr_t next_desc
)
1873 memset(desc
, 0, sizeof(*desc
));
1874 /* Descriptors are written in native byte order (wordwise) */
1875 desc
->next_desc
= lower_32_bits(next_desc
);
1876 desc
->next_desc_ext
= upper_32_bits(next_desc
);
1877 desc
->cmd_irq
= (dma_cmd
<< 24) |
1878 (end
? (0x03 << 8) : 0) | /* IRQ | STOP */
1879 (!!begin
) | ((!!end
) << 1); /* head, tail */
1880 #ifdef CONFIG_CPU_BIG_ENDIAN
1881 desc
->cmd_irq
|= 0x01 << 12;
1883 desc
->dram_addr
= lower_32_bits(buf
);
1884 desc
->dram_addr_ext
= upper_32_bits(buf
);
1885 desc
->tfr_len
= len
;
1886 desc
->total_len
= len
;
1887 desc
->flash_addr
= lower_32_bits(addr
);
1888 desc
->flash_addr_ext
= upper_32_bits(addr
);
1889 desc
->cs
= host
->cs
;
1890 desc
->status_valid
= 0x01;
1895 * Kick the FLASH_DMA engine, with a given DMA descriptor
1897 static void brcmnand_dma_run(struct brcmnand_host
*host
, dma_addr_t desc
)
1899 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1900 unsigned long timeo
= msecs_to_jiffies(100);
1902 flash_dma_writel(ctrl
, FLASH_DMA_FIRST_DESC
, lower_32_bits(desc
));
1903 (void)flash_dma_readl(ctrl
, FLASH_DMA_FIRST_DESC
);
1904 if (ctrl
->nand_version
> 0x0602) {
1905 flash_dma_writel(ctrl
, FLASH_DMA_FIRST_DESC_EXT
,
1906 upper_32_bits(desc
));
1907 (void)flash_dma_readl(ctrl
, FLASH_DMA_FIRST_DESC_EXT
);
1910 /* Start FLASH_DMA engine */
1911 ctrl
->dma_pending
= true;
1912 mb(); /* flush previous writes */
1913 flash_dma_writel(ctrl
, FLASH_DMA_CTRL
, 0x03); /* wake | run */
1915 if (wait_for_completion_timeout(&ctrl
->dma_done
, timeo
) <= 0) {
1917 "timeout waiting for DMA; status %#x, error status %#x\n",
1918 flash_dma_readl(ctrl
, FLASH_DMA_STATUS
),
1919 flash_dma_readl(ctrl
, FLASH_DMA_ERROR_STATUS
));
1921 ctrl
->dma_pending
= false;
1922 flash_dma_writel(ctrl
, FLASH_DMA_CTRL
, 0); /* force stop */
1925 static int brcmnand_dma_trans(struct brcmnand_host
*host
, u64 addr
, u32
*buf
,
1926 u32 len
, u8 dma_cmd
)
1928 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1930 int dir
= dma_cmd
== CMD_PAGE_READ
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1932 buf_pa
= dma_map_single(ctrl
->dev
, buf
, len
, dir
);
1933 if (dma_mapping_error(ctrl
->dev
, buf_pa
)) {
1934 dev_err(ctrl
->dev
, "unable to map buffer for DMA\n");
1938 brcmnand_fill_dma_desc(host
, ctrl
->dma_desc
, addr
, buf_pa
, len
,
1939 dma_cmd
, true, true, 0);
1941 brcmnand_dma_run(host
, ctrl
->dma_pa
);
1943 dma_unmap_single(ctrl
->dev
, buf_pa
, len
, dir
);
1945 if (ctrl
->dma_desc
->status_valid
& FLASH_DMA_ECC_ERROR
)
1947 else if (ctrl
->dma_desc
->status_valid
& FLASH_DMA_CORR_ERROR
)
1954 * Assumes proper CS is already set
1956 static int brcmnand_read_by_pio(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1957 u64 addr
, unsigned int trans
, u32
*buf
,
1958 u8
*oob
, u64
*err_addr
)
1960 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
1961 struct brcmnand_controller
*ctrl
= host
->ctrl
;
1964 brcmnand_clear_ecc_addr(ctrl
);
1966 for (i
= 0; i
< trans
; i
++, addr
+= FC_BYTES
) {
1967 brcmnand_set_cmd_addr(mtd
, addr
);
1968 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1969 brcmnand_send_cmd(host
, CMD_PAGE_READ
);
1970 brcmnand_waitfunc(chip
);
1973 brcmnand_soc_data_bus_prepare(ctrl
->soc
, false);
1975 for (j
= 0; j
< FC_WORDS
; j
++, buf
++)
1976 *buf
= brcmnand_read_fc(ctrl
, j
);
1978 brcmnand_soc_data_bus_unprepare(ctrl
->soc
, false);
1982 oob
+= read_oob_from_regs(ctrl
, i
, oob
,
1983 mtd
->oobsize
/ trans
,
1984 host
->hwcfg
.sector_size_1k
);
1987 *err_addr
= brcmnand_get_uncorrecc_addr(ctrl
);
1994 *err_addr
= brcmnand_get_correcc_addr(ctrl
);
2005 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
2008 * Because the HW ECC signals an ECC error if an erase paged has even a single
2009 * bitflip, we must check each ECC error to see if it is actually an erased
2010 * page with bitflips, not a truly corrupted page.
2012 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2013 * buf will contain raw data.
2014 * Otherwise, buf gets filled with 0xffs and return the maximum number of
2015 * bitflips-per-ECC-sector to the caller.
2018 static int brcmstb_nand_verify_erased_page(struct mtd_info
*mtd
,
2019 struct nand_chip
*chip
, void *buf
, u64 addr
)
2022 void *oob
= chip
->oob_poi
;
2024 int page
= addr
>> chip
->page_shift
;
2029 buf
= nand_get_data_buf(chip
);
2031 sas
= mtd
->oobsize
/ chip
->ecc
.steps
;
2033 /* read without ecc for verification */
2034 ret
= chip
->ecc
.read_page_raw(chip
, buf
, true, page
);
2038 for (i
= 0; i
< chip
->ecc
.steps
; i
++, oob
+= sas
) {
2039 ecc_chunk
= buf
+ chip
->ecc
.size
* i
;
2040 ret
= nand_check_erased_ecc_chunk(ecc_chunk
,
2043 chip
->ecc
.strength
);
2047 bitflips
= max(bitflips
, ret
);
2053 static int brcmnand_read(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2054 u64 addr
, unsigned int trans
, u32
*buf
, u8
*oob
)
2056 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2057 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2062 dev_dbg(ctrl
->dev
, "read %llx -> %p\n", (unsigned long long)addr
, buf
);
2065 brcmnand_clear_ecc_addr(ctrl
);
2067 if (ctrl
->dma_trans
&& !oob
&& flash_dma_buf_ok(buf
)) {
2068 err
= ctrl
->dma_trans(host
, addr
, buf
,
2073 if (mtd_is_bitflip_or_eccerr(err
))
2080 memset(oob
, 0x99, mtd
->oobsize
);
2082 err
= brcmnand_read_by_pio(mtd
, chip
, addr
, trans
, buf
,
2086 if (mtd_is_eccerr(err
)) {
2088 * On controller version and 7.0, 7.1 , DMA read after a
2089 * prior PIO read that reported uncorrectable error,
2090 * the DMA engine captures this error following DMA read
2091 * cleared only on subsequent DMA read, so just retry once
2092 * to clear a possible false error reported for current DMA
2095 if ((ctrl
->nand_version
== 0x0700) ||
2096 (ctrl
->nand_version
== 0x0701)) {
2104 * Controller version 7.2 has hw encoder to detect erased page
2105 * bitflips, apply sw verification for older controllers only
2107 if (ctrl
->nand_version
< 0x0702) {
2108 err
= brcmstb_nand_verify_erased_page(mtd
, chip
, buf
,
2110 /* erased page bitflips corrected */
2115 dev_dbg(ctrl
->dev
, "uncorrectable error at 0x%llx\n",
2116 (unsigned long long)err_addr
);
2117 mtd
->ecc_stats
.failed
++;
2118 /* NAND layer expects zero on ECC errors */
2122 if (mtd_is_bitflip(err
)) {
2123 unsigned int corrected
= brcmnand_count_corrected(ctrl
);
2125 dev_dbg(ctrl
->dev
, "corrected error at 0x%llx\n",
2126 (unsigned long long)err_addr
);
2127 mtd
->ecc_stats
.corrected
+= corrected
;
2128 /* Always exceed the software-imposed threshold */
2129 return max(mtd
->bitflip_threshold
, corrected
);
2135 static int brcmnand_read_page(struct nand_chip
*chip
, uint8_t *buf
,
2136 int oob_required
, int page
)
2138 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2139 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2140 u8
*oob
= oob_required
? (u8
*)chip
->oob_poi
: NULL
;
2142 nand_read_page_op(chip
, page
, 0, NULL
, 0);
2144 return brcmnand_read(mtd
, chip
, host
->last_addr
,
2145 mtd
->writesize
>> FC_SHIFT
, (u32
*)buf
, oob
);
2148 static int brcmnand_read_page_raw(struct nand_chip
*chip
, uint8_t *buf
,
2149 int oob_required
, int page
)
2151 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2152 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2153 u8
*oob
= oob_required
? (u8
*)chip
->oob_poi
: NULL
;
2156 nand_read_page_op(chip
, page
, 0, NULL
, 0);
2158 brcmnand_set_ecc_enabled(host
, 0);
2159 ret
= brcmnand_read(mtd
, chip
, host
->last_addr
,
2160 mtd
->writesize
>> FC_SHIFT
, (u32
*)buf
, oob
);
2161 brcmnand_set_ecc_enabled(host
, 1);
2165 static int brcmnand_read_oob(struct nand_chip
*chip
, int page
)
2167 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2169 return brcmnand_read(mtd
, chip
, (u64
)page
<< chip
->page_shift
,
2170 mtd
->writesize
>> FC_SHIFT
,
2171 NULL
, (u8
*)chip
->oob_poi
);
2174 static int brcmnand_read_oob_raw(struct nand_chip
*chip
, int page
)
2176 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2177 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2179 brcmnand_set_ecc_enabled(host
, 0);
2180 brcmnand_read(mtd
, chip
, (u64
)page
<< chip
->page_shift
,
2181 mtd
->writesize
>> FC_SHIFT
,
2182 NULL
, (u8
*)chip
->oob_poi
);
2183 brcmnand_set_ecc_enabled(host
, 1);
2187 static int brcmnand_write(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2188 u64 addr
, const u32
*buf
, u8
*oob
)
2190 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2191 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2192 unsigned int i
, j
, trans
= mtd
->writesize
>> FC_SHIFT
;
2193 int status
, ret
= 0;
2195 dev_dbg(ctrl
->dev
, "write %llx <- %p\n", (unsigned long long)addr
, buf
);
2197 if (unlikely((unsigned long)buf
& 0x03)) {
2198 dev_warn(ctrl
->dev
, "unaligned buffer: %p\n", buf
);
2199 buf
= (u32
*)((unsigned long)buf
& ~0x03);
2202 brcmnand_wp(mtd
, 0);
2204 for (i
= 0; i
< ctrl
->max_oob
; i
+= 4)
2205 oob_reg_write(ctrl
, i
, 0xffffffff);
2207 if (use_dma(ctrl
) && !oob
&& flash_dma_buf_ok(buf
)) {
2208 if (ctrl
->dma_trans(host
, addr
, (u32
*)buf
, mtd
->writesize
,
2216 for (i
= 0; i
< trans
; i
++, addr
+= FC_BYTES
) {
2217 /* full address MUST be set before populating FC */
2218 brcmnand_set_cmd_addr(mtd
, addr
);
2221 brcmnand_soc_data_bus_prepare(ctrl
->soc
, false);
2223 for (j
= 0; j
< FC_WORDS
; j
++, buf
++)
2224 brcmnand_write_fc(ctrl
, j
, *buf
);
2226 brcmnand_soc_data_bus_unprepare(ctrl
->soc
, false);
2228 for (j
= 0; j
< FC_WORDS
; j
++)
2229 brcmnand_write_fc(ctrl
, j
, 0xffffffff);
2233 oob
+= write_oob_to_regs(ctrl
, i
, oob
,
2234 mtd
->oobsize
/ trans
,
2235 host
->hwcfg
.sector_size_1k
);
2238 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
2239 brcmnand_send_cmd(host
, CMD_PROGRAM_PAGE
);
2240 status
= brcmnand_waitfunc(chip
);
2242 if (status
& NAND_STATUS_FAIL
) {
2243 dev_info(ctrl
->dev
, "program failed at %llx\n",
2244 (unsigned long long)addr
);
2250 brcmnand_wp(mtd
, 1);
2254 static int brcmnand_write_page(struct nand_chip
*chip
, const uint8_t *buf
,
2255 int oob_required
, int page
)
2257 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2258 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2259 void *oob
= oob_required
? chip
->oob_poi
: NULL
;
2261 nand_prog_page_begin_op(chip
, page
, 0, NULL
, 0);
2262 brcmnand_write(mtd
, chip
, host
->last_addr
, (const u32
*)buf
, oob
);
2264 return nand_prog_page_end_op(chip
);
2267 static int brcmnand_write_page_raw(struct nand_chip
*chip
, const uint8_t *buf
,
2268 int oob_required
, int page
)
2270 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2271 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2272 void *oob
= oob_required
? chip
->oob_poi
: NULL
;
2274 nand_prog_page_begin_op(chip
, page
, 0, NULL
, 0);
2275 brcmnand_set_ecc_enabled(host
, 0);
2276 brcmnand_write(mtd
, chip
, host
->last_addr
, (const u32
*)buf
, oob
);
2277 brcmnand_set_ecc_enabled(host
, 1);
2279 return nand_prog_page_end_op(chip
);
2282 static int brcmnand_write_oob(struct nand_chip
*chip
, int page
)
2284 return brcmnand_write(nand_to_mtd(chip
), chip
,
2285 (u64
)page
<< chip
->page_shift
, NULL
,
2289 static int brcmnand_write_oob_raw(struct nand_chip
*chip
, int page
)
2291 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2292 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2295 brcmnand_set_ecc_enabled(host
, 0);
2296 ret
= brcmnand_write(mtd
, chip
, (u64
)page
<< chip
->page_shift
, NULL
,
2297 (u8
*)chip
->oob_poi
);
2298 brcmnand_set_ecc_enabled(host
, 1);
2303 /***********************************************************************
2304 * Per-CS setup (1 NAND device)
2305 ***********************************************************************/
2307 static int brcmnand_set_cfg(struct brcmnand_host
*host
,
2308 struct brcmnand_cfg
*cfg
)
2310 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2311 struct nand_chip
*chip
= &host
->chip
;
2312 u16 cfg_offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_CFG
);
2313 u16 cfg_ext_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
2314 BRCMNAND_CS_CFG_EXT
);
2315 u16 acc_control_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
2316 BRCMNAND_CS_ACC_CONTROL
);
2317 u8 block_size
= 0, page_size
= 0, device_size
= 0;
2320 if (ctrl
->block_sizes
) {
2323 for (i
= 0, found
= 0; ctrl
->block_sizes
[i
]; i
++)
2324 if (ctrl
->block_sizes
[i
] * 1024 == cfg
->block_size
) {
2329 dev_warn(ctrl
->dev
, "invalid block size %u\n",
2334 block_size
= ffs(cfg
->block_size
) - ffs(BRCMNAND_MIN_BLOCKSIZE
);
2337 if (cfg
->block_size
< BRCMNAND_MIN_BLOCKSIZE
|| (ctrl
->max_block_size
&&
2338 cfg
->block_size
> ctrl
->max_block_size
)) {
2339 dev_warn(ctrl
->dev
, "invalid block size %u\n",
2344 if (ctrl
->page_sizes
) {
2347 for (i
= 0, found
= 0; ctrl
->page_sizes
[i
]; i
++)
2348 if (ctrl
->page_sizes
[i
] == cfg
->page_size
) {
2353 dev_warn(ctrl
->dev
, "invalid page size %u\n",
2358 page_size
= ffs(cfg
->page_size
) - ffs(BRCMNAND_MIN_PAGESIZE
);
2361 if (cfg
->page_size
< BRCMNAND_MIN_PAGESIZE
|| (ctrl
->max_page_size
&&
2362 cfg
->page_size
> ctrl
->max_page_size
)) {
2363 dev_warn(ctrl
->dev
, "invalid page size %u\n", cfg
->page_size
);
2367 if (fls64(cfg
->device_size
) < fls64(BRCMNAND_MIN_DEVSIZE
)) {
2368 dev_warn(ctrl
->dev
, "invalid device size 0x%llx\n",
2369 (unsigned long long)cfg
->device_size
);
2372 device_size
= fls64(cfg
->device_size
) - fls64(BRCMNAND_MIN_DEVSIZE
);
2374 tmp
= (cfg
->blk_adr_bytes
<< CFG_BLK_ADR_BYTES_SHIFT
) |
2375 (cfg
->col_adr_bytes
<< CFG_COL_ADR_BYTES_SHIFT
) |
2376 (cfg
->ful_adr_bytes
<< CFG_FUL_ADR_BYTES_SHIFT
) |
2377 (!!(cfg
->device_width
== 16) << CFG_BUS_WIDTH_SHIFT
) |
2378 (device_size
<< CFG_DEVICE_SIZE_SHIFT
);
2379 if (cfg_offs
== cfg_ext_offs
) {
2380 tmp
|= (page_size
<< CFG_PAGE_SIZE_SHIFT
) |
2381 (block_size
<< CFG_BLK_SIZE_SHIFT
);
2382 nand_writereg(ctrl
, cfg_offs
, tmp
);
2384 nand_writereg(ctrl
, cfg_offs
, tmp
);
2385 tmp
= (page_size
<< CFG_EXT_PAGE_SIZE_SHIFT
) |
2386 (block_size
<< CFG_EXT_BLK_SIZE_SHIFT
);
2387 nand_writereg(ctrl
, cfg_ext_offs
, tmp
);
2390 tmp
= nand_readreg(ctrl
, acc_control_offs
);
2391 tmp
&= ~brcmnand_ecc_level_mask(ctrl
);
2392 tmp
|= cfg
->ecc_level
<< NAND_ACC_CONTROL_ECC_SHIFT
;
2393 tmp
&= ~brcmnand_spare_area_mask(ctrl
);
2394 tmp
|= cfg
->spare_area_size
;
2395 nand_writereg(ctrl
, acc_control_offs
, tmp
);
2397 brcmnand_set_sector_size_1k(host
, cfg
->sector_size_1k
);
2399 /* threshold = ceil(BCH-level * 0.75) */
2400 brcmnand_wr_corr_thresh(host
, DIV_ROUND_UP(chip
->ecc
.strength
* 3, 4));
2405 static void brcmnand_print_cfg(struct brcmnand_host
*host
,
2406 char *buf
, struct brcmnand_cfg
*cfg
)
2409 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2410 (unsigned long long)cfg
->device_size
>> 20,
2411 cfg
->block_size
>> 10,
2412 cfg
->page_size
>= 1024 ? cfg
->page_size
>> 10 : cfg
->page_size
,
2413 cfg
->page_size
>= 1024 ? "KiB" : "B",
2414 cfg
->spare_area_size
, cfg
->device_width
);
2416 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2417 if (is_hamming_ecc(host
->ctrl
, cfg
))
2418 sprintf(buf
, ", Hamming ECC");
2419 else if (cfg
->sector_size_1k
)
2420 sprintf(buf
, ", BCH-%u (1KiB sector)", cfg
->ecc_level
<< 1);
2422 sprintf(buf
, ", BCH-%u", cfg
->ecc_level
);
2426 * Minimum number of bytes to address a page. Calculated as:
2427 * roundup(log2(size / page-size) / 8)
2429 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2430 * OK because many other things will break if 'size' is irregular...
2432 static inline int get_blk_adr_bytes(u64 size
, u32 writesize
)
2434 return ALIGN(ilog2(size
) - ilog2(writesize
), 8) >> 3;
2437 static int brcmnand_setup_dev(struct brcmnand_host
*host
)
2439 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
2440 struct nand_chip
*chip
= &host
->chip
;
2441 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2442 struct brcmnand_cfg
*cfg
= &host
->hwcfg
;
2444 u32 offs
, tmp
, oob_sector
;
2447 memset(cfg
, 0, sizeof(*cfg
));
2449 ret
= of_property_read_u32(nand_get_flash_node(chip
),
2450 "brcm,nand-oob-sector-size",
2453 /* Use detected size */
2454 cfg
->spare_area_size
= mtd
->oobsize
/
2455 (mtd
->writesize
>> FC_SHIFT
);
2457 cfg
->spare_area_size
= oob_sector
;
2459 if (cfg
->spare_area_size
> ctrl
->max_oob
)
2460 cfg
->spare_area_size
= ctrl
->max_oob
;
2462 * Set oobsize to be consistent with controller's spare_area_size, as
2463 * the rest is inaccessible.
2465 mtd
->oobsize
= cfg
->spare_area_size
* (mtd
->writesize
>> FC_SHIFT
);
2467 cfg
->device_size
= mtd
->size
;
2468 cfg
->block_size
= mtd
->erasesize
;
2469 cfg
->page_size
= mtd
->writesize
;
2470 cfg
->device_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8;
2471 cfg
->col_adr_bytes
= 2;
2472 cfg
->blk_adr_bytes
= get_blk_adr_bytes(mtd
->size
, mtd
->writesize
);
2474 if (chip
->ecc
.mode
!= NAND_ECC_HW
) {
2475 dev_err(ctrl
->dev
, "only HW ECC supported; selected: %d\n",
2480 if (chip
->ecc
.algo
== NAND_ECC_UNKNOWN
) {
2481 if (chip
->ecc
.strength
== 1 && chip
->ecc
.size
== 512)
2482 /* Default to Hamming for 1-bit ECC, if unspecified */
2483 chip
->ecc
.algo
= NAND_ECC_HAMMING
;
2485 /* Otherwise, BCH */
2486 chip
->ecc
.algo
= NAND_ECC_BCH
;
2489 if (chip
->ecc
.algo
== NAND_ECC_HAMMING
&& (chip
->ecc
.strength
!= 1 ||
2490 chip
->ecc
.size
!= 512)) {
2491 dev_err(ctrl
->dev
, "invalid Hamming params: %d bits per %d bytes\n",
2492 chip
->ecc
.strength
, chip
->ecc
.size
);
2496 if (chip
->ecc
.mode
!= NAND_ECC_NONE
&&
2497 (!chip
->ecc
.size
|| !chip
->ecc
.strength
)) {
2498 if (chip
->base
.eccreq
.step_size
&& chip
->base
.eccreq
.strength
) {
2499 /* use detected ECC parameters */
2500 chip
->ecc
.size
= chip
->base
.eccreq
.step_size
;
2501 chip
->ecc
.strength
= chip
->base
.eccreq
.strength
;
2502 dev_info(ctrl
->dev
, "Using ECC step-size %d, strength %d\n",
2503 chip
->ecc
.size
, chip
->ecc
.strength
);
2507 switch (chip
->ecc
.size
) {
2509 if (chip
->ecc
.algo
== NAND_ECC_HAMMING
)
2510 cfg
->ecc_level
= 15;
2512 cfg
->ecc_level
= chip
->ecc
.strength
;
2513 cfg
->sector_size_1k
= 0;
2516 if (!(ctrl
->features
& BRCMNAND_HAS_1K_SECTORS
)) {
2517 dev_err(ctrl
->dev
, "1KB sectors not supported\n");
2520 if (chip
->ecc
.strength
& 0x1) {
2522 "odd ECC not supported with 1KB sectors\n");
2526 cfg
->ecc_level
= chip
->ecc
.strength
>> 1;
2527 cfg
->sector_size_1k
= 1;
2530 dev_err(ctrl
->dev
, "unsupported ECC size: %d\n",
2535 cfg
->ful_adr_bytes
= cfg
->blk_adr_bytes
;
2536 if (mtd
->writesize
> 512)
2537 cfg
->ful_adr_bytes
+= cfg
->col_adr_bytes
;
2539 cfg
->ful_adr_bytes
+= 1;
2541 ret
= brcmnand_set_cfg(host
, cfg
);
2545 brcmnand_set_ecc_enabled(host
, 1);
2547 brcmnand_print_cfg(host
, msg
, cfg
);
2548 dev_info(ctrl
->dev
, "detected %s\n", msg
);
2550 /* Configure ACC_CONTROL */
2551 offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_ACC_CONTROL
);
2552 tmp
= nand_readreg(ctrl
, offs
);
2553 tmp
&= ~ACC_CONTROL_PARTIAL_PAGE
;
2554 tmp
&= ~ACC_CONTROL_RD_ERASED
;
2556 /* We need to turn on Read from erased paged protected by ECC */
2557 if (ctrl
->nand_version
>= 0x0702)
2558 tmp
|= ACC_CONTROL_RD_ERASED
;
2559 tmp
&= ~ACC_CONTROL_FAST_PGM_RDIN
;
2560 if (ctrl
->features
& BRCMNAND_HAS_PREFETCH
)
2561 tmp
&= ~ACC_CONTROL_PREFETCH
;
2563 nand_writereg(ctrl
, offs
, tmp
);
2568 static int brcmnand_attach_chip(struct nand_chip
*chip
)
2570 struct mtd_info
*mtd
= nand_to_mtd(chip
);
2571 struct brcmnand_host
*host
= nand_get_controller_data(chip
);
2574 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
2576 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2577 * to/from, and have nand_base pass us a bounce buffer instead, as
2580 chip
->options
|= NAND_USE_BOUNCE_BUFFER
;
2582 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
)
2583 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
2585 if (brcmnand_setup_dev(host
))
2588 chip
->ecc
.size
= host
->hwcfg
.sector_size_1k
? 1024 : 512;
2590 /* only use our internal HW threshold */
2591 mtd
->bitflip_threshold
= 1;
2593 ret
= brcmstb_choose_ecc_layout(host
);
2598 static const struct nand_controller_ops brcmnand_controller_ops
= {
2599 .attach_chip
= brcmnand_attach_chip
,
2602 static int brcmnand_init_cs(struct brcmnand_host
*host
, struct device_node
*dn
)
2604 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2605 struct platform_device
*pdev
= host
->pdev
;
2606 struct mtd_info
*mtd
;
2607 struct nand_chip
*chip
;
2611 ret
= of_property_read_u32(dn
, "reg", &host
->cs
);
2613 dev_err(&pdev
->dev
, "can't get chip-select\n");
2617 mtd
= nand_to_mtd(&host
->chip
);
2620 nand_set_flash_node(chip
, dn
);
2621 nand_set_controller_data(chip
, host
);
2622 mtd
->name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
, "brcmnand.%d",
2627 mtd
->owner
= THIS_MODULE
;
2628 mtd
->dev
.parent
= &pdev
->dev
;
2630 chip
->legacy
.cmd_ctrl
= brcmnand_cmd_ctrl
;
2631 chip
->legacy
.cmdfunc
= brcmnand_cmdfunc
;
2632 chip
->legacy
.waitfunc
= brcmnand_waitfunc
;
2633 chip
->legacy
.read_byte
= brcmnand_read_byte
;
2634 chip
->legacy
.read_buf
= brcmnand_read_buf
;
2635 chip
->legacy
.write_buf
= brcmnand_write_buf
;
2637 chip
->ecc
.mode
= NAND_ECC_HW
;
2638 chip
->ecc
.read_page
= brcmnand_read_page
;
2639 chip
->ecc
.write_page
= brcmnand_write_page
;
2640 chip
->ecc
.read_page_raw
= brcmnand_read_page_raw
;
2641 chip
->ecc
.write_page_raw
= brcmnand_write_page_raw
;
2642 chip
->ecc
.write_oob_raw
= brcmnand_write_oob_raw
;
2643 chip
->ecc
.read_oob_raw
= brcmnand_read_oob_raw
;
2644 chip
->ecc
.read_oob
= brcmnand_read_oob
;
2645 chip
->ecc
.write_oob
= brcmnand_write_oob
;
2647 chip
->controller
= &ctrl
->controller
;
2650 * The bootloader might have configured 16bit mode but
2651 * NAND READID command only works in 8bit mode. We force
2652 * 8bit mode here to ensure that NAND READID commands works.
2654 cfg_offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_CFG
);
2655 nand_writereg(ctrl
, cfg_offs
,
2656 nand_readreg(ctrl
, cfg_offs
) & ~CFG_BUS_WIDTH
);
2658 ret
= nand_scan(chip
, 1);
2662 ret
= mtd_device_register(mtd
, NULL
, 0);
2669 static void brcmnand_save_restore_cs_config(struct brcmnand_host
*host
,
2672 struct brcmnand_controller
*ctrl
= host
->ctrl
;
2673 u16 cfg_offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_CFG
);
2674 u16 cfg_ext_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
2675 BRCMNAND_CS_CFG_EXT
);
2676 u16 acc_control_offs
= brcmnand_cs_offset(ctrl
, host
->cs
,
2677 BRCMNAND_CS_ACC_CONTROL
);
2678 u16 t1_offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_TIMING1
);
2679 u16 t2_offs
= brcmnand_cs_offset(ctrl
, host
->cs
, BRCMNAND_CS_TIMING2
);
2682 nand_writereg(ctrl
, cfg_offs
, host
->hwcfg
.config
);
2683 if (cfg_offs
!= cfg_ext_offs
)
2684 nand_writereg(ctrl
, cfg_ext_offs
,
2685 host
->hwcfg
.config_ext
);
2686 nand_writereg(ctrl
, acc_control_offs
, host
->hwcfg
.acc_control
);
2687 nand_writereg(ctrl
, t1_offs
, host
->hwcfg
.timing_1
);
2688 nand_writereg(ctrl
, t2_offs
, host
->hwcfg
.timing_2
);
2690 host
->hwcfg
.config
= nand_readreg(ctrl
, cfg_offs
);
2691 if (cfg_offs
!= cfg_ext_offs
)
2692 host
->hwcfg
.config_ext
=
2693 nand_readreg(ctrl
, cfg_ext_offs
);
2694 host
->hwcfg
.acc_control
= nand_readreg(ctrl
, acc_control_offs
);
2695 host
->hwcfg
.timing_1
= nand_readreg(ctrl
, t1_offs
);
2696 host
->hwcfg
.timing_2
= nand_readreg(ctrl
, t2_offs
);
2700 static int brcmnand_suspend(struct device
*dev
)
2702 struct brcmnand_controller
*ctrl
= dev_get_drvdata(dev
);
2703 struct brcmnand_host
*host
;
2705 list_for_each_entry(host
, &ctrl
->host_list
, node
)
2706 brcmnand_save_restore_cs_config(host
, 0);
2708 ctrl
->nand_cs_nand_select
= brcmnand_read_reg(ctrl
, BRCMNAND_CS_SELECT
);
2709 ctrl
->nand_cs_nand_xor
= brcmnand_read_reg(ctrl
, BRCMNAND_CS_XOR
);
2710 ctrl
->corr_stat_threshold
=
2711 brcmnand_read_reg(ctrl
, BRCMNAND_CORR_THRESHOLD
);
2713 if (has_flash_dma(ctrl
))
2714 ctrl
->flash_dma_mode
= flash_dma_readl(ctrl
, FLASH_DMA_MODE
);
2715 else if (has_edu(ctrl
))
2716 ctrl
->edu_config
= edu_readl(ctrl
, EDU_CONFIG
);
2721 static int brcmnand_resume(struct device
*dev
)
2723 struct brcmnand_controller
*ctrl
= dev_get_drvdata(dev
);
2724 struct brcmnand_host
*host
;
2726 if (has_flash_dma(ctrl
)) {
2727 flash_dma_writel(ctrl
, FLASH_DMA_MODE
, ctrl
->flash_dma_mode
);
2728 flash_dma_writel(ctrl
, FLASH_DMA_ERROR_STATUS
, 0);
2732 ctrl
->edu_config
= edu_readl(ctrl
, EDU_CONFIG
);
2734 edu_writel(ctrl
, EDU_CONFIG
, ctrl
->edu_config
);
2735 edu_readl(ctrl
, EDU_CONFIG
);
2736 brcmnand_edu_init(ctrl
);
2739 brcmnand_write_reg(ctrl
, BRCMNAND_CS_SELECT
, ctrl
->nand_cs_nand_select
);
2740 brcmnand_write_reg(ctrl
, BRCMNAND_CS_XOR
, ctrl
->nand_cs_nand_xor
);
2741 brcmnand_write_reg(ctrl
, BRCMNAND_CORR_THRESHOLD
,
2742 ctrl
->corr_stat_threshold
);
2744 /* Clear/re-enable interrupt */
2745 ctrl
->soc
->ctlrdy_ack(ctrl
->soc
);
2746 ctrl
->soc
->ctlrdy_set_enabled(ctrl
->soc
, true);
2749 list_for_each_entry(host
, &ctrl
->host_list
, node
) {
2750 struct nand_chip
*chip
= &host
->chip
;
2752 brcmnand_save_restore_cs_config(host
, 1);
2754 /* Reset the chip, required by some chips after power-up */
2755 nand_reset_op(chip
);
2761 const struct dev_pm_ops brcmnand_pm_ops
= {
2762 .suspend
= brcmnand_suspend
,
2763 .resume
= brcmnand_resume
,
2765 EXPORT_SYMBOL_GPL(brcmnand_pm_ops
);
2767 static const struct of_device_id brcmnand_of_match
[] = {
2768 { .compatible
= "brcm,brcmnand-v4.0" },
2769 { .compatible
= "brcm,brcmnand-v5.0" },
2770 { .compatible
= "brcm,brcmnand-v6.0" },
2771 { .compatible
= "brcm,brcmnand-v6.1" },
2772 { .compatible
= "brcm,brcmnand-v6.2" },
2773 { .compatible
= "brcm,brcmnand-v7.0" },
2774 { .compatible
= "brcm,brcmnand-v7.1" },
2775 { .compatible
= "brcm,brcmnand-v7.2" },
2776 { .compatible
= "brcm,brcmnand-v7.3" },
2779 MODULE_DEVICE_TABLE(of
, brcmnand_of_match
);
2781 /***********************************************************************
2782 * Platform driver setup (per controller)
2783 ***********************************************************************/
2784 static int brcmnand_edu_setup(struct platform_device
*pdev
)
2786 struct device
*dev
= &pdev
->dev
;
2787 struct brcmnand_controller
*ctrl
= dev_get_drvdata(&pdev
->dev
);
2788 struct resource
*res
;
2791 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "flash-edu");
2793 ctrl
->edu_base
= devm_ioremap_resource(dev
, res
);
2794 if (IS_ERR(ctrl
->edu_base
))
2795 return PTR_ERR(ctrl
->edu_base
);
2797 ctrl
->edu_offsets
= edu_regs
;
2799 edu_writel(ctrl
, EDU_CONFIG
, EDU_CONFIG_MODE_NAND
|
2800 EDU_CONFIG_SWAP_CFG
);
2801 edu_readl(ctrl
, EDU_CONFIG
);
2803 /* initialize edu */
2804 brcmnand_edu_init(ctrl
);
2806 ctrl
->edu_irq
= platform_get_irq_optional(pdev
, 1);
2807 if (ctrl
->edu_irq
< 0) {
2809 "FLASH EDU enabled, using ctlrdy irq\n");
2811 ret
= devm_request_irq(dev
, ctrl
->edu_irq
,
2812 brcmnand_edu_irq
, 0,
2813 "brcmnand-edu", ctrl
);
2815 dev_err(ctrl
->dev
, "can't allocate IRQ %d: error %d\n",
2816 ctrl
->edu_irq
, ret
);
2820 dev_info(dev
, "FLASH EDU enabled using irq %u\n",
2828 int brcmnand_probe(struct platform_device
*pdev
, struct brcmnand_soc
*soc
)
2830 struct device
*dev
= &pdev
->dev
;
2831 struct device_node
*dn
= dev
->of_node
, *child
;
2832 struct brcmnand_controller
*ctrl
;
2833 struct resource
*res
;
2836 /* We only support device-tree instantiation */
2840 if (!of_match_node(brcmnand_of_match
, dn
))
2843 ctrl
= devm_kzalloc(dev
, sizeof(*ctrl
), GFP_KERNEL
);
2847 dev_set_drvdata(dev
, ctrl
);
2850 init_completion(&ctrl
->done
);
2851 init_completion(&ctrl
->dma_done
);
2852 init_completion(&ctrl
->edu_done
);
2853 nand_controller_init(&ctrl
->controller
);
2854 ctrl
->controller
.ops
= &brcmnand_controller_ops
;
2855 INIT_LIST_HEAD(&ctrl
->host_list
);
2857 /* NAND register range */
2858 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2859 ctrl
->nand_base
= devm_ioremap_resource(dev
, res
);
2860 if (IS_ERR(ctrl
->nand_base
))
2861 return PTR_ERR(ctrl
->nand_base
);
2863 /* Enable clock before using NAND registers */
2864 ctrl
->clk
= devm_clk_get(dev
, "nand");
2865 if (!IS_ERR(ctrl
->clk
)) {
2866 ret
= clk_prepare_enable(ctrl
->clk
);
2870 ret
= PTR_ERR(ctrl
->clk
);
2871 if (ret
== -EPROBE_DEFER
)
2877 /* Initialize NAND revision */
2878 ret
= brcmnand_revision_init(ctrl
);
2883 * Most chips have this cache at a fixed offset within 'nand' block.
2884 * Some must specify this region separately.
2886 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nand-cache");
2888 ctrl
->nand_fc
= devm_ioremap_resource(dev
, res
);
2889 if (IS_ERR(ctrl
->nand_fc
)) {
2890 ret
= PTR_ERR(ctrl
->nand_fc
);
2894 ctrl
->nand_fc
= ctrl
->nand_base
+
2895 ctrl
->reg_offsets
[BRCMNAND_FC_BASE
];
2899 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "flash-dma");
2901 ctrl
->flash_dma_base
= devm_ioremap_resource(dev
, res
);
2902 if (IS_ERR(ctrl
->flash_dma_base
)) {
2903 ret
= PTR_ERR(ctrl
->flash_dma_base
);
2907 /* initialize the dma version */
2908 brcmnand_flash_dma_revision_init(ctrl
);
2911 if (ctrl
->nand_version
>= 0x0700)
2912 ret
= dma_set_mask_and_coherent(&pdev
->dev
,
2915 ret
= dma_set_mask_and_coherent(&pdev
->dev
,
2920 /* linked-list and stop on error */
2921 flash_dma_writel(ctrl
, FLASH_DMA_MODE
, FLASH_DMA_MODE_MASK
);
2922 flash_dma_writel(ctrl
, FLASH_DMA_ERROR_STATUS
, 0);
2924 /* Allocate descriptor(s) */
2925 ctrl
->dma_desc
= dmam_alloc_coherent(dev
,
2926 sizeof(*ctrl
->dma_desc
),
2927 &ctrl
->dma_pa
, GFP_KERNEL
);
2928 if (!ctrl
->dma_desc
) {
2933 ctrl
->dma_irq
= platform_get_irq(pdev
, 1);
2934 if ((int)ctrl
->dma_irq
< 0) {
2935 dev_err(dev
, "missing FLASH_DMA IRQ\n");
2940 ret
= devm_request_irq(dev
, ctrl
->dma_irq
,
2941 brcmnand_dma_irq
, 0, DRV_NAME
,
2944 dev_err(dev
, "can't allocate IRQ %d: error %d\n",
2945 ctrl
->dma_irq
, ret
);
2949 dev_info(dev
, "enabling FLASH_DMA\n");
2950 /* set flash dma transfer function to call */
2951 ctrl
->dma_trans
= brcmnand_dma_trans
;
2953 ret
= brcmnand_edu_setup(pdev
);
2957 /* set edu transfer function to call */
2958 ctrl
->dma_trans
= brcmnand_edu_trans
;
2961 /* Disable automatic device ID config, direct addressing */
2962 brcmnand_rmw_reg(ctrl
, BRCMNAND_CS_SELECT
,
2963 CS_SELECT_AUTO_DEVICE_ID_CFG
| 0xff, 0, 0);
2964 /* Disable XOR addressing */
2965 brcmnand_rmw_reg(ctrl
, BRCMNAND_CS_XOR
, 0xff, 0, 0);
2967 if (ctrl
->features
& BRCMNAND_HAS_WP
) {
2968 /* Permanently disable write protection */
2970 brcmnand_set_wp(ctrl
, false);
2976 ctrl
->irq
= platform_get_irq(pdev
, 0);
2977 if ((int)ctrl
->irq
< 0) {
2978 dev_err(dev
, "no IRQ defined\n");
2984 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2990 ret
= devm_request_irq(dev
, ctrl
->irq
, brcmnand_irq
, 0,
2993 /* Enable interrupt */
2994 ctrl
->soc
->ctlrdy_ack(ctrl
->soc
);
2995 ctrl
->soc
->ctlrdy_set_enabled(ctrl
->soc
, true);
2997 /* Use standard interrupt infrastructure */
2998 ret
= devm_request_irq(dev
, ctrl
->irq
, brcmnand_ctlrdy_irq
, 0,
3002 dev_err(dev
, "can't allocate IRQ %d: error %d\n",
3007 for_each_available_child_of_node(dn
, child
) {
3008 if (of_device_is_compatible(child
, "brcm,nandcs")) {
3009 struct brcmnand_host
*host
;
3011 host
= devm_kzalloc(dev
, sizeof(*host
), GFP_KERNEL
);
3020 ret
= brcmnand_init_cs(host
, child
);
3022 devm_kfree(dev
, host
);
3023 continue; /* Try all chip-selects */
3026 list_add_tail(&host
->node
, &ctrl
->host_list
);
3030 /* No chip-selects could initialize properly */
3031 if (list_empty(&ctrl
->host_list
)) {
3039 clk_disable_unprepare(ctrl
->clk
);
3043 EXPORT_SYMBOL_GPL(brcmnand_probe
);
3045 int brcmnand_remove(struct platform_device
*pdev
)
3047 struct brcmnand_controller
*ctrl
= dev_get_drvdata(&pdev
->dev
);
3048 struct brcmnand_host
*host
;
3050 list_for_each_entry(host
, &ctrl
->host_list
, node
)
3051 nand_release(&host
->chip
);
3053 clk_disable_unprepare(ctrl
->clk
);
3055 dev_set_drvdata(&pdev
->dev
, NULL
);
3059 EXPORT_SYMBOL_GPL(brcmnand_remove
);
3061 MODULE_LICENSE("GPL v2");
3062 MODULE_AUTHOR("Kevin Cernekee");
3063 MODULE_AUTHOR("Brian Norris");
3064 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
3065 MODULE_ALIAS("platform:brcmnand");