1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
11 #include <dm/device_compat.h>
12 #include <dm/devres.h>
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dma-direction.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
25 #define DENALI_NAND_NAME "denali-nand"
27 /* for Indexed Addressing */
28 #define DENALI_INDEXED_CTRL 0x00
29 #define DENALI_INDEXED_DATA 0x10
31 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
32 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
33 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
34 #define DENALI_MAP11 (3 << 26) /* direct controller access */
36 /* MAP11 access cycle type */
37 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
38 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
39 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
42 #define DENALI_ERASE 0x01
44 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
46 #define DENALI_INVALID_BANK -1
47 #define DENALI_NR_BANKS 4
49 static inline struct denali_nand_info
*mtd_to_denali(struct mtd_info
*mtd
)
51 return container_of(mtd_to_nand(mtd
), struct denali_nand_info
, nand
);
55 * Direct Addressing - the slave address forms the control information (command
56 * type, bank, block, and page address). The slave data is the actual data to
57 * be transferred. This mode requires 28 bits of address region allocated.
59 static u32
denali_direct_read(struct denali_nand_info
*denali
, u32 addr
)
61 return ioread32(denali
->host
+ addr
);
64 static void denali_direct_write(struct denali_nand_info
*denali
, u32 addr
,
67 iowrite32(data
, denali
->host
+ addr
);
71 * Indexed Addressing - address translation module intervenes in passing the
72 * control information. This mode reduces the required address range. The
73 * control information and transferred data are latched by the registers in
74 * the translation module.
76 static u32
denali_indexed_read(struct denali_nand_info
*denali
, u32 addr
)
78 iowrite32(addr
, denali
->host
+ DENALI_INDEXED_CTRL
);
79 return ioread32(denali
->host
+ DENALI_INDEXED_DATA
);
82 static void denali_indexed_write(struct denali_nand_info
*denali
, u32 addr
,
85 iowrite32(addr
, denali
->host
+ DENALI_INDEXED_CTRL
);
86 iowrite32(data
, denali
->host
+ DENALI_INDEXED_DATA
);
90 * Use the configuration feature register to determine the maximum number of
91 * banks that the hardware supports.
93 static void denali_detect_max_banks(struct denali_nand_info
*denali
)
95 uint32_t features
= ioread32(denali
->reg
+ FEATURES
);
97 denali
->max_banks
= 1 << FIELD_GET(FEATURES__N_BANKS
, features
);
99 /* the encoding changed from rev 5.0 to 5.1 */
100 if (denali
->revision
< 0x0501)
101 denali
->max_banks
<<= 1;
104 static void __maybe_unused
denali_enable_irq(struct denali_nand_info
*denali
)
108 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
109 iowrite32(U32_MAX
, denali
->reg
+ INTR_EN(i
));
110 iowrite32(GLOBAL_INT_EN_FLAG
, denali
->reg
+ GLOBAL_INT_ENABLE
);
113 static void __maybe_unused
denali_disable_irq(struct denali_nand_info
*denali
)
117 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
118 iowrite32(0, denali
->reg
+ INTR_EN(i
));
119 iowrite32(0, denali
->reg
+ GLOBAL_INT_ENABLE
);
122 static void denali_clear_irq(struct denali_nand_info
*denali
,
123 int bank
, uint32_t irq_status
)
125 /* write one to clear bits */
126 iowrite32(irq_status
, denali
->reg
+ INTR_STATUS(bank
));
129 static void denali_clear_irq_all(struct denali_nand_info
*denali
)
133 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
134 denali_clear_irq(denali
, i
, U32_MAX
);
137 static void __denali_check_irq(struct denali_nand_info
*denali
)
142 for (i
= 0; i
< DENALI_NR_BANKS
; i
++) {
143 irq_status
= ioread32(denali
->reg
+ INTR_STATUS(i
));
144 denali_clear_irq(denali
, i
, irq_status
);
146 if (i
!= denali
->active_bank
)
149 denali
->irq_status
|= irq_status
;
153 static void denali_reset_irq(struct denali_nand_info
*denali
)
155 denali
->irq_status
= 0;
156 denali
->irq_mask
= 0;
159 static uint32_t denali_wait_for_irq(struct denali_nand_info
*denali
,
162 unsigned long time_left
= 1000000;
165 __denali_check_irq(denali
);
167 if (irq_mask
& denali
->irq_status
)
168 return denali
->irq_status
;
174 dev_err(denali
->dev
, "timeout while waiting for irq 0x%x\n",
179 return denali
->irq_status
;
182 static uint32_t denali_check_irq(struct denali_nand_info
*denali
)
184 __denali_check_irq(denali
);
186 return denali
->irq_status
;
189 static void denali_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
191 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
192 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
195 for (i
= 0; i
< len
; i
++)
196 buf
[i
] = denali
->host_read(denali
, addr
);
199 static void denali_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
201 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
202 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
205 for (i
= 0; i
< len
; i
++)
206 denali
->host_write(denali
, addr
, buf
[i
]);
209 static void denali_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
211 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
212 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
213 uint16_t *buf16
= (uint16_t *)buf
;
216 for (i
= 0; i
< len
/ 2; i
++)
217 buf16
[i
] = denali
->host_read(denali
, addr
);
220 static void denali_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
,
223 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
224 u32 addr
= DENALI_MAP11_DATA
| DENALI_BANK(denali
);
225 const uint16_t *buf16
= (const uint16_t *)buf
;
228 for (i
= 0; i
< len
/ 2; i
++)
229 denali
->host_write(denali
, addr
, buf16
[i
]);
232 static uint8_t denali_read_byte(struct mtd_info
*mtd
)
236 denali_read_buf(mtd
, &byte
, 1);
241 static void denali_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
243 denali_write_buf(mtd
, &byte
, 1);
246 static uint16_t denali_read_word(struct mtd_info
*mtd
)
250 denali_read_buf16(mtd
, (uint8_t *)&word
, 2);
255 static void denali_cmd_ctrl(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
)
257 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
261 type
= DENALI_MAP11_CMD
;
262 else if (ctrl
& NAND_ALE
)
263 type
= DENALI_MAP11_ADDR
;
268 * Some commands are followed by chip->dev_ready or chip->waitfunc.
269 * irq_status must be cleared here to catch the R/B# interrupt later.
271 if (ctrl
& NAND_CTRL_CHANGE
)
272 denali_reset_irq(denali
);
274 denali
->host_write(denali
, DENALI_BANK(denali
) | type
, dat
);
277 static int denali_dev_ready(struct mtd_info
*mtd
)
279 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
281 return !!(denali_check_irq(denali
) & INTR__INT_ACT
);
284 static int denali_check_erased_page(struct mtd_info
*mtd
,
285 struct nand_chip
*chip
, uint8_t *buf
,
286 unsigned long uncor_ecc_flags
,
287 unsigned int max_bitflips
)
289 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
290 int ecc_steps
= chip
->ecc
.steps
;
291 int ecc_size
= chip
->ecc
.size
;
292 int ecc_bytes
= chip
->ecc
.bytes
;
295 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
300 for (i
= 0; i
< ecc_steps
; i
++) {
301 if (!(uncor_ecc_flags
& BIT(i
)))
304 stat
= nand_check_erased_ecc_chunk(buf
, ecc_size
,
309 mtd
->ecc_stats
.failed
++;
311 mtd
->ecc_stats
.corrected
+= stat
;
312 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
316 ecc_code
+= ecc_bytes
;
322 static int denali_hw_ecc_fixup(struct mtd_info
*mtd
,
323 struct denali_nand_info
*denali
,
324 unsigned long *uncor_ecc_flags
)
326 struct nand_chip
*chip
= mtd_to_nand(mtd
);
327 int bank
= denali
->active_bank
;
329 unsigned int max_bitflips
;
331 ecc_cor
= ioread32(denali
->reg
+ ECC_COR_INFO(bank
));
332 ecc_cor
>>= ECC_COR_INFO__SHIFT(bank
);
334 if (ecc_cor
& ECC_COR_INFO__UNCOR_ERR
) {
336 * This flag is set when uncorrectable error occurs at least in
337 * one ECC sector. We can not know "how many sectors", or
338 * "which sector(s)". We need erase-page check for all sectors.
340 *uncor_ecc_flags
= GENMASK(chip
->ecc
.steps
- 1, 0);
344 max_bitflips
= FIELD_GET(ECC_COR_INFO__MAX_ERRORS
, ecc_cor
);
347 * The register holds the maximum of per-sector corrected bitflips.
348 * This is suitable for the return value of the ->read_page() callback.
349 * Unfortunately, we can not know the total number of corrected bits in
350 * the page. Increase the stats by max_bitflips. (compromised solution)
352 mtd
->ecc_stats
.corrected
+= max_bitflips
;
357 static int denali_sw_ecc_fixup(struct mtd_info
*mtd
,
358 struct denali_nand_info
*denali
,
359 unsigned long *uncor_ecc_flags
, uint8_t *buf
)
361 unsigned int ecc_size
= denali
->nand
.ecc
.size
;
362 unsigned int bitflips
= 0;
363 unsigned int max_bitflips
= 0;
364 uint32_t err_addr
, err_cor_info
;
365 unsigned int err_byte
, err_sector
, err_device
;
366 uint8_t err_cor_value
;
367 unsigned int prev_sector
= 0;
370 denali_reset_irq(denali
);
373 err_addr
= ioread32(denali
->reg
+ ECC_ERROR_ADDRESS
);
374 err_sector
= FIELD_GET(ECC_ERROR_ADDRESS__SECTOR
, err_addr
);
375 err_byte
= FIELD_GET(ECC_ERROR_ADDRESS__OFFSET
, err_addr
);
377 err_cor_info
= ioread32(denali
->reg
+ ERR_CORRECTION_INFO
);
378 err_cor_value
= FIELD_GET(ERR_CORRECTION_INFO__BYTE
,
380 err_device
= FIELD_GET(ERR_CORRECTION_INFO__DEVICE
,
383 /* reset the bitflip counter when crossing ECC sector */
384 if (err_sector
!= prev_sector
)
387 if (err_cor_info
& ERR_CORRECTION_INFO__UNCOR
) {
389 * Check later if this is a real ECC error, or
392 *uncor_ecc_flags
|= BIT(err_sector
);
393 } else if (err_byte
< ecc_size
) {
395 * If err_byte is larger than ecc_size, means error
396 * happened in OOB, so we ignore it. It's no need for
397 * us to correct it err_device is represented the NAND
398 * error bits are happened in if there are more than
399 * one NAND connected.
402 unsigned int flips_in_byte
;
404 offset
= (err_sector
* ecc_size
+ err_byte
) *
405 denali
->devs_per_cs
+ err_device
;
407 /* correct the ECC error */
408 flips_in_byte
= hweight8(buf
[offset
] ^ err_cor_value
);
409 buf
[offset
] ^= err_cor_value
;
410 mtd
->ecc_stats
.corrected
+= flips_in_byte
;
411 bitflips
+= flips_in_byte
;
413 max_bitflips
= max(max_bitflips
, bitflips
);
416 prev_sector
= err_sector
;
417 } while (!(err_cor_info
& ERR_CORRECTION_INFO__LAST_ERR
));
420 * Once handle all ECC errors, controller will trigger an
421 * ECC_TRANSACTION_DONE interrupt.
423 irq_status
= denali_wait_for_irq(denali
, INTR__ECC_TRANSACTION_DONE
);
424 if (!(irq_status
& INTR__ECC_TRANSACTION_DONE
))
430 static void denali_setup_dma64(struct denali_nand_info
*denali
,
431 dma_addr_t dma_addr
, int page
, int write
)
434 const int page_count
= 1;
436 mode
= DENALI_MAP10
| DENALI_BANK(denali
) | page
;
438 /* DMA is a three step process */
441 * 1. setup transfer type, interrupt when complete,
442 * burst len = 64 bytes, the number of pages
444 denali
->host_write(denali
, mode
,
445 0x01002000 | (64 << 16) | (write
<< 8) | page_count
);
447 /* 2. set memory low address */
448 denali
->host_write(denali
, mode
, lower_32_bits(dma_addr
));
450 /* 3. set memory high address */
451 denali
->host_write(denali
, mode
, upper_32_bits(dma_addr
));
454 static void denali_setup_dma32(struct denali_nand_info
*denali
,
455 dma_addr_t dma_addr
, int page
, int write
)
458 const int page_count
= 1;
460 mode
= DENALI_MAP10
| DENALI_BANK(denali
);
462 /* DMA is a four step process */
464 /* 1. setup transfer type and # of pages */
465 denali
->host_write(denali
, mode
| page
,
466 0x2000 | (write
<< 8) | page_count
);
468 /* 2. set memory high address bits 23:8 */
469 denali
->host_write(denali
, mode
| ((dma_addr
>> 16) << 8), 0x2200);
471 /* 3. set memory low address bits 23:8 */
472 denali
->host_write(denali
, mode
| ((dma_addr
& 0xffff) << 8), 0x2300);
474 /* 4. interrupt when complete, burst len = 64 bytes */
475 denali
->host_write(denali
, mode
| 0x14000, 0x2400);
478 static int denali_pio_read(struct denali_nand_info
*denali
, void *buf
,
479 size_t size
, int page
, int raw
)
481 u32 addr
= DENALI_MAP01
| DENALI_BANK(denali
) | page
;
482 uint32_t *buf32
= (uint32_t *)buf
;
483 uint32_t irq_status
, ecc_err_mask
;
486 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
487 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
489 ecc_err_mask
= INTR__ECC_ERR
;
491 denali_reset_irq(denali
);
493 for (i
= 0; i
< size
/ 4; i
++)
494 *buf32
++ = denali
->host_read(denali
, addr
);
496 irq_status
= denali_wait_for_irq(denali
, INTR__PAGE_XFER_INC
);
497 if (!(irq_status
& INTR__PAGE_XFER_INC
))
500 if (irq_status
& INTR__ERASED_PAGE
)
501 memset(buf
, 0xff, size
);
503 return irq_status
& ecc_err_mask
? -EBADMSG
: 0;
506 static int denali_pio_write(struct denali_nand_info
*denali
,
507 const void *buf
, size_t size
, int page
, int raw
)
509 u32 addr
= DENALI_MAP01
| DENALI_BANK(denali
) | page
;
510 const uint32_t *buf32
= (uint32_t *)buf
;
514 denali_reset_irq(denali
);
516 for (i
= 0; i
< size
/ 4; i
++)
517 denali
->host_write(denali
, addr
, *buf32
++);
519 irq_status
= denali_wait_for_irq(denali
,
520 INTR__PROGRAM_COMP
| INTR__PROGRAM_FAIL
);
521 if (!(irq_status
& INTR__PROGRAM_COMP
))
527 static int denali_pio_xfer(struct denali_nand_info
*denali
, void *buf
,
528 size_t size
, int page
, int raw
, int write
)
531 return denali_pio_write(denali
, buf
, size
, page
, raw
);
533 return denali_pio_read(denali
, buf
, size
, page
, raw
);
536 static int denali_dma_xfer(struct denali_nand_info
*denali
, void *buf
,
537 size_t size
, int page
, int raw
, int write
)
540 uint32_t irq_mask
, irq_status
, ecc_err_mask
;
541 enum dma_data_direction dir
= write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
544 dma_addr
= dma_map_single(buf
, size
, dir
);
545 if (dma_mapping_error(denali
->dev
, dma_addr
)) {
546 dev_dbg(denali
->dev
, "Failed to DMA-map buffer. Trying PIO.\n");
547 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
552 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
553 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
554 * when the page program is completed.
556 irq_mask
= INTR__DMA_CMD_COMP
| INTR__PROGRAM_FAIL
;
558 } else if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
) {
559 irq_mask
= INTR__DMA_CMD_COMP
;
560 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
562 irq_mask
= INTR__DMA_CMD_COMP
;
563 ecc_err_mask
= INTR__ECC_ERR
;
566 iowrite32(DMA_ENABLE__FLAG
, denali
->reg
+ DMA_ENABLE
);
568 * The ->setup_dma() hook kicks DMA by using the data/command
569 * interface, which belongs to a different AXI port from the
570 * register interface. Read back the register to avoid a race.
572 ioread32(denali
->reg
+ DMA_ENABLE
);
574 denali_reset_irq(denali
);
575 denali
->setup_dma(denali
, dma_addr
, page
, write
);
577 irq_status
= denali_wait_for_irq(denali
, irq_mask
);
578 if (!(irq_status
& INTR__DMA_CMD_COMP
))
580 else if (irq_status
& ecc_err_mask
)
583 iowrite32(0, denali
->reg
+ DMA_ENABLE
);
585 dma_unmap_single(dma_addr
, size
, dir
);
587 if (irq_status
& INTR__ERASED_PAGE
)
588 memset(buf
, 0xff, size
);
593 static int denali_data_xfer(struct denali_nand_info
*denali
, void *buf
,
594 size_t size
, int page
, int raw
, int write
)
596 iowrite32(raw
? 0 : ECC_ENABLE__FLAG
, denali
->reg
+ ECC_ENABLE
);
597 iowrite32(raw
? TRANSFER_SPARE_REG__FLAG
: 0,
598 denali
->reg
+ TRANSFER_SPARE_REG
);
600 if (denali
->dma_avail
)
601 return denali_dma_xfer(denali
, buf
, size
, page
, raw
, write
);
603 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
606 static void denali_oob_xfer(struct mtd_info
*mtd
, struct nand_chip
*chip
,
609 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
610 unsigned int start_cmd
= write
? NAND_CMD_SEQIN
: NAND_CMD_READ0
;
611 unsigned int rnd_cmd
= write
? NAND_CMD_RNDIN
: NAND_CMD_RNDOUT
;
612 int writesize
= mtd
->writesize
;
613 int oobsize
= mtd
->oobsize
;
614 uint8_t *bufpoi
= chip
->oob_poi
;
615 int ecc_steps
= chip
->ecc
.steps
;
616 int ecc_size
= chip
->ecc
.size
;
617 int ecc_bytes
= chip
->ecc
.bytes
;
618 int oob_skip
= denali
->oob_skip_bytes
;
619 size_t size
= writesize
+ oobsize
;
622 /* BBM at the beginning of the OOB area */
623 chip
->cmdfunc(mtd
, start_cmd
, writesize
, page
);
625 chip
->write_buf(mtd
, bufpoi
, oob_skip
);
627 chip
->read_buf(mtd
, bufpoi
, oob_skip
);
631 for (i
= 0; i
< ecc_steps
; i
++) {
632 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
635 if (pos
>= writesize
)
637 else if (pos
+ len
> writesize
)
638 len
= writesize
- pos
;
640 chip
->cmdfunc(mtd
, rnd_cmd
, pos
, -1);
642 chip
->write_buf(mtd
, bufpoi
, len
);
644 chip
->read_buf(mtd
, bufpoi
, len
);
646 if (len
< ecc_bytes
) {
647 len
= ecc_bytes
- len
;
648 chip
->cmdfunc(mtd
, rnd_cmd
, writesize
+ oob_skip
, -1);
650 chip
->write_buf(mtd
, bufpoi
, len
);
652 chip
->read_buf(mtd
, bufpoi
, len
);
658 len
= oobsize
- (bufpoi
- chip
->oob_poi
);
659 chip
->cmdfunc(mtd
, rnd_cmd
, size
- len
, -1);
661 chip
->write_buf(mtd
, bufpoi
, len
);
663 chip
->read_buf(mtd
, bufpoi
, len
);
666 static int denali_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
667 uint8_t *buf
, int oob_required
, int page
)
669 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
670 int writesize
= mtd
->writesize
;
671 int oobsize
= mtd
->oobsize
;
672 int ecc_steps
= chip
->ecc
.steps
;
673 int ecc_size
= chip
->ecc
.size
;
674 int ecc_bytes
= chip
->ecc
.bytes
;
675 void *tmp_buf
= denali
->buf
;
676 int oob_skip
= denali
->oob_skip_bytes
;
677 size_t size
= writesize
+ oobsize
;
678 int ret
, i
, pos
, len
;
680 ret
= denali_data_xfer(denali
, tmp_buf
, size
, page
, 1, 0);
684 /* Arrange the buffer for syndrome payload/ecc layout */
686 for (i
= 0; i
< ecc_steps
; i
++) {
687 pos
= i
* (ecc_size
+ ecc_bytes
);
690 if (pos
>= writesize
)
692 else if (pos
+ len
> writesize
)
693 len
= writesize
- pos
;
695 memcpy(buf
, tmp_buf
+ pos
, len
);
697 if (len
< ecc_size
) {
698 len
= ecc_size
- len
;
699 memcpy(buf
, tmp_buf
+ writesize
+ oob_skip
,
707 uint8_t *oob
= chip
->oob_poi
;
709 /* BBM at the beginning of the OOB area */
710 memcpy(oob
, tmp_buf
+ writesize
, oob_skip
);
714 for (i
= 0; i
< ecc_steps
; i
++) {
715 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
718 if (pos
>= writesize
)
720 else if (pos
+ len
> writesize
)
721 len
= writesize
- pos
;
723 memcpy(oob
, tmp_buf
+ pos
, len
);
725 if (len
< ecc_bytes
) {
726 len
= ecc_bytes
- len
;
727 memcpy(oob
, tmp_buf
+ writesize
+ oob_skip
,
734 len
= oobsize
- (oob
- chip
->oob_poi
);
735 memcpy(oob
, tmp_buf
+ size
- len
, len
);
741 static int denali_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
744 denali_oob_xfer(mtd
, chip
, page
, 0);
749 static int denali_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
752 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
755 denali_reset_irq(denali
);
757 denali_oob_xfer(mtd
, chip
, page
, 1);
759 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
760 status
= chip
->waitfunc(mtd
, chip
);
762 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
765 static int denali_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
766 uint8_t *buf
, int oob_required
, int page
)
768 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
769 unsigned long uncor_ecc_flags
= 0;
773 ret
= denali_data_xfer(denali
, buf
, mtd
->writesize
, page
, 0, 0);
774 if (ret
&& ret
!= -EBADMSG
)
777 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
778 stat
= denali_hw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
);
779 else if (ret
== -EBADMSG
)
780 stat
= denali_sw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
, buf
);
785 if (uncor_ecc_flags
) {
786 ret
= denali_read_oob(mtd
, chip
, page
);
790 stat
= denali_check_erased_page(mtd
, chip
, buf
,
791 uncor_ecc_flags
, stat
);
797 static int denali_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
798 const uint8_t *buf
, int oob_required
, int page
)
800 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
801 int writesize
= mtd
->writesize
;
802 int oobsize
= mtd
->oobsize
;
803 int ecc_steps
= chip
->ecc
.steps
;
804 int ecc_size
= chip
->ecc
.size
;
805 int ecc_bytes
= chip
->ecc
.bytes
;
806 void *tmp_buf
= denali
->buf
;
807 int oob_skip
= denali
->oob_skip_bytes
;
808 size_t size
= writesize
+ oobsize
;
812 * Fill the buffer with 0xff first except the full page transfer.
813 * This simplifies the logic.
815 if (!buf
|| !oob_required
)
816 memset(tmp_buf
, 0xff, size
);
818 /* Arrange the buffer for syndrome payload/ecc layout */
820 for (i
= 0; i
< ecc_steps
; i
++) {
821 pos
= i
* (ecc_size
+ ecc_bytes
);
824 if (pos
>= writesize
)
826 else if (pos
+ len
> writesize
)
827 len
= writesize
- pos
;
829 memcpy(tmp_buf
+ pos
, buf
, len
);
831 if (len
< ecc_size
) {
832 len
= ecc_size
- len
;
833 memcpy(tmp_buf
+ writesize
+ oob_skip
, buf
,
841 const uint8_t *oob
= chip
->oob_poi
;
843 /* BBM at the beginning of the OOB area */
844 memcpy(tmp_buf
+ writesize
, oob
, oob_skip
);
848 for (i
= 0; i
< ecc_steps
; i
++) {
849 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
852 if (pos
>= writesize
)
854 else if (pos
+ len
> writesize
)
855 len
= writesize
- pos
;
857 memcpy(tmp_buf
+ pos
, oob
, len
);
859 if (len
< ecc_bytes
) {
860 len
= ecc_bytes
- len
;
861 memcpy(tmp_buf
+ writesize
+ oob_skip
, oob
,
868 len
= oobsize
- (oob
- chip
->oob_poi
);
869 memcpy(tmp_buf
+ size
- len
, oob
, len
);
872 return denali_data_xfer(denali
, tmp_buf
, size
, page
, 1, 1);
875 static int denali_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
876 const uint8_t *buf
, int oob_required
, int page
)
878 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
880 return denali_data_xfer(denali
, (void *)buf
, mtd
->writesize
,
884 static void denali_select_chip(struct mtd_info
*mtd
, int chip
)
886 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
888 denali
->active_bank
= chip
;
891 static int denali_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*chip
)
893 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
896 /* R/B# pin transitioned from low to high? */
897 irq_status
= denali_wait_for_irq(denali
, INTR__INT_ACT
);
899 return irq_status
& INTR__INT_ACT
? 0 : NAND_STATUS_FAIL
;
902 static int denali_erase(struct mtd_info
*mtd
, int page
)
904 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
907 denali_reset_irq(denali
);
909 denali
->host_write(denali
, DENALI_MAP10
| DENALI_BANK(denali
) | page
,
912 /* wait for erase to complete or failure to occur */
913 irq_status
= denali_wait_for_irq(denali
,
914 INTR__ERASE_COMP
| INTR__ERASE_FAIL
);
916 return irq_status
& INTR__ERASE_COMP
? 0 : NAND_STATUS_FAIL
;
919 static int denali_setup_data_interface(struct mtd_info
*mtd
, int chipnr
,
920 const struct nand_data_interface
*conf
)
922 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
923 const struct nand_sdr_timings
*timings
;
924 unsigned long t_x
, mult_x
;
925 int acc_clks
, re_2_we
, re_2_re
, we_2_re
, addr_2_data
;
926 int rdwr_en_lo
, rdwr_en_hi
, rdwr_en_lo_hi
, cs_setup
;
927 int addr_2_data_mask
;
930 timings
= nand_get_sdr_timings(conf
);
932 return PTR_ERR(timings
);
934 /* clk_x period in picoseconds */
935 t_x
= DIV_ROUND_DOWN_ULL(1000000000000ULL, denali
->clk_x_rate
);
940 * The bus interface clock, clk_x, is phase aligned with the core clock.
941 * The clk_x is an integral multiple N of the core clk. The value N is
942 * configured at IP delivery time, and its available value is 4, 5, 6.
944 mult_x
= DIV_ROUND_CLOSEST_ULL(denali
->clk_x_rate
, denali
->clk_rate
);
945 if (mult_x
< 4 || mult_x
> 6)
948 if (chipnr
== NAND_DATA_IFACE_CHECK_ONLY
)
951 /* tREA -> ACC_CLKS */
952 acc_clks
= DIV_ROUND_UP(timings
->tREA_max
, t_x
);
953 acc_clks
= min_t(int, acc_clks
, ACC_CLKS__VALUE
);
955 tmp
= ioread32(denali
->reg
+ ACC_CLKS
);
956 tmp
&= ~ACC_CLKS__VALUE
;
957 tmp
|= FIELD_PREP(ACC_CLKS__VALUE
, acc_clks
);
958 iowrite32(tmp
, denali
->reg
+ ACC_CLKS
);
960 /* tRWH -> RE_2_WE */
961 re_2_we
= DIV_ROUND_UP(timings
->tRHW_min
, t_x
);
962 re_2_we
= min_t(int, re_2_we
, RE_2_WE__VALUE
);
964 tmp
= ioread32(denali
->reg
+ RE_2_WE
);
965 tmp
&= ~RE_2_WE__VALUE
;
966 tmp
|= FIELD_PREP(RE_2_WE__VALUE
, re_2_we
);
967 iowrite32(tmp
, denali
->reg
+ RE_2_WE
);
969 /* tRHZ -> RE_2_RE */
970 re_2_re
= DIV_ROUND_UP(timings
->tRHZ_max
, t_x
);
971 re_2_re
= min_t(int, re_2_re
, RE_2_RE__VALUE
);
973 tmp
= ioread32(denali
->reg
+ RE_2_RE
);
974 tmp
&= ~RE_2_RE__VALUE
;
975 tmp
|= FIELD_PREP(RE_2_RE__VALUE
, re_2_re
);
976 iowrite32(tmp
, denali
->reg
+ RE_2_RE
);
979 * tCCS, tWHR -> WE_2_RE
981 * With WE_2_RE properly set, the Denali controller automatically takes
982 * care of the delay; the driver need not set NAND_WAIT_TCCS.
984 we_2_re
= DIV_ROUND_UP(max(timings
->tCCS_min
, timings
->tWHR_min
), t_x
);
985 we_2_re
= min_t(int, we_2_re
, TWHR2_AND_WE_2_RE__WE_2_RE
);
987 tmp
= ioread32(denali
->reg
+ TWHR2_AND_WE_2_RE
);
988 tmp
&= ~TWHR2_AND_WE_2_RE__WE_2_RE
;
989 tmp
|= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE
, we_2_re
);
990 iowrite32(tmp
, denali
->reg
+ TWHR2_AND_WE_2_RE
);
992 /* tADL -> ADDR_2_DATA */
994 /* for older versions, ADDR_2_DATA is only 6 bit wide */
995 addr_2_data_mask
= TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
;
996 if (denali
->revision
< 0x0501)
997 addr_2_data_mask
>>= 1;
999 addr_2_data
= DIV_ROUND_UP(timings
->tADL_min
, t_x
);
1000 addr_2_data
= min_t(int, addr_2_data
, addr_2_data_mask
);
1002 tmp
= ioread32(denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1003 tmp
&= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
;
1004 tmp
|= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
, addr_2_data
);
1005 iowrite32(tmp
, denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1007 /* tREH, tWH -> RDWR_EN_HI_CNT */
1008 rdwr_en_hi
= DIV_ROUND_UP(max(timings
->tREH_min
, timings
->tWH_min
),
1010 rdwr_en_hi
= min_t(int, rdwr_en_hi
, RDWR_EN_HI_CNT__VALUE
);
1012 tmp
= ioread32(denali
->reg
+ RDWR_EN_HI_CNT
);
1013 tmp
&= ~RDWR_EN_HI_CNT__VALUE
;
1014 tmp
|= FIELD_PREP(RDWR_EN_HI_CNT__VALUE
, rdwr_en_hi
);
1015 iowrite32(tmp
, denali
->reg
+ RDWR_EN_HI_CNT
);
1017 /* tRP, tWP -> RDWR_EN_LO_CNT */
1018 rdwr_en_lo
= DIV_ROUND_UP(max(timings
->tRP_min
, timings
->tWP_min
), t_x
);
1019 rdwr_en_lo_hi
= DIV_ROUND_UP(max(timings
->tRC_min
, timings
->tWC_min
),
1021 rdwr_en_lo_hi
= max_t(int, rdwr_en_lo_hi
, mult_x
);
1022 rdwr_en_lo
= max(rdwr_en_lo
, rdwr_en_lo_hi
- rdwr_en_hi
);
1023 rdwr_en_lo
= min_t(int, rdwr_en_lo
, RDWR_EN_LO_CNT__VALUE
);
1025 tmp
= ioread32(denali
->reg
+ RDWR_EN_LO_CNT
);
1026 tmp
&= ~RDWR_EN_LO_CNT__VALUE
;
1027 tmp
|= FIELD_PREP(RDWR_EN_LO_CNT__VALUE
, rdwr_en_lo
);
1028 iowrite32(tmp
, denali
->reg
+ RDWR_EN_LO_CNT
);
1030 /* tCS, tCEA -> CS_SETUP_CNT */
1031 cs_setup
= max3((int)DIV_ROUND_UP(timings
->tCS_min
, t_x
) - rdwr_en_lo
,
1032 (int)DIV_ROUND_UP(timings
->tCEA_max
, t_x
) - acc_clks
,
1034 cs_setup
= min_t(int, cs_setup
, CS_SETUP_CNT__VALUE
);
1036 tmp
= ioread32(denali
->reg
+ CS_SETUP_CNT
);
1037 tmp
&= ~CS_SETUP_CNT__VALUE
;
1038 tmp
|= FIELD_PREP(CS_SETUP_CNT__VALUE
, cs_setup
);
1039 iowrite32(tmp
, denali
->reg
+ CS_SETUP_CNT
);
1044 static void denali_reset_banks(struct denali_nand_info
*denali
)
1049 for (i
= 0; i
< denali
->max_banks
; i
++) {
1050 denali
->active_bank
= i
;
1052 denali_reset_irq(denali
);
1054 iowrite32(DEVICE_RESET__BANK(i
),
1055 denali
->reg
+ DEVICE_RESET
);
1057 irq_status
= denali_wait_for_irq(denali
,
1058 INTR__RST_COMP
| INTR__INT_ACT
| INTR__TIME_OUT
);
1059 if (!(irq_status
& INTR__INT_ACT
))
1063 dev_dbg(denali
->dev
, "%d chips connected\n", i
);
1064 denali
->max_banks
= i
;
1067 static void denali_hw_init(struct denali_nand_info
*denali
)
1070 * The REVISION register may not be reliable. Platforms are allowed to
1073 if (!denali
->revision
)
1074 denali
->revision
= swab16(ioread32(denali
->reg
+ REVISION
));
1077 * Set how many bytes should be skipped before writing data in OOB.
1078 * If a platform requests a non-zero value, set it to the register.
1079 * Otherwise, read the value out, expecting it has already been set up
1082 if (denali
->oob_skip_bytes
)
1083 iowrite32(denali
->oob_skip_bytes
,
1084 denali
->reg
+ SPARE_AREA_SKIP_BYTES
);
1086 denali
->oob_skip_bytes
= ioread32(denali
->reg
+
1087 SPARE_AREA_SKIP_BYTES
);
1089 denali_detect_max_banks(denali
);
1090 iowrite32(0x0F, denali
->reg
+ RB_PIN_ENABLED
);
1091 iowrite32(CHIP_EN_DONT_CARE__FLAG
, denali
->reg
+ CHIP_ENABLE_DONT_CARE
);
1093 iowrite32(0xffff, denali
->reg
+ SPARE_AREA_MARKER
);
1096 int denali_calc_ecc_bytes(int step_size
, int strength
)
1098 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1099 return DIV_ROUND_UP(strength
* fls(step_size
* 8), 16) * 2;
1101 EXPORT_SYMBOL(denali_calc_ecc_bytes
);
1103 static int denali_ecc_setup(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1104 struct denali_nand_info
*denali
)
1106 int oobavail
= mtd
->oobsize
- denali
->oob_skip_bytes
;
1110 * If .size and .strength are already set (usually by DT),
1111 * check if they are supported by this controller.
1113 if (chip
->ecc
.size
&& chip
->ecc
.strength
)
1114 return nand_check_ecc_caps(chip
, denali
->ecc_caps
, oobavail
);
1117 * We want .size and .strength closest to the chip's requirement
1118 * unless NAND_ECC_MAXIMIZE is requested.
1120 if (!(chip
->ecc
.options
& NAND_ECC_MAXIMIZE
)) {
1121 ret
= nand_match_ecc_req(chip
, denali
->ecc_caps
, oobavail
);
1126 /* Max ECC strength is the last thing we can do */
1127 return nand_maximize_ecc(chip
, denali
->ecc_caps
, oobavail
);
1130 static struct nand_ecclayout nand_oob
;
1132 static int denali_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1133 struct mtd_oob_region
*oobregion
)
1135 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1136 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1141 oobregion
->offset
= denali
->oob_skip_bytes
;
1142 oobregion
->length
= chip
->ecc
.total
;
1147 static int denali_ooblayout_free(struct mtd_info
*mtd
, int section
,
1148 struct mtd_oob_region
*oobregion
)
1150 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1151 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1156 oobregion
->offset
= chip
->ecc
.total
+ denali
->oob_skip_bytes
;
1157 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
1162 static const struct mtd_ooblayout_ops denali_ooblayout_ops
= {
1163 .ecc
= denali_ooblayout_ecc
,
1164 .rfree
= denali_ooblayout_free
,
1167 static int denali_multidev_fixup(struct denali_nand_info
*denali
)
1169 struct nand_chip
*chip
= &denali
->nand
;
1170 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1173 * Support for multi device:
1174 * When the IP configuration is x16 capable and two x8 chips are
1175 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1176 * In this case, the core framework knows nothing about this fact,
1177 * so we should tell it the _logical_ pagesize and anything necessary.
1179 denali
->devs_per_cs
= ioread32(denali
->reg
+ DEVICES_CONNECTED
);
1182 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1183 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1185 if (denali
->devs_per_cs
== 0) {
1186 denali
->devs_per_cs
= 1;
1187 iowrite32(1, denali
->reg
+ DEVICES_CONNECTED
);
1190 if (denali
->devs_per_cs
== 1)
1193 if (denali
->devs_per_cs
!= 2) {
1194 dev_err(denali
->dev
, "unsupported number of devices %d\n",
1195 denali
->devs_per_cs
);
1199 /* 2 chips in parallel */
1201 mtd
->erasesize
<<= 1;
1202 mtd
->writesize
<<= 1;
1204 chip
->chipsize
<<= 1;
1205 chip
->page_shift
+= 1;
1206 chip
->phys_erase_shift
+= 1;
1207 chip
->bbt_erase_shift
+= 1;
1208 chip
->chip_shift
+= 1;
1209 chip
->pagemask
<<= 1;
1210 chip
->ecc
.size
<<= 1;
1211 chip
->ecc
.bytes
<<= 1;
1212 chip
->ecc
.strength
<<= 1;
1213 denali
->oob_skip_bytes
<<= 1;
1218 int denali_init(struct denali_nand_info
*denali
)
1220 struct nand_chip
*chip
= &denali
->nand
;
1221 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1222 u32 features
= ioread32(denali
->reg
+ FEATURES
);
1225 denali_hw_init(denali
);
1227 denali_clear_irq_all(denali
);
1229 denali_reset_banks(denali
);
1231 denali
->active_bank
= DENALI_INVALID_BANK
;
1233 chip
->flash_node
= dev_of_offset(denali
->dev
);
1234 /* Fallback to the default name if DT did not give "label" property */
1236 mtd
->name
= "denali-nand";
1238 chip
->select_chip
= denali_select_chip
;
1239 chip
->read_byte
= denali_read_byte
;
1240 chip
->write_byte
= denali_write_byte
;
1241 chip
->read_word
= denali_read_word
;
1242 chip
->cmd_ctrl
= denali_cmd_ctrl
;
1243 chip
->dev_ready
= denali_dev_ready
;
1244 chip
->waitfunc
= denali_waitfunc
;
1246 if (features
& FEATURES__INDEX_ADDR
) {
1247 denali
->host_read
= denali_indexed_read
;
1248 denali
->host_write
= denali_indexed_write
;
1250 denali
->host_read
= denali_direct_read
;
1251 denali
->host_write
= denali_direct_write
;
1254 /* clk rate info is needed for setup_data_interface */
1255 if (denali
->clk_x_rate
)
1256 chip
->setup_data_interface
= denali_setup_data_interface
;
1258 ret
= nand_scan_ident(mtd
, denali
->max_banks
, NULL
);
1262 if (ioread32(denali
->reg
+ FEATURES
) & FEATURES__DMA
)
1263 denali
->dma_avail
= 1;
1265 if (denali
->dma_avail
) {
1266 chip
->buf_align
= ARCH_DMA_MINALIGN
;
1267 if (denali
->caps
& DENALI_CAP_DMA_64BIT
)
1268 denali
->setup_dma
= denali_setup_dma64
;
1270 denali
->setup_dma
= denali_setup_dma32
;
1272 chip
->buf_align
= 4;
1275 chip
->options
|= NAND_USE_BOUNCE_BUFFER
;
1276 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1277 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
1278 denali
->nand
.ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1280 /* no subpage writes on denali */
1281 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1283 ret
= denali_ecc_setup(mtd
, chip
, denali
);
1285 dev_err(denali
->dev
, "Failed to setup ECC settings.\n");
1289 dev_dbg(denali
->dev
,
1290 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1291 chip
->ecc
.size
, chip
->ecc
.strength
, chip
->ecc
.bytes
);
1293 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD
, 1) |
1294 FIELD_PREP(ECC_CORRECTION__VALUE
, chip
->ecc
.strength
),
1295 denali
->reg
+ ECC_CORRECTION
);
1296 iowrite32(mtd
->erasesize
/ mtd
->writesize
,
1297 denali
->reg
+ PAGES_PER_BLOCK
);
1298 iowrite32(chip
->options
& NAND_BUSWIDTH_16
? 1 : 0,
1299 denali
->reg
+ DEVICE_WIDTH
);
1300 iowrite32(chip
->options
& NAND_ROW_ADDR_3
? 0 : TWO_ROW_ADDR_CYCLES__FLAG
,
1301 denali
->reg
+ TWO_ROW_ADDR_CYCLES
);
1302 iowrite32(mtd
->writesize
, denali
->reg
+ DEVICE_MAIN_AREA_SIZE
);
1303 iowrite32(mtd
->oobsize
, denali
->reg
+ DEVICE_SPARE_AREA_SIZE
);
1305 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_DATA_BLOCK_SIZE
);
1306 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_LAST_DATA_BLOCK_SIZE
);
1307 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1308 iowrite32(mtd
->writesize
/ chip
->ecc
.size
,
1309 denali
->reg
+ CFG_NUM_DATA_BLOCKS
);
1311 mtd_set_ooblayout(mtd
, &denali_ooblayout_ops
);
1313 nand_oob
.eccbytes
= denali
->nand
.ecc
.bytes
;
1314 denali
->nand
.ecc
.layout
= &nand_oob
;
1316 if (chip
->options
& NAND_BUSWIDTH_16
) {
1317 chip
->read_buf
= denali_read_buf16
;
1318 chip
->write_buf
= denali_write_buf16
;
1320 chip
->read_buf
= denali_read_buf
;
1321 chip
->write_buf
= denali_write_buf
;
1323 chip
->ecc
.options
|= NAND_ECC_CUSTOM_PAGE_ACCESS
;
1324 chip
->ecc
.read_page
= denali_read_page
;
1325 chip
->ecc
.read_page_raw
= denali_read_page_raw
;
1326 chip
->ecc
.write_page
= denali_write_page
;
1327 chip
->ecc
.write_page_raw
= denali_write_page_raw
;
1328 chip
->ecc
.read_oob
= denali_read_oob
;
1329 chip
->ecc
.write_oob
= denali_write_oob
;
1330 chip
->erase
= denali_erase
;
1332 ret
= denali_multidev_fixup(denali
);
1337 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1338 * use devm_kmalloc() because the memory allocated by devm_ does not
1339 * guarantee DMA-safe alignment.
1341 denali
->buf
= kmalloc(mtd
->writesize
+ mtd
->oobsize
, GFP_KERNEL
);
1345 ret
= nand_scan_tail(mtd
);
1349 ret
= nand_register(0, mtd
);
1351 dev_err(denali
->dev
, "Failed to register MTD: %d\n", ret
);