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[thirdparty/kernel/linux.git] / drivers / mtd / nand / raw / denali.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NAND Flash Controller Device Driver
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
5 *
6 * Copyright (c) 2017 Socionext Inc.
7 * Reworked by Masahiro Yamada <yamada.masahiro@socionext.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/completion.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20
21 #include "denali.h"
22
23 #define DENALI_NAND_NAME "denali-nand"
24 #define DENALI_DEFAULT_OOB_SKIP_BYTES 8
25
26 /* for Indexed Addressing */
27 #define DENALI_INDEXED_CTRL 0x00
28 #define DENALI_INDEXED_DATA 0x10
29
30 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
31 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
32 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
33 #define DENALI_MAP11 (3 << 26) /* direct controller access */
34
35 /* MAP11 access cycle type */
36 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
37 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
38 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
39
40 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41
42 #define DENALI_INVALID_BANK -1
43 #define DENALI_NR_BANKS 4
44
45 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
46 {
47 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
48 }
49
50 static struct denali_nand_info *to_denali(struct nand_chip *chip)
51 {
52 return container_of(chip, struct denali_nand_info, nand);
53 }
54
55 /*
56 * Direct Addressing - the slave address forms the control information (command
57 * type, bank, block, and page address). The slave data is the actual data to
58 * be transferred. This mode requires 28 bits of address region allocated.
59 */
60 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
61 {
62 return ioread32(denali->host + addr);
63 }
64
65 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
66 u32 data)
67 {
68 iowrite32(data, denali->host + addr);
69 }
70
71 /*
72 * Indexed Addressing - address translation module intervenes in passing the
73 * control information. This mode reduces the required address range. The
74 * control information and transferred data are latched by the registers in
75 * the translation module.
76 */
77 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
78 {
79 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
80 return ioread32(denali->host + DENALI_INDEXED_DATA);
81 }
82
83 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
84 u32 data)
85 {
86 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
87 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
88 }
89
90 /*
91 * Use the configuration feature register to determine the maximum number of
92 * banks that the hardware supports.
93 */
94 static void denali_detect_max_banks(struct denali_nand_info *denali)
95 {
96 uint32_t features = ioread32(denali->reg + FEATURES);
97
98 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
99
100 /* the encoding changed from rev 5.0 to 5.1 */
101 if (denali->revision < 0x0501)
102 denali->max_banks <<= 1;
103 }
104
105 static void denali_enable_irq(struct denali_nand_info *denali)
106 {
107 int i;
108
109 for (i = 0; i < DENALI_NR_BANKS; i++)
110 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
111 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
112 }
113
114 static void denali_disable_irq(struct denali_nand_info *denali)
115 {
116 int i;
117
118 for (i = 0; i < DENALI_NR_BANKS; i++)
119 iowrite32(0, denali->reg + INTR_EN(i));
120 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
121 }
122
123 static void denali_clear_irq(struct denali_nand_info *denali,
124 int bank, uint32_t irq_status)
125 {
126 /* write one to clear bits */
127 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
128 }
129
130 static void denali_clear_irq_all(struct denali_nand_info *denali)
131 {
132 int i;
133
134 for (i = 0; i < DENALI_NR_BANKS; i++)
135 denali_clear_irq(denali, i, U32_MAX);
136 }
137
138 static irqreturn_t denali_isr(int irq, void *dev_id)
139 {
140 struct denali_nand_info *denali = dev_id;
141 irqreturn_t ret = IRQ_NONE;
142 uint32_t irq_status;
143 int i;
144
145 spin_lock(&denali->irq_lock);
146
147 for (i = 0; i < DENALI_NR_BANKS; i++) {
148 irq_status = ioread32(denali->reg + INTR_STATUS(i));
149 if (irq_status)
150 ret = IRQ_HANDLED;
151
152 denali_clear_irq(denali, i, irq_status);
153
154 if (i != denali->active_bank)
155 continue;
156
157 denali->irq_status |= irq_status;
158
159 if (denali->irq_status & denali->irq_mask)
160 complete(&denali->complete);
161 }
162
163 spin_unlock(&denali->irq_lock);
164
165 return ret;
166 }
167
168 static void denali_reset_irq(struct denali_nand_info *denali)
169 {
170 unsigned long flags;
171
172 spin_lock_irqsave(&denali->irq_lock, flags);
173 denali->irq_status = 0;
174 denali->irq_mask = 0;
175 spin_unlock_irqrestore(&denali->irq_lock, flags);
176 }
177
178 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
179 uint32_t irq_mask)
180 {
181 unsigned long time_left, flags;
182 uint32_t irq_status;
183
184 spin_lock_irqsave(&denali->irq_lock, flags);
185
186 irq_status = denali->irq_status;
187
188 if (irq_mask & irq_status) {
189 /* return immediately if the IRQ has already happened. */
190 spin_unlock_irqrestore(&denali->irq_lock, flags);
191 return irq_status;
192 }
193
194 denali->irq_mask = irq_mask;
195 reinit_completion(&denali->complete);
196 spin_unlock_irqrestore(&denali->irq_lock, flags);
197
198 time_left = wait_for_completion_timeout(&denali->complete,
199 msecs_to_jiffies(1000));
200 if (!time_left) {
201 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
202 irq_mask);
203 return 0;
204 }
205
206 return denali->irq_status;
207 }
208
209 static void denali_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
210 {
211 struct mtd_info *mtd = nand_to_mtd(chip);
212 struct denali_nand_info *denali = mtd_to_denali(mtd);
213 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
214 int i;
215
216 for (i = 0; i < len; i++)
217 buf[i] = denali->host_read(denali, addr);
218 }
219
220 static void denali_write_buf(struct nand_chip *chip, const uint8_t *buf,
221 int len)
222 {
223 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
224 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
225 int i;
226
227 for (i = 0; i < len; i++)
228 denali->host_write(denali, addr, buf[i]);
229 }
230
231 static void denali_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
232 {
233 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
234 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
235 uint16_t *buf16 = (uint16_t *)buf;
236 int i;
237
238 for (i = 0; i < len / 2; i++)
239 buf16[i] = denali->host_read(denali, addr);
240 }
241
242 static void denali_write_buf16(struct nand_chip *chip, const uint8_t *buf,
243 int len)
244 {
245 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
246 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
247 const uint16_t *buf16 = (const uint16_t *)buf;
248 int i;
249
250 for (i = 0; i < len / 2; i++)
251 denali->host_write(denali, addr, buf16[i]);
252 }
253
254 static uint8_t denali_read_byte(struct nand_chip *chip)
255 {
256 uint8_t byte;
257
258 denali_read_buf(chip, &byte, 1);
259
260 return byte;
261 }
262
263 static void denali_write_byte(struct nand_chip *chip, uint8_t byte)
264 {
265 denali_write_buf(chip, &byte, 1);
266 }
267
268 static void denali_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
269 {
270 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
271 uint32_t type;
272
273 if (ctrl & NAND_CLE)
274 type = DENALI_MAP11_CMD;
275 else if (ctrl & NAND_ALE)
276 type = DENALI_MAP11_ADDR;
277 else
278 return;
279
280 /*
281 * Some commands are followed by chip->legacy.waitfunc.
282 * irq_status must be cleared here to catch the R/B# interrupt later.
283 */
284 if (ctrl & NAND_CTRL_CHANGE)
285 denali_reset_irq(denali);
286
287 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
288 }
289
290 static int denali_check_erased_page(struct nand_chip *chip, u8 *buf,
291 unsigned long uncor_ecc_flags,
292 unsigned int max_bitflips)
293 {
294 struct denali_nand_info *denali = to_denali(chip);
295 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
296 uint8_t *ecc_code = chip->oob_poi + denali->oob_skip_bytes;
297 int ecc_steps = chip->ecc.steps;
298 int ecc_size = chip->ecc.size;
299 int ecc_bytes = chip->ecc.bytes;
300 int i, stat;
301
302 for (i = 0; i < ecc_steps; i++) {
303 if (!(uncor_ecc_flags & BIT(i)))
304 continue;
305
306 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
307 ecc_code, ecc_bytes,
308 NULL, 0,
309 chip->ecc.strength);
310 if (stat < 0) {
311 ecc_stats->failed++;
312 } else {
313 ecc_stats->corrected += stat;
314 max_bitflips = max_t(unsigned int, max_bitflips, stat);
315 }
316
317 buf += ecc_size;
318 ecc_code += ecc_bytes;
319 }
320
321 return max_bitflips;
322 }
323
324 static int denali_hw_ecc_fixup(struct nand_chip *chip,
325 unsigned long *uncor_ecc_flags)
326 {
327 struct denali_nand_info *denali = to_denali(chip);
328 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
329 int bank = denali->active_bank;
330 uint32_t ecc_cor;
331 unsigned int max_bitflips;
332
333 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
334 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
335
336 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
337 /*
338 * This flag is set when uncorrectable error occurs at least in
339 * one ECC sector. We can not know "how many sectors", or
340 * "which sector(s)". We need erase-page check for all sectors.
341 */
342 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
343 return 0;
344 }
345
346 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
347
348 /*
349 * The register holds the maximum of per-sector corrected bitflips.
350 * This is suitable for the return value of the ->read_page() callback.
351 * Unfortunately, we can not know the total number of corrected bits in
352 * the page. Increase the stats by max_bitflips. (compromised solution)
353 */
354 ecc_stats->corrected += max_bitflips;
355
356 return max_bitflips;
357 }
358
359 static int denali_sw_ecc_fixup(struct nand_chip *chip,
360 unsigned long *uncor_ecc_flags, uint8_t *buf)
361 {
362 struct denali_nand_info *denali = to_denali(chip);
363 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
364 unsigned int ecc_size = chip->ecc.size;
365 unsigned int bitflips = 0;
366 unsigned int max_bitflips = 0;
367 uint32_t err_addr, err_cor_info;
368 unsigned int err_byte, err_sector, err_device;
369 uint8_t err_cor_value;
370 unsigned int prev_sector = 0;
371 uint32_t irq_status;
372
373 denali_reset_irq(denali);
374
375 do {
376 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
377 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
378 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
379
380 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
381 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
382 err_cor_info);
383 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
384 err_cor_info);
385
386 /* reset the bitflip counter when crossing ECC sector */
387 if (err_sector != prev_sector)
388 bitflips = 0;
389
390 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
391 /*
392 * Check later if this is a real ECC error, or
393 * an erased sector.
394 */
395 *uncor_ecc_flags |= BIT(err_sector);
396 } else if (err_byte < ecc_size) {
397 /*
398 * If err_byte is larger than ecc_size, means error
399 * happened in OOB, so we ignore it. It's no need for
400 * us to correct it err_device is represented the NAND
401 * error bits are happened in if there are more than
402 * one NAND connected.
403 */
404 int offset;
405 unsigned int flips_in_byte;
406
407 offset = (err_sector * ecc_size + err_byte) *
408 denali->devs_per_cs + err_device;
409
410 /* correct the ECC error */
411 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
412 buf[offset] ^= err_cor_value;
413 ecc_stats->corrected += flips_in_byte;
414 bitflips += flips_in_byte;
415
416 max_bitflips = max(max_bitflips, bitflips);
417 }
418
419 prev_sector = err_sector;
420 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
421
422 /*
423 * Once handle all ECC errors, controller will trigger an
424 * ECC_TRANSACTION_DONE interrupt.
425 */
426 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
427 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
428 return -EIO;
429
430 return max_bitflips;
431 }
432
433 static void denali_setup_dma64(struct denali_nand_info *denali,
434 dma_addr_t dma_addr, int page, int write)
435 {
436 uint32_t mode;
437 const int page_count = 1;
438
439 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
440
441 /* DMA is a three step process */
442
443 /*
444 * 1. setup transfer type, interrupt when complete,
445 * burst len = 64 bytes, the number of pages
446 */
447 denali->host_write(denali, mode,
448 0x01002000 | (64 << 16) | (write << 8) | page_count);
449
450 /* 2. set memory low address */
451 denali->host_write(denali, mode, lower_32_bits(dma_addr));
452
453 /* 3. set memory high address */
454 denali->host_write(denali, mode, upper_32_bits(dma_addr));
455 }
456
457 static void denali_setup_dma32(struct denali_nand_info *denali,
458 dma_addr_t dma_addr, int page, int write)
459 {
460 uint32_t mode;
461 const int page_count = 1;
462
463 mode = DENALI_MAP10 | DENALI_BANK(denali);
464
465 /* DMA is a four step process */
466
467 /* 1. setup transfer type and # of pages */
468 denali->host_write(denali, mode | page,
469 0x2000 | (write << 8) | page_count);
470
471 /* 2. set memory high address bits 23:8 */
472 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
473
474 /* 3. set memory low address bits 23:8 */
475 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
476
477 /* 4. interrupt when complete, burst len = 64 bytes */
478 denali->host_write(denali, mode | 0x14000, 0x2400);
479 }
480
481 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
482 size_t size, int page)
483 {
484 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
485 uint32_t *buf32 = (uint32_t *)buf;
486 uint32_t irq_status, ecc_err_mask;
487 int i;
488
489 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
490 ecc_err_mask = INTR__ECC_UNCOR_ERR;
491 else
492 ecc_err_mask = INTR__ECC_ERR;
493
494 denali_reset_irq(denali);
495
496 for (i = 0; i < size / 4; i++)
497 *buf32++ = denali->host_read(denali, addr);
498
499 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
500 if (!(irq_status & INTR__PAGE_XFER_INC))
501 return -EIO;
502
503 if (irq_status & INTR__ERASED_PAGE)
504 memset(buf, 0xff, size);
505
506 return irq_status & ecc_err_mask ? -EBADMSG : 0;
507 }
508
509 static int denali_pio_write(struct denali_nand_info *denali,
510 const void *buf, size_t size, int page)
511 {
512 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
513 const uint32_t *buf32 = (uint32_t *)buf;
514 uint32_t irq_status;
515 int i;
516
517 denali_reset_irq(denali);
518
519 for (i = 0; i < size / 4; i++)
520 denali->host_write(denali, addr, *buf32++);
521
522 irq_status = denali_wait_for_irq(denali,
523 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
524 if (!(irq_status & INTR__PROGRAM_COMP))
525 return -EIO;
526
527 return 0;
528 }
529
530 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
531 size_t size, int page, int write)
532 {
533 if (write)
534 return denali_pio_write(denali, buf, size, page);
535 else
536 return denali_pio_read(denali, buf, size, page);
537 }
538
539 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
540 size_t size, int page, int write)
541 {
542 dma_addr_t dma_addr;
543 uint32_t irq_mask, irq_status, ecc_err_mask;
544 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
545 int ret = 0;
546
547 dma_addr = dma_map_single(denali->dev, buf, size, dir);
548 if (dma_mapping_error(denali->dev, dma_addr)) {
549 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
550 return denali_pio_xfer(denali, buf, size, page, write);
551 }
552
553 if (write) {
554 /*
555 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
556 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
557 * when the page program is completed.
558 */
559 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
560 ecc_err_mask = 0;
561 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
562 irq_mask = INTR__DMA_CMD_COMP;
563 ecc_err_mask = INTR__ECC_UNCOR_ERR;
564 } else {
565 irq_mask = INTR__DMA_CMD_COMP;
566 ecc_err_mask = INTR__ECC_ERR;
567 }
568
569 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
570 /*
571 * The ->setup_dma() hook kicks DMA by using the data/command
572 * interface, which belongs to a different AXI port from the
573 * register interface. Read back the register to avoid a race.
574 */
575 ioread32(denali->reg + DMA_ENABLE);
576
577 denali_reset_irq(denali);
578 denali->setup_dma(denali, dma_addr, page, write);
579
580 irq_status = denali_wait_for_irq(denali, irq_mask);
581 if (!(irq_status & INTR__DMA_CMD_COMP))
582 ret = -EIO;
583 else if (irq_status & ecc_err_mask)
584 ret = -EBADMSG;
585
586 iowrite32(0, denali->reg + DMA_ENABLE);
587
588 dma_unmap_single(denali->dev, dma_addr, size, dir);
589
590 if (irq_status & INTR__ERASED_PAGE)
591 memset(buf, 0xff, size);
592
593 return ret;
594 }
595
596 static int denali_data_xfer(struct nand_chip *chip, void *buf, size_t size,
597 int page, int raw, int write)
598 {
599 struct denali_nand_info *denali = to_denali(chip);
600
601 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
602 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
603 denali->reg + TRANSFER_SPARE_REG);
604
605 if (denali->dma_avail)
606 return denali_dma_xfer(denali, buf, size, page, write);
607 else
608 return denali_pio_xfer(denali, buf, size, page, write);
609 }
610
611 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
612 int page, int write)
613 {
614 struct denali_nand_info *denali = mtd_to_denali(mtd);
615 int writesize = mtd->writesize;
616 int oobsize = mtd->oobsize;
617 uint8_t *bufpoi = chip->oob_poi;
618 int ecc_steps = chip->ecc.steps;
619 int ecc_size = chip->ecc.size;
620 int ecc_bytes = chip->ecc.bytes;
621 int oob_skip = denali->oob_skip_bytes;
622 size_t size = writesize + oobsize;
623 int i, pos, len;
624
625 /* BBM at the beginning of the OOB area */
626 if (write)
627 nand_prog_page_begin_op(chip, page, writesize, bufpoi,
628 oob_skip);
629 else
630 nand_read_page_op(chip, page, writesize, bufpoi, oob_skip);
631 bufpoi += oob_skip;
632
633 /* OOB ECC */
634 for (i = 0; i < ecc_steps; i++) {
635 pos = ecc_size + i * (ecc_size + ecc_bytes);
636 len = ecc_bytes;
637
638 if (pos >= writesize)
639 pos += oob_skip;
640 else if (pos + len > writesize)
641 len = writesize - pos;
642
643 if (write)
644 nand_change_write_column_op(chip, pos, bufpoi, len,
645 false);
646 else
647 nand_change_read_column_op(chip, pos, bufpoi, len,
648 false);
649 bufpoi += len;
650 if (len < ecc_bytes) {
651 len = ecc_bytes - len;
652 if (write)
653 nand_change_write_column_op(chip, writesize +
654 oob_skip, bufpoi,
655 len, false);
656 else
657 nand_change_read_column_op(chip, writesize +
658 oob_skip, bufpoi,
659 len, false);
660 bufpoi += len;
661 }
662 }
663
664 /* OOB free */
665 len = oobsize - (bufpoi - chip->oob_poi);
666 if (write)
667 nand_change_write_column_op(chip, size - len, bufpoi, len,
668 false);
669 else
670 nand_change_read_column_op(chip, size - len, bufpoi, len,
671 false);
672 }
673
674 static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf,
675 int oob_required, int page)
676 {
677 struct mtd_info *mtd = nand_to_mtd(chip);
678 struct denali_nand_info *denali = mtd_to_denali(mtd);
679 int writesize = mtd->writesize;
680 int oobsize = mtd->oobsize;
681 int ecc_steps = chip->ecc.steps;
682 int ecc_size = chip->ecc.size;
683 int ecc_bytes = chip->ecc.bytes;
684 void *tmp_buf = denali->buf;
685 int oob_skip = denali->oob_skip_bytes;
686 size_t size = writesize + oobsize;
687 int ret, i, pos, len;
688
689 ret = denali_data_xfer(chip, tmp_buf, size, page, 1, 0);
690 if (ret)
691 return ret;
692
693 /* Arrange the buffer for syndrome payload/ecc layout */
694 if (buf) {
695 for (i = 0; i < ecc_steps; i++) {
696 pos = i * (ecc_size + ecc_bytes);
697 len = ecc_size;
698
699 if (pos >= writesize)
700 pos += oob_skip;
701 else if (pos + len > writesize)
702 len = writesize - pos;
703
704 memcpy(buf, tmp_buf + pos, len);
705 buf += len;
706 if (len < ecc_size) {
707 len = ecc_size - len;
708 memcpy(buf, tmp_buf + writesize + oob_skip,
709 len);
710 buf += len;
711 }
712 }
713 }
714
715 if (oob_required) {
716 uint8_t *oob = chip->oob_poi;
717
718 /* BBM at the beginning of the OOB area */
719 memcpy(oob, tmp_buf + writesize, oob_skip);
720 oob += oob_skip;
721
722 /* OOB ECC */
723 for (i = 0; i < ecc_steps; i++) {
724 pos = ecc_size + i * (ecc_size + ecc_bytes);
725 len = ecc_bytes;
726
727 if (pos >= writesize)
728 pos += oob_skip;
729 else if (pos + len > writesize)
730 len = writesize - pos;
731
732 memcpy(oob, tmp_buf + pos, len);
733 oob += len;
734 if (len < ecc_bytes) {
735 len = ecc_bytes - len;
736 memcpy(oob, tmp_buf + writesize + oob_skip,
737 len);
738 oob += len;
739 }
740 }
741
742 /* OOB free */
743 len = oobsize - (oob - chip->oob_poi);
744 memcpy(oob, tmp_buf + size - len, len);
745 }
746
747 return 0;
748 }
749
750 static int denali_read_oob(struct nand_chip *chip, int page)
751 {
752 struct mtd_info *mtd = nand_to_mtd(chip);
753
754 denali_oob_xfer(mtd, chip, page, 0);
755
756 return 0;
757 }
758
759 static int denali_write_oob(struct nand_chip *chip, int page)
760 {
761 struct mtd_info *mtd = nand_to_mtd(chip);
762
763 denali_oob_xfer(mtd, chip, page, 1);
764
765 return nand_prog_page_end_op(chip);
766 }
767
768 static int denali_read_page(struct nand_chip *chip, uint8_t *buf,
769 int oob_required, int page)
770 {
771 struct mtd_info *mtd = nand_to_mtd(chip);
772 struct denali_nand_info *denali = mtd_to_denali(mtd);
773 unsigned long uncor_ecc_flags = 0;
774 int stat = 0;
775 int ret;
776
777 ret = denali_data_xfer(chip, buf, mtd->writesize, page, 0, 0);
778 if (ret && ret != -EBADMSG)
779 return ret;
780
781 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
782 stat = denali_hw_ecc_fixup(chip, &uncor_ecc_flags);
783 else if (ret == -EBADMSG)
784 stat = denali_sw_ecc_fixup(chip, &uncor_ecc_flags, buf);
785
786 if (stat < 0)
787 return stat;
788
789 if (uncor_ecc_flags) {
790 ret = denali_read_oob(chip, page);
791 if (ret)
792 return ret;
793
794 stat = denali_check_erased_page(chip, buf,
795 uncor_ecc_flags, stat);
796 }
797
798 return stat;
799 }
800
801 static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
802 int oob_required, int page)
803 {
804 struct mtd_info *mtd = nand_to_mtd(chip);
805 struct denali_nand_info *denali = mtd_to_denali(mtd);
806 int writesize = mtd->writesize;
807 int oobsize = mtd->oobsize;
808 int ecc_steps = chip->ecc.steps;
809 int ecc_size = chip->ecc.size;
810 int ecc_bytes = chip->ecc.bytes;
811 void *tmp_buf = denali->buf;
812 int oob_skip = denali->oob_skip_bytes;
813 size_t size = writesize + oobsize;
814 int i, pos, len;
815
816 /*
817 * Fill the buffer with 0xff first except the full page transfer.
818 * This simplifies the logic.
819 */
820 if (!buf || !oob_required)
821 memset(tmp_buf, 0xff, size);
822
823 /* Arrange the buffer for syndrome payload/ecc layout */
824 if (buf) {
825 for (i = 0; i < ecc_steps; i++) {
826 pos = i * (ecc_size + ecc_bytes);
827 len = ecc_size;
828
829 if (pos >= writesize)
830 pos += oob_skip;
831 else if (pos + len > writesize)
832 len = writesize - pos;
833
834 memcpy(tmp_buf + pos, buf, len);
835 buf += len;
836 if (len < ecc_size) {
837 len = ecc_size - len;
838 memcpy(tmp_buf + writesize + oob_skip, buf,
839 len);
840 buf += len;
841 }
842 }
843 }
844
845 if (oob_required) {
846 const uint8_t *oob = chip->oob_poi;
847
848 /* BBM at the beginning of the OOB area */
849 memcpy(tmp_buf + writesize, oob, oob_skip);
850 oob += oob_skip;
851
852 /* OOB ECC */
853 for (i = 0; i < ecc_steps; i++) {
854 pos = ecc_size + i * (ecc_size + ecc_bytes);
855 len = ecc_bytes;
856
857 if (pos >= writesize)
858 pos += oob_skip;
859 else if (pos + len > writesize)
860 len = writesize - pos;
861
862 memcpy(tmp_buf + pos, oob, len);
863 oob += len;
864 if (len < ecc_bytes) {
865 len = ecc_bytes - len;
866 memcpy(tmp_buf + writesize + oob_skip, oob,
867 len);
868 oob += len;
869 }
870 }
871
872 /* OOB free */
873 len = oobsize - (oob - chip->oob_poi);
874 memcpy(tmp_buf + size - len, oob, len);
875 }
876
877 return denali_data_xfer(chip, tmp_buf, size, page, 1, 1);
878 }
879
880 static int denali_write_page(struct nand_chip *chip, const uint8_t *buf,
881 int oob_required, int page)
882 {
883 struct mtd_info *mtd = nand_to_mtd(chip);
884
885 return denali_data_xfer(chip, (void *)buf, mtd->writesize, page,
886 0, 1);
887 }
888
889 static void denali_select_chip(struct nand_chip *chip, int cs)
890 {
891 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
892
893 denali->active_bank = cs;
894 }
895
896 static int denali_waitfunc(struct nand_chip *chip)
897 {
898 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
899 uint32_t irq_status;
900
901 /* R/B# pin transitioned from low to high? */
902 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
903
904 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
905 }
906
907 static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
908 const struct nand_data_interface *conf)
909 {
910 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
911 const struct nand_sdr_timings *timings;
912 unsigned long t_x, mult_x;
913 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
914 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
915 int addr_2_data_mask;
916 uint32_t tmp;
917
918 timings = nand_get_sdr_timings(conf);
919 if (IS_ERR(timings))
920 return PTR_ERR(timings);
921
922 /* clk_x period in picoseconds */
923 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
924 if (!t_x)
925 return -EINVAL;
926
927 /*
928 * The bus interface clock, clk_x, is phase aligned with the core clock.
929 * The clk_x is an integral multiple N of the core clk. The value N is
930 * configured at IP delivery time, and its available value is 4, 5, 6.
931 */
932 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
933 if (mult_x < 4 || mult_x > 6)
934 return -EINVAL;
935
936 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
937 return 0;
938
939 /* tREA -> ACC_CLKS */
940 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
941 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
942
943 tmp = ioread32(denali->reg + ACC_CLKS);
944 tmp &= ~ACC_CLKS__VALUE;
945 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
946 iowrite32(tmp, denali->reg + ACC_CLKS);
947
948 /* tRWH -> RE_2_WE */
949 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
950 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
951
952 tmp = ioread32(denali->reg + RE_2_WE);
953 tmp &= ~RE_2_WE__VALUE;
954 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
955 iowrite32(tmp, denali->reg + RE_2_WE);
956
957 /* tRHZ -> RE_2_RE */
958 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
959 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
960
961 tmp = ioread32(denali->reg + RE_2_RE);
962 tmp &= ~RE_2_RE__VALUE;
963 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
964 iowrite32(tmp, denali->reg + RE_2_RE);
965
966 /*
967 * tCCS, tWHR -> WE_2_RE
968 *
969 * With WE_2_RE properly set, the Denali controller automatically takes
970 * care of the delay; the driver need not set NAND_WAIT_TCCS.
971 */
972 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
973 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
974
975 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
976 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
977 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
978 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
979
980 /* tADL -> ADDR_2_DATA */
981
982 /* for older versions, ADDR_2_DATA is only 6 bit wide */
983 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
984 if (denali->revision < 0x0501)
985 addr_2_data_mask >>= 1;
986
987 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
988 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
989
990 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
991 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
992 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
993 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
994
995 /* tREH, tWH -> RDWR_EN_HI_CNT */
996 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
997 t_x);
998 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
999
1000 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1001 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1002 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1003 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1004
1005 /* tRP, tWP -> RDWR_EN_LO_CNT */
1006 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
1007 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1008 t_x);
1009 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
1010 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1011 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1012
1013 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1014 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1015 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1016 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1017
1018 /* tCS, tCEA -> CS_SETUP_CNT */
1019 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
1020 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
1021 0);
1022 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1023
1024 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1025 tmp &= ~CS_SETUP_CNT__VALUE;
1026 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1027 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1028
1029 return 0;
1030 }
1031
1032 static void denali_hw_init(struct denali_nand_info *denali)
1033 {
1034 /*
1035 * The REVISION register may not be reliable. Platforms are allowed to
1036 * override it.
1037 */
1038 if (!denali->revision)
1039 denali->revision = swab16(ioread32(denali->reg + REVISION));
1040
1041 /*
1042 * Set how many bytes should be skipped before writing data in OOB.
1043 * If a non-zero value has already been set (by firmware or something),
1044 * just use it. Otherwise, set the driver default.
1045 */
1046 denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES);
1047 if (!denali->oob_skip_bytes) {
1048 denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES;
1049 iowrite32(denali->oob_skip_bytes,
1050 denali->reg + SPARE_AREA_SKIP_BYTES);
1051 }
1052
1053 denali_detect_max_banks(denali);
1054 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1055 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1056
1057 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1058 }
1059
1060 int denali_calc_ecc_bytes(int step_size, int strength)
1061 {
1062 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1063 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1064 }
1065 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1066
1067 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1068 struct mtd_oob_region *oobregion)
1069 {
1070 struct denali_nand_info *denali = mtd_to_denali(mtd);
1071 struct nand_chip *chip = mtd_to_nand(mtd);
1072
1073 if (section)
1074 return -ERANGE;
1075
1076 oobregion->offset = denali->oob_skip_bytes;
1077 oobregion->length = chip->ecc.total;
1078
1079 return 0;
1080 }
1081
1082 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1083 struct mtd_oob_region *oobregion)
1084 {
1085 struct denali_nand_info *denali = mtd_to_denali(mtd);
1086 struct nand_chip *chip = mtd_to_nand(mtd);
1087
1088 if (section)
1089 return -ERANGE;
1090
1091 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1092 oobregion->length = mtd->oobsize - oobregion->offset;
1093
1094 return 0;
1095 }
1096
1097 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1098 .ecc = denali_ooblayout_ecc,
1099 .free = denali_ooblayout_free,
1100 };
1101
1102 static int denali_multidev_fixup(struct nand_chip *chip)
1103 {
1104 struct denali_nand_info *denali = to_denali(chip);
1105 struct mtd_info *mtd = nand_to_mtd(chip);
1106 struct nand_memory_organization *memorg;
1107
1108 memorg = nanddev_get_memorg(&chip->base);
1109
1110 /*
1111 * Support for multi device:
1112 * When the IP configuration is x16 capable and two x8 chips are
1113 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1114 * In this case, the core framework knows nothing about this fact,
1115 * so we should tell it the _logical_ pagesize and anything necessary.
1116 */
1117 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1118
1119 /*
1120 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1121 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1122 */
1123 if (denali->devs_per_cs == 0) {
1124 denali->devs_per_cs = 1;
1125 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1126 }
1127
1128 if (denali->devs_per_cs == 1)
1129 return 0;
1130
1131 if (denali->devs_per_cs != 2) {
1132 dev_err(denali->dev, "unsupported number of devices %d\n",
1133 denali->devs_per_cs);
1134 return -EINVAL;
1135 }
1136
1137 /* 2 chips in parallel */
1138 memorg->pagesize <<= 1;
1139 memorg->oobsize <<= 1;
1140 mtd->size <<= 1;
1141 mtd->erasesize <<= 1;
1142 mtd->writesize <<= 1;
1143 mtd->oobsize <<= 1;
1144 chip->page_shift += 1;
1145 chip->phys_erase_shift += 1;
1146 chip->bbt_erase_shift += 1;
1147 chip->chip_shift += 1;
1148 chip->pagemask <<= 1;
1149 chip->ecc.size <<= 1;
1150 chip->ecc.bytes <<= 1;
1151 chip->ecc.strength <<= 1;
1152 denali->oob_skip_bytes <<= 1;
1153
1154 return 0;
1155 }
1156
1157 static int denali_attach_chip(struct nand_chip *chip)
1158 {
1159 struct mtd_info *mtd = nand_to_mtd(chip);
1160 struct denali_nand_info *denali = mtd_to_denali(mtd);
1161 int ret;
1162
1163 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1164 denali->dma_avail = 1;
1165
1166 if (denali->dma_avail) {
1167 int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
1168
1169 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
1170 if (ret) {
1171 dev_info(denali->dev,
1172 "Failed to set DMA mask. Disabling DMA.\n");
1173 denali->dma_avail = 0;
1174 }
1175 }
1176
1177 if (denali->dma_avail) {
1178 chip->options |= NAND_USE_BOUNCE_BUFFER;
1179 chip->buf_align = 16;
1180 if (denali->caps & DENALI_CAP_DMA_64BIT)
1181 denali->setup_dma = denali_setup_dma64;
1182 else
1183 denali->setup_dma = denali_setup_dma32;
1184 }
1185
1186 chip->bbt_options |= NAND_BBT_USE_FLASH;
1187 chip->bbt_options |= NAND_BBT_NO_OOB;
1188 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
1189 chip->options |= NAND_NO_SUBPAGE_WRITE;
1190
1191 ret = nand_ecc_choose_conf(chip, denali->ecc_caps,
1192 mtd->oobsize - denali->oob_skip_bytes);
1193 if (ret) {
1194 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1195 return ret;
1196 }
1197
1198 dev_dbg(denali->dev,
1199 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1200 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1201
1202 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1203 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1204 denali->reg + ECC_CORRECTION);
1205 iowrite32(mtd->erasesize / mtd->writesize,
1206 denali->reg + PAGES_PER_BLOCK);
1207 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1208 denali->reg + DEVICE_WIDTH);
1209 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1210 denali->reg + TWO_ROW_ADDR_CYCLES);
1211 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1212 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1213
1214 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1215 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1216 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1217 iowrite32(mtd->writesize / chip->ecc.size,
1218 denali->reg + CFG_NUM_DATA_BLOCKS);
1219
1220 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1221
1222 if (chip->options & NAND_BUSWIDTH_16) {
1223 chip->legacy.read_buf = denali_read_buf16;
1224 chip->legacy.write_buf = denali_write_buf16;
1225 } else {
1226 chip->legacy.read_buf = denali_read_buf;
1227 chip->legacy.write_buf = denali_write_buf;
1228 }
1229 chip->ecc.read_page = denali_read_page;
1230 chip->ecc.read_page_raw = denali_read_page_raw;
1231 chip->ecc.write_page = denali_write_page;
1232 chip->ecc.write_page_raw = denali_write_page_raw;
1233 chip->ecc.read_oob = denali_read_oob;
1234 chip->ecc.write_oob = denali_write_oob;
1235
1236 ret = denali_multidev_fixup(chip);
1237 if (ret)
1238 return ret;
1239
1240 /*
1241 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1242 * use devm_kmalloc() because the memory allocated by devm_ does not
1243 * guarantee DMA-safe alignment.
1244 */
1245 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1246 if (!denali->buf)
1247 return -ENOMEM;
1248
1249 return 0;
1250 }
1251
1252 static void denali_detach_chip(struct nand_chip *chip)
1253 {
1254 struct mtd_info *mtd = nand_to_mtd(chip);
1255 struct denali_nand_info *denali = mtd_to_denali(mtd);
1256
1257 kfree(denali->buf);
1258 }
1259
1260 static const struct nand_controller_ops denali_controller_ops = {
1261 .attach_chip = denali_attach_chip,
1262 .detach_chip = denali_detach_chip,
1263 .setup_data_interface = denali_setup_data_interface,
1264 };
1265
1266 int denali_init(struct denali_nand_info *denali)
1267 {
1268 struct nand_chip *chip = &denali->nand;
1269 struct mtd_info *mtd = nand_to_mtd(chip);
1270 u32 features = ioread32(denali->reg + FEATURES);
1271 int ret;
1272
1273 mtd->dev.parent = denali->dev;
1274 denali_hw_init(denali);
1275
1276 init_completion(&denali->complete);
1277 spin_lock_init(&denali->irq_lock);
1278
1279 denali_clear_irq_all(denali);
1280
1281 ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
1282 IRQF_SHARED, DENALI_NAND_NAME, denali);
1283 if (ret) {
1284 dev_err(denali->dev, "Unable to request IRQ\n");
1285 return ret;
1286 }
1287
1288 denali_enable_irq(denali);
1289
1290 denali->active_bank = DENALI_INVALID_BANK;
1291
1292 nand_set_flash_node(chip, denali->dev->of_node);
1293 /* Fallback to the default name if DT did not give "label" property */
1294 if (!mtd->name)
1295 mtd->name = "denali-nand";
1296
1297 chip->legacy.select_chip = denali_select_chip;
1298 chip->legacy.read_byte = denali_read_byte;
1299 chip->legacy.write_byte = denali_write_byte;
1300 chip->legacy.cmd_ctrl = denali_cmd_ctrl;
1301 chip->legacy.waitfunc = denali_waitfunc;
1302
1303 if (features & FEATURES__INDEX_ADDR) {
1304 denali->host_read = denali_indexed_read;
1305 denali->host_write = denali_indexed_write;
1306 } else {
1307 denali->host_read = denali_direct_read;
1308 denali->host_write = denali_direct_write;
1309 }
1310
1311 /* clk rate info is needed for setup_data_interface */
1312 if (!denali->clk_rate || !denali->clk_x_rate)
1313 chip->options |= NAND_KEEP_TIMINGS;
1314
1315 chip->legacy.dummy_controller.ops = &denali_controller_ops;
1316 ret = nand_scan(chip, denali->max_banks);
1317 if (ret)
1318 goto disable_irq;
1319
1320 ret = mtd_device_register(mtd, NULL, 0);
1321 if (ret) {
1322 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
1323 goto cleanup_nand;
1324 }
1325
1326 return 0;
1327
1328 cleanup_nand:
1329 nand_cleanup(chip);
1330 disable_irq:
1331 denali_disable_irq(denali);
1332
1333 return ret;
1334 }
1335 EXPORT_SYMBOL(denali_init);
1336
1337 void denali_remove(struct denali_nand_info *denali)
1338 {
1339 nand_release(&denali->nand);
1340 denali_disable_irq(denali);
1341 }
1342 EXPORT_SYMBOL(denali_remove);
1343
1344 MODULE_DESCRIPTION("Driver core for Denali NAND controller");
1345 MODULE_AUTHOR("Intel Corporation and its suppliers");
1346 MODULE_LICENSE("GPL v2");
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