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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / drivers / mtd / nand / tegra_nand.c
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27 #include <asm/io.h>
28 #include <nand.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/funcmux.h>
31 #include <asm/arch-tegra/clk_rst.h>
32 #include <asm/errno.h>
33 #include <asm/gpio.h>
34 #include <fdtdec.h>
35 #include "tegra_nand.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #define NAND_CMD_TIMEOUT_MS 10
40
41 #define SKIPPED_SPARE_BYTES 4
42
43 /* ECC bytes to be generated for tag data */
44 #define TAG_ECC_BYTES 4
45
46 /* 64 byte oob block info for large page (== 2KB) device
47 *
48 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
49 * Skipped bytes(4)
50 * Main area Ecc(36)
51 * Tag data(20)
52 * Tag data Ecc(4)
53 *
54 * Yaffs2 will use 16 tag bytes.
55 */
56 static struct nand_ecclayout eccoob = {
57 .eccbytes = 36,
58 .eccpos = {
59 4, 5, 6, 7, 8, 9, 10, 11, 12,
60 13, 14, 15, 16, 17, 18, 19, 20, 21,
61 22, 23, 24, 25, 26, 27, 28, 29, 30,
62 31, 32, 33, 34, 35, 36, 37, 38, 39,
63 },
64 .oobavail = 20,
65 .oobfree = {
66 {
67 .offset = 40,
68 .length = 20,
69 },
70 }
71 };
72
73 enum {
74 ECC_OK,
75 ECC_TAG_ERROR = 1 << 0,
76 ECC_DATA_ERROR = 1 << 1
77 };
78
79 /* Timing parameters */
80 enum {
81 FDT_NAND_MAX_TRP_TREA,
82 FDT_NAND_TWB,
83 FDT_NAND_MAX_TCR_TAR_TRR,
84 FDT_NAND_TWHR,
85 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
86 FDT_NAND_TWH,
87 FDT_NAND_TWP,
88 FDT_NAND_TRH,
89 FDT_NAND_TADL,
90
91 FDT_NAND_TIMING_COUNT
92 };
93
94 /* Information about an attached NAND chip */
95 struct fdt_nand {
96 struct nand_ctlr *reg;
97 int enabled; /* 1 to enable, 0 to disable */
98 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
99 s32 width; /* bit width, normally 8 */
100 u32 timing[FDT_NAND_TIMING_COUNT];
101 };
102
103 struct nand_drv {
104 struct nand_ctlr *reg;
105
106 /*
107 * When running in PIO mode to get READ ID bytes from register
108 * RESP_0, we need this variable as an index to know which byte in
109 * register RESP_0 should be read.
110 * Because common code in nand_base.c invokes read_byte function two
111 * times for NAND_CMD_READID.
112 * And our controller returns 4 bytes at once in register RESP_0.
113 */
114 int pio_byte_index;
115 struct fdt_nand config;
116 };
117
118 static struct nand_drv nand_ctrl;
119 static struct mtd_info *our_mtd;
120 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
121
122 #ifdef CONFIG_SYS_DCACHE_OFF
123 static inline void dma_prepare(void *start, unsigned long length,
124 int is_writing)
125 {
126 }
127 #else
128 /**
129 * Prepare for a DMA transaction
130 *
131 * For a write we flush out our data. For a read we invalidate, since we
132 * need to do this before we read from the buffer after the DMA has
133 * completed, so may as well do it now.
134 *
135 * @param start Start address for DMA buffer (should be cache-aligned)
136 * @param length Length of DMA buffer in bytes
137 * @param is_writing 0 if reading, non-zero if writing
138 */
139 static void dma_prepare(void *start, unsigned long length, int is_writing)
140 {
141 unsigned long addr = (unsigned long)start;
142
143 length = ALIGN(length, ARCH_DMA_MINALIGN);
144 if (is_writing)
145 flush_dcache_range(addr, addr + length);
146 else
147 invalidate_dcache_range(addr, addr + length);
148 }
149 #endif
150
151 /**
152 * Wait for command completion
153 *
154 * @param reg nand_ctlr structure
155 * @return
156 * 1 - Command completed
157 * 0 - Timeout
158 */
159 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
160 {
161 u32 reg_val;
162 int running;
163 int i;
164
165 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
166 if ((readl(&reg->command) & CMD_GO) ||
167 !(readl(&reg->status) & STATUS_RBSY0) ||
168 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
169 udelay(1);
170 continue;
171 }
172 reg_val = readl(&reg->dma_mst_ctrl);
173 /*
174 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
175 * is set, that means DMA engine is running.
176 *
177 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
178 * is cleared, indicating DMA transfer completion.
179 */
180 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
181 DMA_MST_CTRL_EN_B_ENABLE);
182 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
183 return 1;
184 udelay(1);
185 }
186 return 0;
187 }
188
189 /**
190 * Read one byte from the chip
191 *
192 * @param mtd MTD device structure
193 * @return data byte
194 *
195 * Read function for 8bit bus-width
196 */
197 static uint8_t read_byte(struct mtd_info *mtd)
198 {
199 struct nand_chip *chip = mtd->priv;
200 u32 dword_read;
201 struct nand_drv *info;
202
203 info = (struct nand_drv *)chip->priv;
204
205 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
206 if (info->pio_byte_index > 3) {
207 info->pio_byte_index = 0;
208 writel(CMD_GO | CMD_PIO
209 | CMD_RX | CMD_CE0,
210 &info->reg->command);
211 if (!nand_waitfor_cmd_completion(info->reg))
212 printf("Command timeout\n");
213 }
214
215 dword_read = readl(&info->reg->resp);
216 dword_read = dword_read >> (8 * info->pio_byte_index);
217 info->pio_byte_index++;
218 return (uint8_t)dword_read;
219 }
220
221 /**
222 * Read len bytes from the chip into a buffer
223 *
224 * @param mtd MTD device structure
225 * @param buf buffer to store data to
226 * @param len number of bytes to read
227 *
228 * Read function for 8bit bus-width
229 */
230 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
231 {
232 int i, s;
233 unsigned int reg;
234 struct nand_chip *chip = mtd->priv;
235 struct nand_drv *info = (struct nand_drv *)chip->priv;
236
237 for (i = 0; i < len; i += 4) {
238 s = (len - i) > 4 ? 4 : len - i;
239 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
240 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
241 &info->reg->command);
242 if (!nand_waitfor_cmd_completion(info->reg))
243 puts("Command timeout during read_buf\n");
244 reg = readl(&info->reg->resp);
245 memcpy(buf + i, &reg, s);
246 }
247 }
248
249 /**
250 * Check NAND status to see if it is ready or not
251 *
252 * @param mtd MTD device structure
253 * @return
254 * 1 - ready
255 * 0 - not ready
256 */
257 static int nand_dev_ready(struct mtd_info *mtd)
258 {
259 struct nand_chip *chip = mtd->priv;
260 int reg_val;
261 struct nand_drv *info;
262
263 info = (struct nand_drv *)chip->priv;
264
265 reg_val = readl(&info->reg->status);
266 if (reg_val & STATUS_RBSY0)
267 return 1;
268 else
269 return 0;
270 }
271
272 /* Dummy implementation: we don't support multiple chips */
273 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
274 {
275 switch (chipnr) {
276 case -1:
277 case 0:
278 break;
279
280 default:
281 BUG();
282 }
283 }
284
285 /**
286 * Clear all interrupt status bits
287 *
288 * @param reg nand_ctlr structure
289 */
290 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
291 {
292 u32 reg_val;
293
294 /* Clear interrupt status */
295 reg_val = readl(&reg->isr);
296 writel(reg_val, &reg->isr);
297 }
298
299 /**
300 * Send command to NAND device
301 *
302 * @param mtd MTD device structure
303 * @param command the command to be sent
304 * @param column the column address for this command, -1 if none
305 * @param page_addr the page address for this command, -1 if none
306 */
307 static void nand_command(struct mtd_info *mtd, unsigned int command,
308 int column, int page_addr)
309 {
310 struct nand_chip *chip = mtd->priv;
311 struct nand_drv *info;
312
313 info = (struct nand_drv *)chip->priv;
314
315 /*
316 * Write out the command to the device.
317 *
318 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
319 * here before mtd->writesize is initialized.
320 */
321
322 /* Emulate NAND_CMD_READOOB */
323 if (command == NAND_CMD_READOOB) {
324 assert(mtd->writesize != 0);
325 column += mtd->writesize;
326 command = NAND_CMD_READ0;
327 }
328
329 /* Adjust columns for 16 bit bus-width */
330 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
331 column >>= 1;
332
333 nand_clear_interrupt_status(info->reg);
334
335 /* Stop DMA engine, clear DMA completion status */
336 writel(DMA_MST_CTRL_EN_A_DISABLE
337 | DMA_MST_CTRL_EN_B_DISABLE
338 | DMA_MST_CTRL_IS_DMA_DONE,
339 &info->reg->dma_mst_ctrl);
340
341 /*
342 * Program and erase have their own busy handlers
343 * status and sequential in needs no delay
344 */
345 switch (command) {
346 case NAND_CMD_READID:
347 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
348 writel(column & 0xFF, &info->reg->addr_reg1);
349 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
350 | CMD_RX |
351 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
352 | CMD_CE0,
353 &info->reg->command);
354 info->pio_byte_index = 0;
355 break;
356 case NAND_CMD_PARAM:
357 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
358 writel(column & 0xFF, &info->reg->addr_reg1);
359 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
360 &info->reg->command);
361 break;
362 case NAND_CMD_READ0:
363 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
364 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
365 writel((page_addr << 16) | (column & 0xFFFF),
366 &info->reg->addr_reg1);
367 writel(page_addr >> 16, &info->reg->addr_reg2);
368 return;
369 case NAND_CMD_SEQIN:
370 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
371 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
372 writel((page_addr << 16) | (column & 0xFFFF),
373 &info->reg->addr_reg1);
374 writel(page_addr >> 16,
375 &info->reg->addr_reg2);
376 return;
377 case NAND_CMD_PAGEPROG:
378 return;
379 case NAND_CMD_ERASE1:
380 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
381 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
382 writel(page_addr, &info->reg->addr_reg1);
383 writel(CMD_GO | CMD_CLE | CMD_ALE |
384 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
385 &info->reg->command);
386 break;
387 case NAND_CMD_ERASE2:
388 return;
389 case NAND_CMD_STATUS:
390 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
391 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
392 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
393 | CMD_CE0,
394 &info->reg->command);
395 info->pio_byte_index = 0;
396 break;
397 case NAND_CMD_RESET:
398 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
399 writel(CMD_GO | CMD_CLE | CMD_CE0,
400 &info->reg->command);
401 break;
402 case NAND_CMD_RNDOUT:
403 default:
404 printf("%s: Unsupported command %d\n", __func__, command);
405 return;
406 }
407 if (!nand_waitfor_cmd_completion(info->reg))
408 printf("Command 0x%02X timeout\n", command);
409 }
410
411 /**
412 * Check whether the pointed buffer are all 0xff (blank).
413 *
414 * @param buf data buffer for blank check
415 * @param len length of the buffer in byte
416 * @return
417 * 1 - blank
418 * 0 - non-blank
419 */
420 static int blank_check(u8 *buf, int len)
421 {
422 int i;
423
424 for (i = 0; i < len; i++)
425 if (buf[i] != 0xFF)
426 return 0;
427 return 1;
428 }
429
430 /**
431 * After a DMA transfer for read, we call this function to see whether there
432 * is any uncorrectable error on the pointed data buffer or oob buffer.
433 *
434 * @param reg nand_ctlr structure
435 * @param databuf data buffer
436 * @param a_len data buffer length
437 * @param oobbuf oob buffer
438 * @param b_len oob buffer length
439 * @return
440 * ECC_OK - no ECC error or correctable ECC error
441 * ECC_TAG_ERROR - uncorrectable tag ECC error
442 * ECC_DATA_ERROR - uncorrectable data ECC error
443 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
444 */
445 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
446 int a_len, u8 *oobbuf, int b_len)
447 {
448 int return_val = ECC_OK;
449 u32 reg_val;
450
451 if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
452 return ECC_OK;
453
454 /*
455 * Area A is used for the data block (databuf). Area B is used for
456 * the spare block (oobbuf)
457 */
458 reg_val = readl(&reg->dec_status);
459 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
460 reg_val = readl(&reg->bch_dec_status_buf);
461 /*
462 * If uncorrectable error occurs on data area, then see whether
463 * they are all FF. If all are FF, it's a blank page.
464 * Not error.
465 */
466 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
467 !blank_check(databuf, a_len))
468 return_val |= ECC_DATA_ERROR;
469 }
470
471 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
472 reg_val = readl(&reg->bch_dec_status_buf);
473 /*
474 * If uncorrectable error occurs on tag area, then see whether
475 * they are all FF. If all are FF, it's a blank page.
476 * Not error.
477 */
478 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
479 !blank_check(oobbuf, b_len))
480 return_val |= ECC_TAG_ERROR;
481 }
482
483 return return_val;
484 }
485
486 /**
487 * Set GO bit to send command to device
488 *
489 * @param reg nand_ctlr structure
490 */
491 static void start_command(struct nand_ctlr *reg)
492 {
493 u32 reg_val;
494
495 reg_val = readl(&reg->command);
496 reg_val |= CMD_GO;
497 writel(reg_val, &reg->command);
498 }
499
500 /**
501 * Clear command GO bit, DMA GO bit, and DMA completion status
502 *
503 * @param reg nand_ctlr structure
504 */
505 static void stop_command(struct nand_ctlr *reg)
506 {
507 /* Stop command */
508 writel(0, &reg->command);
509
510 /* Stop DMA engine and clear DMA completion status */
511 writel(DMA_MST_CTRL_GO_DISABLE
512 | DMA_MST_CTRL_IS_DMA_DONE,
513 &reg->dma_mst_ctrl);
514 }
515
516 /**
517 * Set up NAND bus width and page size
518 *
519 * @param info nand_info structure
520 * @param *reg_val address of reg_val
521 * @return 0 if ok, -1 on error
522 */
523 static int set_bus_width_page_size(struct fdt_nand *config,
524 u32 *reg_val)
525 {
526 if (config->width == 8)
527 *reg_val = CFG_BUS_WIDTH_8BIT;
528 else if (config->width == 16)
529 *reg_val = CFG_BUS_WIDTH_16BIT;
530 else {
531 debug("%s: Unsupported bus width %d\n", __func__,
532 config->width);
533 return -1;
534 }
535
536 if (our_mtd->writesize == 512)
537 *reg_val |= CFG_PAGE_SIZE_512;
538 else if (our_mtd->writesize == 2048)
539 *reg_val |= CFG_PAGE_SIZE_2048;
540 else if (our_mtd->writesize == 4096)
541 *reg_val |= CFG_PAGE_SIZE_4096;
542 else {
543 debug("%s: Unsupported page size %d\n", __func__,
544 our_mtd->writesize);
545 return -1;
546 }
547
548 return 0;
549 }
550
551 /**
552 * Page read/write function
553 *
554 * @param mtd mtd info structure
555 * @param chip nand chip info structure
556 * @param buf data buffer
557 * @param page page number
558 * @param with_ecc 1 to enable ECC, 0 to disable ECC
559 * @param is_writing 0 for read, 1 for write
560 * @return 0 when successfully completed
561 * -EIO when command timeout
562 */
563 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
564 uint8_t *buf, int page, int with_ecc, int is_writing)
565 {
566 u32 reg_val;
567 int tag_size;
568 struct nand_oobfree *free = chip->ecc.layout->oobfree;
569 /* 4*128=512 (byte) is the value that our HW can support. */
570 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
571 char *tag_ptr;
572 struct nand_drv *info;
573 struct fdt_nand *config;
574
575 if ((uintptr_t)buf & 0x03) {
576 printf("buf %p has to be 4-byte aligned\n", buf);
577 return -EINVAL;
578 }
579
580 info = (struct nand_drv *)chip->priv;
581 config = &info->config;
582 if (set_bus_width_page_size(config, &reg_val))
583 return -EINVAL;
584
585 /* Need to be 4-byte aligned */
586 tag_ptr = (char *)tag_buf;
587
588 stop_command(info->reg);
589
590 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
591 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
592
593 if (with_ecc) {
594 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
595 if (is_writing)
596 memcpy(tag_ptr, chip->oob_poi + free->offset,
597 chip->ecc.layout->oobavail +
598 TAG_ECC_BYTES);
599 } else {
600 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
601 }
602
603 /* Set ECC selection, configure ECC settings */
604 if (with_ecc) {
605 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
606 reg_val |= (CFG_SKIP_SPARE_SEL_4
607 | CFG_SKIP_SPARE_ENABLE
608 | CFG_HW_ECC_CORRECTION_ENABLE
609 | CFG_ECC_EN_TAG_DISABLE
610 | CFG_HW_ECC_SEL_RS
611 | CFG_HW_ECC_ENABLE
612 | CFG_TVAL4
613 | (tag_size - 1));
614
615 if (!is_writing)
616 tag_size += SKIPPED_SPARE_BYTES;
617 dma_prepare(tag_ptr, tag_size, is_writing);
618 } else {
619 tag_size = mtd->oobsize;
620 reg_val |= (CFG_SKIP_SPARE_DISABLE
621 | CFG_HW_ECC_CORRECTION_DISABLE
622 | CFG_ECC_EN_TAG_DISABLE
623 | CFG_HW_ECC_DISABLE
624 | (tag_size - 1));
625 dma_prepare(chip->oob_poi, tag_size, is_writing);
626 }
627 writel(reg_val, &info->reg->config);
628
629 dma_prepare(buf, 1 << chip->page_shift, is_writing);
630
631 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
632
633 writel(tag_size - 1, &info->reg->dma_cfg_b);
634
635 nand_clear_interrupt_status(info->reg);
636
637 reg_val = CMD_CLE | CMD_ALE
638 | CMD_SEC_CMD
639 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
640 | CMD_A_VALID
641 | CMD_B_VALID
642 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
643 | CMD_CE0;
644 if (!is_writing)
645 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
646 else
647 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
648 writel(reg_val, &info->reg->command);
649
650 /* Setup DMA engine */
651 reg_val = DMA_MST_CTRL_GO_ENABLE
652 | DMA_MST_CTRL_BURST_8WORDS
653 | DMA_MST_CTRL_EN_A_ENABLE
654 | DMA_MST_CTRL_EN_B_ENABLE;
655
656 if (!is_writing)
657 reg_val |= DMA_MST_CTRL_DIR_READ;
658 else
659 reg_val |= DMA_MST_CTRL_DIR_WRITE;
660
661 writel(reg_val, &info->reg->dma_mst_ctrl);
662
663 start_command(info->reg);
664
665 if (!nand_waitfor_cmd_completion(info->reg)) {
666 if (!is_writing)
667 printf("Read Page 0x%X timeout ", page);
668 else
669 printf("Write Page 0x%X timeout ", page);
670 if (with_ecc)
671 printf("with ECC");
672 else
673 printf("without ECC");
674 printf("\n");
675 return -EIO;
676 }
677
678 if (with_ecc && !is_writing) {
679 memcpy(chip->oob_poi, tag_ptr,
680 SKIPPED_SPARE_BYTES);
681 memcpy(chip->oob_poi + free->offset,
682 tag_ptr + SKIPPED_SPARE_BYTES,
683 chip->ecc.layout->oobavail);
684 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
685 1 << chip->page_shift,
686 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
687 chip->ecc.layout->oobavail);
688 if (reg_val & ECC_TAG_ERROR)
689 printf("Read Page 0x%X tag ECC error\n", page);
690 if (reg_val & ECC_DATA_ERROR)
691 printf("Read Page 0x%X data ECC error\n",
692 page);
693 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
694 return -EIO;
695 }
696 return 0;
697 }
698
699 /**
700 * Hardware ecc based page read function
701 *
702 * @param mtd mtd info structure
703 * @param chip nand chip info structure
704 * @param buf buffer to store read data
705 * @param page page number to read
706 * @return 0 when successfully completed
707 * -EIO when command timeout
708 */
709 static int nand_read_page_hwecc(struct mtd_info *mtd,
710 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
711 {
712 return nand_rw_page(mtd, chip, buf, page, 1, 0);
713 }
714
715 /**
716 * Hardware ecc based page write function
717 *
718 * @param mtd mtd info structure
719 * @param chip nand chip info structure
720 * @param buf data buffer
721 */
722 static int nand_write_page_hwecc(struct mtd_info *mtd,
723 struct nand_chip *chip, const uint8_t *buf, int oob_required)
724 {
725 int page;
726 struct nand_drv *info;
727
728 info = (struct nand_drv *)chip->priv;
729
730 page = (readl(&info->reg->addr_reg1) >> 16) |
731 (readl(&info->reg->addr_reg2) << 16);
732
733 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
734 return 0;
735 }
736
737
738 /**
739 * Read raw page data without ecc
740 *
741 * @param mtd mtd info structure
742 * @param chip nand chip info structure
743 * @param buf buffer to store read data
744 * @param page page number to read
745 * @return 0 when successfully completed
746 * -EINVAL when chip->oob_poi is not double-word aligned
747 * -EIO when command timeout
748 */
749 static int nand_read_page_raw(struct mtd_info *mtd,
750 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
751 {
752 return nand_rw_page(mtd, chip, buf, page, 0, 0);
753 }
754
755 /**
756 * Raw page write function
757 *
758 * @param mtd mtd info structure
759 * @param chip nand chip info structure
760 * @param buf data buffer
761 */
762 static int nand_write_page_raw(struct mtd_info *mtd,
763 struct nand_chip *chip, const uint8_t *buf, int oob_required)
764 {
765 int page;
766 struct nand_drv *info;
767
768 info = (struct nand_drv *)chip->priv;
769 page = (readl(&info->reg->addr_reg1) >> 16) |
770 (readl(&info->reg->addr_reg2) << 16);
771
772 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
773 return 0;
774 }
775
776 /**
777 * OOB data read/write function
778 *
779 * @param mtd mtd info structure
780 * @param chip nand chip info structure
781 * @param page page number to read
782 * @param with_ecc 1 to enable ECC, 0 to disable ECC
783 * @param is_writing 0 for read, 1 for write
784 * @return 0 when successfully completed
785 * -EINVAL when chip->oob_poi is not double-word aligned
786 * -EIO when command timeout
787 */
788 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
789 int page, int with_ecc, int is_writing)
790 {
791 u32 reg_val;
792 int tag_size;
793 struct nand_oobfree *free = chip->ecc.layout->oobfree;
794 struct nand_drv *info;
795
796 if (((int)chip->oob_poi) & 0x03)
797 return -EINVAL;
798 info = (struct nand_drv *)chip->priv;
799 if (set_bus_width_page_size(&info->config, &reg_val))
800 return -EINVAL;
801
802 stop_command(info->reg);
803
804 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
805
806 /* Set ECC selection */
807 tag_size = mtd->oobsize;
808 if (with_ecc)
809 reg_val |= CFG_ECC_EN_TAG_ENABLE;
810 else
811 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
812
813 reg_val |= ((tag_size - 1) |
814 CFG_SKIP_SPARE_DISABLE |
815 CFG_HW_ECC_CORRECTION_DISABLE |
816 CFG_HW_ECC_DISABLE);
817 writel(reg_val, &info->reg->config);
818
819 dma_prepare(chip->oob_poi, tag_size, is_writing);
820
821 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
822
823 if (is_writing && with_ecc)
824 tag_size -= TAG_ECC_BYTES;
825
826 writel(tag_size - 1, &info->reg->dma_cfg_b);
827
828 nand_clear_interrupt_status(info->reg);
829
830 reg_val = CMD_CLE | CMD_ALE
831 | CMD_SEC_CMD
832 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
833 | CMD_B_VALID
834 | CMD_CE0;
835 if (!is_writing)
836 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
837 else
838 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
839 writel(reg_val, &info->reg->command);
840
841 /* Setup DMA engine */
842 reg_val = DMA_MST_CTRL_GO_ENABLE
843 | DMA_MST_CTRL_BURST_8WORDS
844 | DMA_MST_CTRL_EN_B_ENABLE;
845 if (!is_writing)
846 reg_val |= DMA_MST_CTRL_DIR_READ;
847 else
848 reg_val |= DMA_MST_CTRL_DIR_WRITE;
849
850 writel(reg_val, &info->reg->dma_mst_ctrl);
851
852 start_command(info->reg);
853
854 if (!nand_waitfor_cmd_completion(info->reg)) {
855 if (!is_writing)
856 printf("Read OOB of Page 0x%X timeout\n", page);
857 else
858 printf("Write OOB of Page 0x%X timeout\n", page);
859 return -EIO;
860 }
861
862 if (with_ecc && !is_writing) {
863 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
864 (u8 *)(chip->oob_poi + free->offset),
865 chip->ecc.layout->oobavail);
866 if (reg_val & ECC_TAG_ERROR)
867 printf("Read OOB of Page 0x%X tag ECC error\n", page);
868 }
869 return 0;
870 }
871
872 /**
873 * OOB data read function
874 *
875 * @param mtd mtd info structure
876 * @param chip nand chip info structure
877 * @param page page number to read
878 */
879 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
880 int page)
881 {
882 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
883 nand_rw_oob(mtd, chip, page, 0, 0);
884 return 0;
885 }
886
887 /**
888 * OOB data write function
889 *
890 * @param mtd mtd info structure
891 * @param chip nand chip info structure
892 * @param page page number to write
893 * @return 0 when successfully completed
894 * -EINVAL when chip->oob_poi is not double-word aligned
895 * -EIO when command timeout
896 */
897 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
898 int page)
899 {
900 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
901
902 return nand_rw_oob(mtd, chip, page, 0, 1);
903 }
904
905 /**
906 * Set up NAND memory timings according to the provided parameters
907 *
908 * @param timing Timing parameters
909 * @param reg NAND controller register address
910 */
911 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
912 struct nand_ctlr *reg)
913 {
914 u32 reg_val, clk_rate, clk_period, time_val;
915
916 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
917 CLOCK_ID_PERIPH) / 1000000;
918 clk_period = 1000 / clk_rate;
919 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
920 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
921 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
922 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
923 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
924 if (time_val > 2)
925 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
926 TIMING_TCR_TAR_TRR_CNT_MASK;
927 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
928 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
929 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
930 if (time_val > 1)
931 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
932 TIMING_TCS_CNT_MASK;
933 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
934 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
935 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
936 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
937 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
938 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
939 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
940 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
941 writel(reg_val, &reg->timing);
942
943 reg_val = 0;
944 time_val = timing[FDT_NAND_TADL] / clk_period;
945 if (time_val > 2)
946 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
947 writel(reg_val, &reg->timing2);
948 }
949
950 /**
951 * Decode NAND parameters from the device tree
952 *
953 * @param blob Device tree blob
954 * @param node Node containing "nand-flash" compatble node
955 * @return 0 if ok, -ve on error (FDT_ERR_...)
956 */
957 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
958 {
959 int err;
960
961 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
962 config->enabled = fdtdec_get_is_enabled(blob, node);
963 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
964 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
965 &config->wp_gpio);
966 if (err)
967 return err;
968 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
969 config->timing, FDT_NAND_TIMING_COUNT);
970 if (err < 0)
971 return err;
972
973 /* Now look up the controller and decode that */
974 node = fdt_next_node(blob, node, NULL);
975 if (node < 0)
976 return node;
977
978 return 0;
979 }
980
981 /**
982 * Board-specific NAND initialization
983 *
984 * @param nand nand chip info structure
985 * @return 0, after initialized, -1 on error
986 */
987 int tegra_nand_init(struct nand_chip *nand, int devnum)
988 {
989 struct nand_drv *info = &nand_ctrl;
990 struct fdt_nand *config = &info->config;
991 int node, ret;
992
993 node = fdtdec_next_compatible(gd->fdt_blob, 0,
994 COMPAT_NVIDIA_TEGRA20_NAND);
995 if (node < 0)
996 return -1;
997 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
998 printf("Could not decode nand-flash in device tree\n");
999 return -1;
1000 }
1001 if (!config->enabled)
1002 return -1;
1003 info->reg = config->reg;
1004 nand->ecc.mode = NAND_ECC_HW;
1005 nand->ecc.layout = &eccoob;
1006
1007 nand->options = LP_OPTIONS;
1008 nand->cmdfunc = nand_command;
1009 nand->read_byte = read_byte;
1010 nand->read_buf = read_buf;
1011 nand->ecc.read_page = nand_read_page_hwecc;
1012 nand->ecc.write_page = nand_write_page_hwecc;
1013 nand->ecc.read_page_raw = nand_read_page_raw;
1014 nand->ecc.write_page_raw = nand_write_page_raw;
1015 nand->ecc.read_oob = nand_read_oob;
1016 nand->ecc.write_oob = nand_write_oob;
1017 nand->ecc.strength = 1;
1018 nand->select_chip = nand_select_chip;
1019 nand->dev_ready = nand_dev_ready;
1020 nand->priv = &nand_ctrl;
1021
1022 /* Adjust controller clock rate */
1023 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
1024
1025 /* Adjust timing for NAND device */
1026 setup_timing(config->timing, info->reg);
1027
1028 fdtdec_setup_gpio(&config->wp_gpio);
1029 gpio_direction_output(config->wp_gpio.gpio, 1);
1030
1031 our_mtd = &nand_info[devnum];
1032 our_mtd->priv = nand;
1033 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1034 if (ret)
1035 return ret;
1036
1037 nand->ecc.size = our_mtd->writesize;
1038 nand->ecc.bytes = our_mtd->oobsize;
1039
1040 ret = nand_scan_tail(our_mtd);
1041 if (ret)
1042 return ret;
1043
1044 ret = nand_register(devnum);
1045 if (ret)
1046 return ret;
1047
1048 return 0;
1049 }
1050
1051 void board_nand_init(void)
1052 {
1053 struct nand_chip *nand = &nand_chip[0];
1054
1055 if (tegra_nand_init(nand, 0))
1056 puts("Tegra NAND init failed\n");
1057 }
"Das U-Boot" Source Tree