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[people/ms/u-boot.git] / drivers / mtd / nand / tegra_nand.c
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27 #include <asm/io.h>
28 #include <nand.h>
29 #include <asm/arch/clk_rst.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/funcmux.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/errno.h>
34 #include <asm-generic/gpio.h>
35 #include <fdtdec.h>
36 #include "tegra_nand.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #define NAND_CMD_TIMEOUT_MS 10
41
42 #define SKIPPED_SPARE_BYTES 4
43
44 /* ECC bytes to be generated for tag data */
45 #define TAG_ECC_BYTES 4
46
47 /* 64 byte oob block info for large page (== 2KB) device
48 *
49 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
50 * Skipped bytes(4)
51 * Main area Ecc(36)
52 * Tag data(20)
53 * Tag data Ecc(4)
54 *
55 * Yaffs2 will use 16 tag bytes.
56 */
57 static struct nand_ecclayout eccoob = {
58 .eccbytes = 36,
59 .eccpos = {
60 4, 5, 6, 7, 8, 9, 10, 11, 12,
61 13, 14, 15, 16, 17, 18, 19, 20, 21,
62 22, 23, 24, 25, 26, 27, 28, 29, 30,
63 31, 32, 33, 34, 35, 36, 37, 38, 39,
64 },
65 .oobavail = 20,
66 .oobfree = {
67 {
68 .offset = 40,
69 .length = 20,
70 },
71 }
72 };
73
74 enum {
75 ECC_OK,
76 ECC_TAG_ERROR = 1 << 0,
77 ECC_DATA_ERROR = 1 << 1
78 };
79
80 /* Timing parameters */
81 enum {
82 FDT_NAND_MAX_TRP_TREA,
83 FDT_NAND_TWB,
84 FDT_NAND_MAX_TCR_TAR_TRR,
85 FDT_NAND_TWHR,
86 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
87 FDT_NAND_TWH,
88 FDT_NAND_TWP,
89 FDT_NAND_TRH,
90 FDT_NAND_TADL,
91
92 FDT_NAND_TIMING_COUNT
93 };
94
95 /* Information about an attached NAND chip */
96 struct fdt_nand {
97 struct nand_ctlr *reg;
98 int enabled; /* 1 to enable, 0 to disable */
99 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
100 s32 width; /* bit width, normally 8 */
101 u32 timing[FDT_NAND_TIMING_COUNT];
102 };
103
104 struct nand_drv {
105 struct nand_ctlr *reg;
106
107 /*
108 * When running in PIO mode to get READ ID bytes from register
109 * RESP_0, we need this variable as an index to know which byte in
110 * register RESP_0 should be read.
111 * Because common code in nand_base.c invokes read_byte function two
112 * times for NAND_CMD_READID.
113 * And our controller returns 4 bytes at once in register RESP_0.
114 */
115 int pio_byte_index;
116 struct fdt_nand config;
117 };
118
119 static struct nand_drv nand_ctrl;
120 static struct mtd_info *our_mtd;
121 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
122
123 #ifdef CONFIG_SYS_DCACHE_OFF
124 static inline void dma_prepare(void *start, unsigned long length,
125 int is_writing)
126 {
127 }
128 #else
129 /**
130 * Prepare for a DMA transaction
131 *
132 * For a write we flush out our data. For a read we invalidate, since we
133 * need to do this before we read from the buffer after the DMA has
134 * completed, so may as well do it now.
135 *
136 * @param start Start address for DMA buffer (should be cache-aligned)
137 * @param length Length of DMA buffer in bytes
138 * @param is_writing 0 if reading, non-zero if writing
139 */
140 static void dma_prepare(void *start, unsigned long length, int is_writing)
141 {
142 unsigned long addr = (unsigned long)start;
143
144 length = ALIGN(length, ARCH_DMA_MINALIGN);
145 if (is_writing)
146 flush_dcache_range(addr, addr + length);
147 else
148 invalidate_dcache_range(addr, addr + length);
149 }
150 #endif
151
152 /**
153 * Wait for command completion
154 *
155 * @param reg nand_ctlr structure
156 * @return
157 * 1 - Command completed
158 * 0 - Timeout
159 */
160 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
161 {
162 u32 reg_val;
163 int running;
164 int i;
165
166 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
167 if ((readl(&reg->command) & CMD_GO) ||
168 !(readl(&reg->status) & STATUS_RBSY0) ||
169 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
170 udelay(1);
171 continue;
172 }
173 reg_val = readl(&reg->dma_mst_ctrl);
174 /*
175 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
176 * is set, that means DMA engine is running.
177 *
178 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
179 * is cleared, indicating DMA transfer completion.
180 */
181 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
182 DMA_MST_CTRL_EN_B_ENABLE);
183 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
184 return 1;
185 udelay(1);
186 }
187 return 0;
188 }
189
190 /**
191 * Read one byte from the chip
192 *
193 * @param mtd MTD device structure
194 * @return data byte
195 *
196 * Read function for 8bit bus-width
197 */
198 static uint8_t read_byte(struct mtd_info *mtd)
199 {
200 struct nand_chip *chip = mtd->priv;
201 u32 dword_read;
202 struct nand_drv *info;
203
204 info = (struct nand_drv *)chip->priv;
205
206 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
207 if (info->pio_byte_index > 3) {
208 info->pio_byte_index = 0;
209 writel(CMD_GO | CMD_PIO
210 | CMD_RX | CMD_CE0,
211 &info->reg->command);
212 if (!nand_waitfor_cmd_completion(info->reg))
213 printf("Command timeout\n");
214 }
215
216 dword_read = readl(&info->reg->resp);
217 dword_read = dword_read >> (8 * info->pio_byte_index);
218 info->pio_byte_index++;
219 return (uint8_t)dword_read;
220 }
221
222 /**
223 * Check NAND status to see if it is ready or not
224 *
225 * @param mtd MTD device structure
226 * @return
227 * 1 - ready
228 * 0 - not ready
229 */
230 static int nand_dev_ready(struct mtd_info *mtd)
231 {
232 struct nand_chip *chip = mtd->priv;
233 int reg_val;
234 struct nand_drv *info;
235
236 info = (struct nand_drv *)chip->priv;
237
238 reg_val = readl(&info->reg->status);
239 if (reg_val & STATUS_RBSY0)
240 return 1;
241 else
242 return 0;
243 }
244
245 /* Dummy implementation: we don't support multiple chips */
246 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
247 {
248 switch (chipnr) {
249 case -1:
250 case 0:
251 break;
252
253 default:
254 BUG();
255 }
256 }
257
258 /**
259 * Clear all interrupt status bits
260 *
261 * @param reg nand_ctlr structure
262 */
263 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
264 {
265 u32 reg_val;
266
267 /* Clear interrupt status */
268 reg_val = readl(&reg->isr);
269 writel(reg_val, &reg->isr);
270 }
271
272 /**
273 * Send command to NAND device
274 *
275 * @param mtd MTD device structure
276 * @param command the command to be sent
277 * @param column the column address for this command, -1 if none
278 * @param page_addr the page address for this command, -1 if none
279 */
280 static void nand_command(struct mtd_info *mtd, unsigned int command,
281 int column, int page_addr)
282 {
283 struct nand_chip *chip = mtd->priv;
284 struct nand_drv *info;
285
286 info = (struct nand_drv *)chip->priv;
287
288 /*
289 * Write out the command to the device.
290 *
291 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
292 * here before mtd->writesize is initialized.
293 */
294
295 /* Emulate NAND_CMD_READOOB */
296 if (command == NAND_CMD_READOOB) {
297 assert(mtd->writesize != 0);
298 column += mtd->writesize;
299 command = NAND_CMD_READ0;
300 }
301
302 /* Adjust columns for 16 bit bus-width */
303 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
304 column >>= 1;
305
306 nand_clear_interrupt_status(info->reg);
307
308 /* Stop DMA engine, clear DMA completion status */
309 writel(DMA_MST_CTRL_EN_A_DISABLE
310 | DMA_MST_CTRL_EN_B_DISABLE
311 | DMA_MST_CTRL_IS_DMA_DONE,
312 &info->reg->dma_mst_ctrl);
313
314 /*
315 * Program and erase have their own busy handlers
316 * status and sequential in needs no delay
317 */
318 switch (command) {
319 case NAND_CMD_READID:
320 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
321 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
322 | CMD_RX |
323 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
324 | CMD_CE0,
325 &info->reg->command);
326 info->pio_byte_index = 0;
327 break;
328 case NAND_CMD_READ0:
329 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
330 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
331 writel((page_addr << 16) | (column & 0xFFFF),
332 &info->reg->addr_reg1);
333 writel(page_addr >> 16, &info->reg->addr_reg2);
334 return;
335 case NAND_CMD_SEQIN:
336 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
337 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
338 writel((page_addr << 16) | (column & 0xFFFF),
339 &info->reg->addr_reg1);
340 writel(page_addr >> 16,
341 &info->reg->addr_reg2);
342 return;
343 case NAND_CMD_PAGEPROG:
344 return;
345 case NAND_CMD_ERASE1:
346 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
347 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
348 writel(page_addr, &info->reg->addr_reg1);
349 writel(CMD_GO | CMD_CLE | CMD_ALE |
350 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
351 &info->reg->command);
352 break;
353 case NAND_CMD_ERASE2:
354 return;
355 case NAND_CMD_STATUS:
356 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
357 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
358 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
359 | CMD_CE0,
360 &info->reg->command);
361 info->pio_byte_index = 0;
362 break;
363 case NAND_CMD_RESET:
364 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
365 writel(CMD_GO | CMD_CLE | CMD_CE0,
366 &info->reg->command);
367 break;
368 case NAND_CMD_RNDOUT:
369 default:
370 printf("%s: Unsupported command %d\n", __func__, command);
371 return;
372 }
373 if (!nand_waitfor_cmd_completion(info->reg))
374 printf("Command 0x%02X timeout\n", command);
375 }
376
377 /**
378 * Check whether the pointed buffer are all 0xff (blank).
379 *
380 * @param buf data buffer for blank check
381 * @param len length of the buffer in byte
382 * @return
383 * 1 - blank
384 * 0 - non-blank
385 */
386 static int blank_check(u8 *buf, int len)
387 {
388 int i;
389
390 for (i = 0; i < len; i++)
391 if (buf[i] != 0xFF)
392 return 0;
393 return 1;
394 }
395
396 /**
397 * After a DMA transfer for read, we call this function to see whether there
398 * is any uncorrectable error on the pointed data buffer or oob buffer.
399 *
400 * @param reg nand_ctlr structure
401 * @param databuf data buffer
402 * @param a_len data buffer length
403 * @param oobbuf oob buffer
404 * @param b_len oob buffer length
405 * @return
406 * ECC_OK - no ECC error or correctable ECC error
407 * ECC_TAG_ERROR - uncorrectable tag ECC error
408 * ECC_DATA_ERROR - uncorrectable data ECC error
409 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
410 */
411 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
412 int a_len, u8 *oobbuf, int b_len)
413 {
414 int return_val = ECC_OK;
415 u32 reg_val;
416
417 if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
418 return ECC_OK;
419
420 /*
421 * Area A is used for the data block (databuf). Area B is used for
422 * the spare block (oobbuf)
423 */
424 reg_val = readl(&reg->dec_status);
425 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
426 reg_val = readl(&reg->bch_dec_status_buf);
427 /*
428 * If uncorrectable error occurs on data area, then see whether
429 * they are all FF. If all are FF, it's a blank page.
430 * Not error.
431 */
432 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
433 !blank_check(databuf, a_len))
434 return_val |= ECC_DATA_ERROR;
435 }
436
437 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
438 reg_val = readl(&reg->bch_dec_status_buf);
439 /*
440 * If uncorrectable error occurs on tag area, then see whether
441 * they are all FF. If all are FF, it's a blank page.
442 * Not error.
443 */
444 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
445 !blank_check(oobbuf, b_len))
446 return_val |= ECC_TAG_ERROR;
447 }
448
449 return return_val;
450 }
451
452 /**
453 * Set GO bit to send command to device
454 *
455 * @param reg nand_ctlr structure
456 */
457 static void start_command(struct nand_ctlr *reg)
458 {
459 u32 reg_val;
460
461 reg_val = readl(&reg->command);
462 reg_val |= CMD_GO;
463 writel(reg_val, &reg->command);
464 }
465
466 /**
467 * Clear command GO bit, DMA GO bit, and DMA completion status
468 *
469 * @param reg nand_ctlr structure
470 */
471 static void stop_command(struct nand_ctlr *reg)
472 {
473 /* Stop command */
474 writel(0, &reg->command);
475
476 /* Stop DMA engine and clear DMA completion status */
477 writel(DMA_MST_CTRL_GO_DISABLE
478 | DMA_MST_CTRL_IS_DMA_DONE,
479 &reg->dma_mst_ctrl);
480 }
481
482 /**
483 * Set up NAND bus width and page size
484 *
485 * @param info nand_info structure
486 * @param *reg_val address of reg_val
487 * @return 0 if ok, -1 on error
488 */
489 static int set_bus_width_page_size(struct fdt_nand *config,
490 u32 *reg_val)
491 {
492 if (config->width == 8)
493 *reg_val = CFG_BUS_WIDTH_8BIT;
494 else if (config->width == 16)
495 *reg_val = CFG_BUS_WIDTH_16BIT;
496 else {
497 debug("%s: Unsupported bus width %d\n", __func__,
498 config->width);
499 return -1;
500 }
501
502 if (our_mtd->writesize == 512)
503 *reg_val |= CFG_PAGE_SIZE_512;
504 else if (our_mtd->writesize == 2048)
505 *reg_val |= CFG_PAGE_SIZE_2048;
506 else if (our_mtd->writesize == 4096)
507 *reg_val |= CFG_PAGE_SIZE_4096;
508 else {
509 debug("%s: Unsupported page size %d\n", __func__,
510 our_mtd->writesize);
511 return -1;
512 }
513
514 return 0;
515 }
516
517 /**
518 * Page read/write function
519 *
520 * @param mtd mtd info structure
521 * @param chip nand chip info structure
522 * @param buf data buffer
523 * @param page page number
524 * @param with_ecc 1 to enable ECC, 0 to disable ECC
525 * @param is_writing 0 for read, 1 for write
526 * @return 0 when successfully completed
527 * -EIO when command timeout
528 */
529 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
530 uint8_t *buf, int page, int with_ecc, int is_writing)
531 {
532 u32 reg_val;
533 int tag_size;
534 struct nand_oobfree *free = chip->ecc.layout->oobfree;
535 /* 4*128=512 (byte) is the value that our HW can support. */
536 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
537 char *tag_ptr;
538 struct nand_drv *info;
539 struct fdt_nand *config;
540
541 if ((uintptr_t)buf & 0x03) {
542 printf("buf %p has to be 4-byte aligned\n", buf);
543 return -EINVAL;
544 }
545
546 info = (struct nand_drv *)chip->priv;
547 config = &info->config;
548 if (set_bus_width_page_size(config, &reg_val))
549 return -EINVAL;
550
551 /* Need to be 4-byte aligned */
552 tag_ptr = (char *)tag_buf;
553
554 stop_command(info->reg);
555
556 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
557 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
558
559 if (with_ecc) {
560 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
561 if (is_writing)
562 memcpy(tag_ptr, chip->oob_poi + free->offset,
563 chip->ecc.layout->oobavail +
564 TAG_ECC_BYTES);
565 } else {
566 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
567 }
568
569 /* Set ECC selection, configure ECC settings */
570 if (with_ecc) {
571 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
572 reg_val |= (CFG_SKIP_SPARE_SEL_4
573 | CFG_SKIP_SPARE_ENABLE
574 | CFG_HW_ECC_CORRECTION_ENABLE
575 | CFG_ECC_EN_TAG_DISABLE
576 | CFG_HW_ECC_SEL_RS
577 | CFG_HW_ECC_ENABLE
578 | CFG_TVAL4
579 | (tag_size - 1));
580
581 if (!is_writing)
582 tag_size += SKIPPED_SPARE_BYTES;
583 dma_prepare(tag_ptr, tag_size, is_writing);
584 } else {
585 tag_size = mtd->oobsize;
586 reg_val |= (CFG_SKIP_SPARE_DISABLE
587 | CFG_HW_ECC_CORRECTION_DISABLE
588 | CFG_ECC_EN_TAG_DISABLE
589 | CFG_HW_ECC_DISABLE
590 | (tag_size - 1));
591 dma_prepare(chip->oob_poi, tag_size, is_writing);
592 }
593 writel(reg_val, &info->reg->config);
594
595 dma_prepare(buf, 1 << chip->page_shift, is_writing);
596
597 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
598
599 writel(tag_size - 1, &info->reg->dma_cfg_b);
600
601 nand_clear_interrupt_status(info->reg);
602
603 reg_val = CMD_CLE | CMD_ALE
604 | CMD_SEC_CMD
605 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
606 | CMD_A_VALID
607 | CMD_B_VALID
608 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
609 | CMD_CE0;
610 if (!is_writing)
611 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
612 else
613 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
614 writel(reg_val, &info->reg->command);
615
616 /* Setup DMA engine */
617 reg_val = DMA_MST_CTRL_GO_ENABLE
618 | DMA_MST_CTRL_BURST_8WORDS
619 | DMA_MST_CTRL_EN_A_ENABLE
620 | DMA_MST_CTRL_EN_B_ENABLE;
621
622 if (!is_writing)
623 reg_val |= DMA_MST_CTRL_DIR_READ;
624 else
625 reg_val |= DMA_MST_CTRL_DIR_WRITE;
626
627 writel(reg_val, &info->reg->dma_mst_ctrl);
628
629 start_command(info->reg);
630
631 if (!nand_waitfor_cmd_completion(info->reg)) {
632 if (!is_writing)
633 printf("Read Page 0x%X timeout ", page);
634 else
635 printf("Write Page 0x%X timeout ", page);
636 if (with_ecc)
637 printf("with ECC");
638 else
639 printf("without ECC");
640 printf("\n");
641 return -EIO;
642 }
643
644 if (with_ecc && !is_writing) {
645 memcpy(chip->oob_poi, tag_ptr,
646 SKIPPED_SPARE_BYTES);
647 memcpy(chip->oob_poi + free->offset,
648 tag_ptr + SKIPPED_SPARE_BYTES,
649 chip->ecc.layout->oobavail);
650 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
651 1 << chip->page_shift,
652 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
653 chip->ecc.layout->oobavail);
654 if (reg_val & ECC_TAG_ERROR)
655 printf("Read Page 0x%X tag ECC error\n", page);
656 if (reg_val & ECC_DATA_ERROR)
657 printf("Read Page 0x%X data ECC error\n",
658 page);
659 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
660 return -EIO;
661 }
662 return 0;
663 }
664
665 /**
666 * Hardware ecc based page read function
667 *
668 * @param mtd mtd info structure
669 * @param chip nand chip info structure
670 * @param buf buffer to store read data
671 * @param page page number to read
672 * @return 0 when successfully completed
673 * -EIO when command timeout
674 */
675 static int nand_read_page_hwecc(struct mtd_info *mtd,
676 struct nand_chip *chip, uint8_t *buf, int page)
677 {
678 return nand_rw_page(mtd, chip, buf, page, 1, 0);
679 }
680
681 /**
682 * Hardware ecc based page write function
683 *
684 * @param mtd mtd info structure
685 * @param chip nand chip info structure
686 * @param buf data buffer
687 */
688 static void nand_write_page_hwecc(struct mtd_info *mtd,
689 struct nand_chip *chip, const uint8_t *buf)
690 {
691 int page;
692 struct nand_drv *info;
693
694 info = (struct nand_drv *)chip->priv;
695
696 page = (readl(&info->reg->addr_reg1) >> 16) |
697 (readl(&info->reg->addr_reg2) << 16);
698
699 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
700 }
701
702
703 /**
704 * Read raw page data without ecc
705 *
706 * @param mtd mtd info structure
707 * @param chip nand chip info structure
708 * @param buf buffer to store read data
709 * @param page page number to read
710 * @return 0 when successfully completed
711 * -EINVAL when chip->oob_poi is not double-word aligned
712 * -EIO when command timeout
713 */
714 static int nand_read_page_raw(struct mtd_info *mtd,
715 struct nand_chip *chip, uint8_t *buf, int page)
716 {
717 return nand_rw_page(mtd, chip, buf, page, 0, 0);
718 }
719
720 /**
721 * Raw page write function
722 *
723 * @param mtd mtd info structure
724 * @param chip nand chip info structure
725 * @param buf data buffer
726 */
727 static void nand_write_page_raw(struct mtd_info *mtd,
728 struct nand_chip *chip, const uint8_t *buf)
729 {
730 int page;
731 struct nand_drv *info;
732
733 info = (struct nand_drv *)chip->priv;
734 page = (readl(&info->reg->addr_reg1) >> 16) |
735 (readl(&info->reg->addr_reg2) << 16);
736
737 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
738 }
739
740 /**
741 * OOB data read/write function
742 *
743 * @param mtd mtd info structure
744 * @param chip nand chip info structure
745 * @param page page number to read
746 * @param with_ecc 1 to enable ECC, 0 to disable ECC
747 * @param is_writing 0 for read, 1 for write
748 * @return 0 when successfully completed
749 * -EINVAL when chip->oob_poi is not double-word aligned
750 * -EIO when command timeout
751 */
752 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
753 int page, int with_ecc, int is_writing)
754 {
755 u32 reg_val;
756 int tag_size;
757 struct nand_oobfree *free = chip->ecc.layout->oobfree;
758 struct nand_drv *info;
759
760 if (((int)chip->oob_poi) & 0x03)
761 return -EINVAL;
762 info = (struct nand_drv *)chip->priv;
763 if (set_bus_width_page_size(&info->config, &reg_val))
764 return -EINVAL;
765
766 stop_command(info->reg);
767
768 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
769
770 /* Set ECC selection */
771 tag_size = mtd->oobsize;
772 if (with_ecc)
773 reg_val |= CFG_ECC_EN_TAG_ENABLE;
774 else
775 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
776
777 reg_val |= ((tag_size - 1) |
778 CFG_SKIP_SPARE_DISABLE |
779 CFG_HW_ECC_CORRECTION_DISABLE |
780 CFG_HW_ECC_DISABLE);
781 writel(reg_val, &info->reg->config);
782
783 dma_prepare(chip->oob_poi, tag_size, is_writing);
784
785 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
786
787 if (is_writing && with_ecc)
788 tag_size -= TAG_ECC_BYTES;
789
790 writel(tag_size - 1, &info->reg->dma_cfg_b);
791
792 nand_clear_interrupt_status(info->reg);
793
794 reg_val = CMD_CLE | CMD_ALE
795 | CMD_SEC_CMD
796 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
797 | CMD_B_VALID
798 | CMD_CE0;
799 if (!is_writing)
800 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
801 else
802 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
803 writel(reg_val, &info->reg->command);
804
805 /* Setup DMA engine */
806 reg_val = DMA_MST_CTRL_GO_ENABLE
807 | DMA_MST_CTRL_BURST_8WORDS
808 | DMA_MST_CTRL_EN_B_ENABLE;
809 if (!is_writing)
810 reg_val |= DMA_MST_CTRL_DIR_READ;
811 else
812 reg_val |= DMA_MST_CTRL_DIR_WRITE;
813
814 writel(reg_val, &info->reg->dma_mst_ctrl);
815
816 start_command(info->reg);
817
818 if (!nand_waitfor_cmd_completion(info->reg)) {
819 if (!is_writing)
820 printf("Read OOB of Page 0x%X timeout\n", page);
821 else
822 printf("Write OOB of Page 0x%X timeout\n", page);
823 return -EIO;
824 }
825
826 if (with_ecc && !is_writing) {
827 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
828 (u8 *)(chip->oob_poi + free->offset),
829 chip->ecc.layout->oobavail);
830 if (reg_val & ECC_TAG_ERROR)
831 printf("Read OOB of Page 0x%X tag ECC error\n", page);
832 }
833 return 0;
834 }
835
836 /**
837 * OOB data read function
838 *
839 * @param mtd mtd info structure
840 * @param chip nand chip info structure
841 * @param page page number to read
842 * @param sndcmd flag whether to issue read command or not
843 * @return 1 - issue read command next time
844 * 0 - not to issue
845 */
846 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
847 int page, int sndcmd)
848 {
849 if (sndcmd) {
850 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
851 sndcmd = 0;
852 }
853 nand_rw_oob(mtd, chip, page, 0, 0);
854 return sndcmd;
855 }
856
857 /**
858 * OOB data write function
859 *
860 * @param mtd mtd info structure
861 * @param chip nand chip info structure
862 * @param page page number to write
863 * @return 0 when successfully completed
864 * -EINVAL when chip->oob_poi is not double-word aligned
865 * -EIO when command timeout
866 */
867 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
868 int page)
869 {
870 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
871
872 return nand_rw_oob(mtd, chip, page, 0, 1);
873 }
874
875 /**
876 * Set up NAND memory timings according to the provided parameters
877 *
878 * @param timing Timing parameters
879 * @param reg NAND controller register address
880 */
881 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
882 struct nand_ctlr *reg)
883 {
884 u32 reg_val, clk_rate, clk_period, time_val;
885
886 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
887 CLOCK_ID_PERIPH) / 1000000;
888 clk_period = 1000 / clk_rate;
889 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
890 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
891 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
892 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
893 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
894 if (time_val > 2)
895 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
896 TIMING_TCR_TAR_TRR_CNT_MASK;
897 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
898 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
899 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
900 if (time_val > 1)
901 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
902 TIMING_TCS_CNT_MASK;
903 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
904 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
905 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
906 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
907 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
908 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
909 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
910 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
911 writel(reg_val, &reg->timing);
912
913 reg_val = 0;
914 time_val = timing[FDT_NAND_TADL] / clk_period;
915 if (time_val > 2)
916 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
917 writel(reg_val, &reg->timing2);
918 }
919
920 /**
921 * Decode NAND parameters from the device tree
922 *
923 * @param blob Device tree blob
924 * @param node Node containing "nand-flash" compatble node
925 * @return 0 if ok, -ve on error (FDT_ERR_...)
926 */
927 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
928 {
929 int err;
930
931 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
932 config->enabled = fdtdec_get_is_enabled(blob, node);
933 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
934 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
935 &config->wp_gpio);
936 if (err)
937 return err;
938 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
939 config->timing, FDT_NAND_TIMING_COUNT);
940 if (err < 0)
941 return err;
942
943 /* Now look up the controller and decode that */
944 node = fdt_next_node(blob, node, NULL);
945 if (node < 0)
946 return node;
947
948 return 0;
949 }
950
951 /**
952 * Board-specific NAND initialization
953 *
954 * @param nand nand chip info structure
955 * @return 0, after initialized, -1 on error
956 */
957 int tegra_nand_init(struct nand_chip *nand, int devnum)
958 {
959 struct nand_drv *info = &nand_ctrl;
960 struct fdt_nand *config = &info->config;
961 int node, ret;
962
963 node = fdtdec_next_compatible(gd->fdt_blob, 0,
964 COMPAT_NVIDIA_TEGRA20_NAND);
965 if (node < 0)
966 return -1;
967 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
968 printf("Could not decode nand-flash in device tree\n");
969 return -1;
970 }
971 if (!config->enabled)
972 return -1;
973 info->reg = config->reg;
974 nand->ecc.mode = NAND_ECC_HW;
975 nand->ecc.layout = &eccoob;
976
977 nand->options = LP_OPTIONS;
978 nand->cmdfunc = nand_command;
979 nand->read_byte = read_byte;
980 nand->ecc.read_page = nand_read_page_hwecc;
981 nand->ecc.write_page = nand_write_page_hwecc;
982 nand->ecc.read_page_raw = nand_read_page_raw;
983 nand->ecc.write_page_raw = nand_write_page_raw;
984 nand->ecc.read_oob = nand_read_oob;
985 nand->ecc.write_oob = nand_write_oob;
986 nand->select_chip = nand_select_chip;
987 nand->dev_ready = nand_dev_ready;
988 nand->priv = &nand_ctrl;
989
990 /* Adjust controller clock rate */
991 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
992
993 /* Adjust timing for NAND device */
994 setup_timing(config->timing, info->reg);
995
996 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
997 fdtdec_setup_gpio(&config->wp_gpio);
998 gpio_direction_output(config->wp_gpio.gpio, 1);
999
1000 our_mtd = &nand_info[devnum];
1001 our_mtd->priv = nand;
1002 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1003 if (ret)
1004 return ret;
1005
1006 nand->ecc.size = our_mtd->writesize;
1007 nand->ecc.bytes = our_mtd->oobsize;
1008
1009 ret = nand_scan_tail(our_mtd);
1010 if (ret)
1011 return ret;
1012
1013 ret = nand_register(devnum);
1014 if (ret)
1015 return ret;
1016
1017 return 0;
1018 }
1019
1020 void board_nand_init(void)
1021 {
1022 struct nand_chip *nand = &nand_chip[0];
1023
1024 if (tegra_nand_init(nand, 0))
1025 puts("Tegra NAND init failed\n");
1026 }
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