]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/spi/sf_dataflash.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
dm: Rename dev_get_parentdata() to dev_get_parent_priv()
[people/ms/u-boot.git] / drivers / mtd / spi / sf_dataflash.c
1 /*
2 *
3 * Atmel DataFlash probing
4 *
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * Haikun Wang (haikun.wang@freescale.com)
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <spi.h>
15 #include <spi_flash.h>
16 #include <div64.h>
17 #include <linux/err.h>
18 #include <linux/math64.h>
19
20 #include "sf_internal.h"
21
22 /* reads can bypass the buffers */
23 #define OP_READ_CONTINUOUS 0xE8
24 #define OP_READ_PAGE 0xD2
25
26 /* group B requests can run even while status reports "busy" */
27 #define OP_READ_STATUS 0xD7 /* group B */
28
29 /* move data between host and buffer */
30 #define OP_READ_BUFFER1 0xD4 /* group B */
31 #define OP_READ_BUFFER2 0xD6 /* group B */
32 #define OP_WRITE_BUFFER1 0x84 /* group B */
33 #define OP_WRITE_BUFFER2 0x87 /* group B */
34
35 /* erasing flash */
36 #define OP_ERASE_PAGE 0x81
37 #define OP_ERASE_BLOCK 0x50
38
39 /* move data between buffer and flash */
40 #define OP_TRANSFER_BUF1 0x53
41 #define OP_TRANSFER_BUF2 0x55
42 #define OP_MREAD_BUFFER1 0xD4
43 #define OP_MREAD_BUFFER2 0xD6
44 #define OP_MWERASE_BUFFER1 0x83
45 #define OP_MWERASE_BUFFER2 0x86
46 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
47 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
48
49 /* write to buffer, then write-erase to flash */
50 #define OP_PROGRAM_VIA_BUF1 0x82
51 #define OP_PROGRAM_VIA_BUF2 0x85
52
53 /* compare buffer to flash */
54 #define OP_COMPARE_BUF1 0x60
55 #define OP_COMPARE_BUF2 0x61
56
57 /* read flash to buffer, then write-erase to flash */
58 #define OP_REWRITE_VIA_BUF1 0x58
59 #define OP_REWRITE_VIA_BUF2 0x59
60
61 /*
62 * newer chips report JEDEC manufacturer and device IDs; chip
63 * serial number and OTP bits; and per-sector writeprotect.
64 */
65 #define OP_READ_ID 0x9F
66 #define OP_READ_SECURITY 0x77
67 #define OP_WRITE_SECURITY_REVC 0x9A
68 #define OP_WRITE_SECURITY 0x9B /* revision D */
69
70
71 struct dataflash {
72 uint8_t command[16];
73 unsigned short page_offset; /* offset in flash address */
74 };
75
76 /*
77 * Return the status of the DataFlash device.
78 */
79 static inline int dataflash_status(struct spi_slave *spi)
80 {
81 int ret;
82 u8 status;
83 /*
84 * NOTE: at45db321c over 25 MHz wants to write
85 * a dummy byte after the opcode...
86 */
87 ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
88 return ret ? -EIO : status;
89 }
90
91 /*
92 * Poll the DataFlash device until it is READY.
93 * This usually takes 5-20 msec or so; more for sector erase.
94 * ready: return > 0
95 */
96 static int dataflash_waitready(struct spi_slave *spi)
97 {
98 int status;
99 int timeout = 2 * CONFIG_SYS_HZ;
100 int timebase;
101
102 timebase = get_timer(0);
103 do {
104 status = dataflash_status(spi);
105 if (status < 0)
106 status = 0;
107
108 if (status & (1 << 7)) /* RDY/nBSY */
109 return status;
110
111 mdelay(3);
112 } while (get_timer(timebase) < timeout);
113
114 return -ETIME;
115 }
116
117 /*
118 * Erase pages of flash.
119 */
120 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
121 {
122 struct dataflash *dataflash;
123 struct spi_flash *spi_flash;
124 struct spi_slave *spi;
125 unsigned blocksize;
126 uint8_t *command;
127 uint32_t rem;
128 int status;
129
130 dataflash = dev_get_priv(dev);
131 spi_flash = dev_get_uclass_priv(dev);
132 spi = spi_flash->spi;
133
134 blocksize = spi_flash->page_size << 3;
135
136 memset(dataflash->command, 0 , sizeof(dataflash->command));
137 command = dataflash->command;
138
139 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
140
141 div_u64_rem(len, spi_flash->page_size, &rem);
142 if (rem)
143 return -EINVAL;
144 div_u64_rem(offset, spi_flash->page_size, &rem);
145 if (rem)
146 return -EINVAL;
147
148 status = spi_claim_bus(spi);
149 if (status) {
150 debug("SPI DATAFLASH: unable to claim SPI bus\n");
151 return status;
152 }
153
154 while (len > 0) {
155 unsigned int pageaddr;
156 int do_block;
157 /*
158 * Calculate flash page address; use block erase (for speed) if
159 * we're at a block boundary and need to erase the whole block.
160 */
161 pageaddr = div_u64(offset, spi_flash->page_size);
162 do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
163 pageaddr = pageaddr << dataflash->page_offset;
164
165 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
166 command[1] = (uint8_t)(pageaddr >> 16);
167 command[2] = (uint8_t)(pageaddr >> 8);
168 command[3] = 0;
169
170 debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
171 dev->name, do_block ? "block" : "page",
172 command[0], command[1], command[2], command[3],
173 pageaddr);
174
175 status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
176 if (status < 0) {
177 debug("%s: erase send command error!\n", dev->name);
178 return -EIO;
179 }
180
181 status = dataflash_waitready(spi);
182 if (status < 0) {
183 debug("%s: erase waitready error!\n", dev->name);
184 return status;
185 }
186
187 if (do_block) {
188 offset += blocksize;
189 len -= blocksize;
190 } else {
191 offset += spi_flash->page_size;
192 len -= spi_flash->page_size;
193 }
194 }
195
196 spi_release_bus(spi);
197
198 return 0;
199 }
200
201 /*
202 * Read from the DataFlash device.
203 * offset : Start offset in flash device
204 * len : Amount to read
205 * buf : Buffer containing the data
206 */
207 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
208 void *buf)
209 {
210 struct dataflash *dataflash;
211 struct spi_flash *spi_flash;
212 struct spi_slave *spi;
213 unsigned int addr;
214 uint8_t *command;
215 int status;
216
217 dataflash = dev_get_priv(dev);
218 spi_flash = dev_get_uclass_priv(dev);
219 spi = spi_flash->spi;
220
221 memset(dataflash->command, 0 , sizeof(dataflash->command));
222 command = dataflash->command;
223
224 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
225 debug("READ: (%x) %x %x %x\n",
226 command[0], command[1], command[2], command[3]);
227
228 /* Calculate flash page/byte address */
229 addr = (((unsigned)offset / spi_flash->page_size)
230 << dataflash->page_offset)
231 + ((unsigned)offset % spi_flash->page_size);
232
233 status = spi_claim_bus(spi);
234 if (status) {
235 debug("SPI DATAFLASH: unable to claim SPI bus\n");
236 return status;
237 }
238
239 /*
240 * Continuous read, max clock = f(car) which may be less than
241 * the peak rate available. Some chips support commands with
242 * fewer "don't care" bytes. Both buffers stay unchanged.
243 */
244 command[0] = OP_READ_CONTINUOUS;
245 command[1] = (uint8_t)(addr >> 16);
246 command[2] = (uint8_t)(addr >> 8);
247 command[3] = (uint8_t)(addr >> 0);
248
249 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
250 status = spi_flash_cmd_read(spi, command, 8, buf, len);
251
252 spi_release_bus(spi);
253
254 return status;
255 }
256
257 /*
258 * Write to the DataFlash device.
259 * offset : Start offset in flash device
260 * len : Amount to write
261 * buf : Buffer containing the data
262 */
263 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
264 const void *buf)
265 {
266 struct dataflash *dataflash;
267 struct spi_flash *spi_flash;
268 struct spi_slave *spi;
269 uint8_t *command;
270 unsigned int pageaddr, addr, to, writelen;
271 size_t remaining = len;
272 u_char *writebuf = (u_char *)buf;
273 int status = -EINVAL;
274
275 dataflash = dev_get_priv(dev);
276 spi_flash = dev_get_uclass_priv(dev);
277 spi = spi_flash->spi;
278
279 memset(dataflash->command, 0 , sizeof(dataflash->command));
280 command = dataflash->command;
281
282 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
283
284 pageaddr = ((unsigned)offset / spi_flash->page_size);
285 to = ((unsigned)offset % spi_flash->page_size);
286 if (to + len > spi_flash->page_size)
287 writelen = spi_flash->page_size - to;
288 else
289 writelen = len;
290
291 status = spi_claim_bus(spi);
292 if (status) {
293 debug("SPI DATAFLASH: unable to claim SPI bus\n");
294 return status;
295 }
296
297 while (remaining > 0) {
298 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
299
300 /*
301 * REVISIT:
302 * (a) each page in a sector must be rewritten at least
303 * once every 10K sibling erase/program operations.
304 * (b) for pages that are already erased, we could
305 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
306 * (c) WRITE to buffer could be done while waiting for
307 * a previous MWRITE/MWERASE to complete ...
308 * (d) error handling here seems to be mostly missing.
309 *
310 * Two persistent bits per page, plus a per-sector counter,
311 * could support (a) and (b) ... we might consider using
312 * the second half of sector zero, which is just one block,
313 * to track that state. (On AT91, that sector should also
314 * support boot-from-DataFlash.)
315 */
316
317 addr = pageaddr << dataflash->page_offset;
318
319 /* (1) Maybe transfer partial page to Buffer1 */
320 if (writelen != spi_flash->page_size) {
321 command[0] = OP_TRANSFER_BUF1;
322 command[1] = (addr & 0x00FF0000) >> 16;
323 command[2] = (addr & 0x0000FF00) >> 8;
324 command[3] = 0;
325
326 debug("TRANSFER: (%x) %x %x %x\n",
327 command[0], command[1], command[2], command[3]);
328
329 status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
330 if (status < 0) {
331 debug("%s: write(<pagesize) command error!\n",
332 dev->name);
333 return -EIO;
334 }
335
336 status = dataflash_waitready(spi);
337 if (status < 0) {
338 debug("%s: write(<pagesize) waitready error!\n",
339 dev->name);
340 return status;
341 }
342 }
343
344 /* (2) Program full page via Buffer1 */
345 addr += to;
346 command[0] = OP_PROGRAM_VIA_BUF1;
347 command[1] = (addr & 0x00FF0000) >> 16;
348 command[2] = (addr & 0x0000FF00) >> 8;
349 command[3] = (addr & 0x000000FF);
350
351 debug("PROGRAM: (%x) %x %x %x\n",
352 command[0], command[1], command[2], command[3]);
353
354 status = spi_flash_cmd_write(spi, command,
355 4, writebuf, writelen);
356 if (status < 0) {
357 debug("%s: write send command error!\n", dev->name);
358 return -EIO;
359 }
360
361 status = dataflash_waitready(spi);
362 if (status < 0) {
363 debug("%s: write waitready error!\n", dev->name);
364 return status;
365 }
366
367 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
368 /* (3) Compare to Buffer1 */
369 addr = pageaddr << dataflash->page_offset;
370 command[0] = OP_COMPARE_BUF1;
371 command[1] = (addr & 0x00FF0000) >> 16;
372 command[2] = (addr & 0x0000FF00) >> 8;
373 command[3] = 0;
374
375 debug("COMPARE: (%x) %x %x %x\n",
376 command[0], command[1], command[2], command[3]);
377
378 status = spi_flash_cmd_write(spi, command,
379 4, writebuf, writelen);
380 if (status < 0) {
381 debug("%s: write(compare) send command error!\n",
382 dev->name);
383 return -EIO;
384 }
385
386 status = dataflash_waitready(spi);
387
388 /* Check result of the compare operation */
389 if (status & (1 << 6)) {
390 printf("SPI DataFlash: write compare page %u, err %d\n",
391 pageaddr, status);
392 remaining = 0;
393 status = -EIO;
394 break;
395 } else {
396 status = 0;
397 }
398
399 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
400 remaining = remaining - writelen;
401 pageaddr++;
402 to = 0;
403 writebuf += writelen;
404
405 if (remaining > spi_flash->page_size)
406 writelen = spi_flash->page_size;
407 else
408 writelen = remaining;
409 }
410
411 spi_release_bus(spi);
412
413 return 0;
414 }
415
416 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
417 int pagesize, int pageoffset, char revision)
418 {
419 struct spi_flash *spi_flash;
420 struct dataflash *dataflash;
421
422 dataflash = dev_get_priv(dev);
423 spi_flash = dev_get_uclass_priv(dev);
424
425 dataflash->page_offset = pageoffset;
426
427 spi_flash->name = name;
428 spi_flash->page_size = pagesize;
429 spi_flash->size = nr_pages * pagesize;
430 spi_flash->erase_size = pagesize;
431
432 #ifndef CONFIG_SPL_BUILD
433 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
434 print_size(spi_flash->page_size, ", erase size ");
435 print_size(spi_flash->erase_size, ", total ");
436 print_size(spi_flash->size, "");
437 printf(", revision %c", revision);
438 puts("\n");
439 #endif
440
441 return 0;
442 }
443
444 struct flash_info {
445 char *name;
446
447 /*
448 * JEDEC id has a high byte of zero plus three data bytes:
449 * the manufacturer id, then a two byte device id.
450 */
451 uint32_t jedec_id;
452
453 /* The size listed here is what works with OP_ERASE_PAGE. */
454 unsigned nr_pages;
455 uint16_t pagesize;
456 uint16_t pageoffset;
457
458 uint16_t flags;
459 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
460 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
461 };
462
463 static struct flash_info dataflash_data[] = {
464 /*
465 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
466 * one with IS_POW2PS and the other without. The entry with the
467 * non-2^N byte page size can't name exact chip revisions without
468 * losing backwards compatibility for cmdlinepart.
469 *
470 * Those two entries have different name spelling format in order to
471 * show their difference obviously.
472 * The upper case refer to the chip isn't in normal 2^N bytes page-size
473 * mode.
474 * The lower case refer to the chip is in normal 2^N bytes page-size
475 * mode.
476 *
477 * These newer chips also support 128-byte security registers (with
478 * 64 bytes one-time-programmable) and software write-protection.
479 */
480 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
481 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
482
483 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
484 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
485
486 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
487 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
488
489 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
490 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
491
492 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
493 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
494
495 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
496
497 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
498 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
499
500 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
501 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
502 };
503
504 static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
505 {
506 int tmp;
507 uint32_t jedec;
508 struct flash_info *info;
509 int status;
510
511 /*
512 * JEDEC also defines an optional "extended device information"
513 * string for after vendor-specific data, after the three bytes
514 * we use here. Supporting some chips might require using it.
515 *
516 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
517 * That's not an error; only rev C and newer chips handle it, and
518 * only Atmel sells these chips.
519 */
520 if (id[0] != 0x1f)
521 return NULL;
522
523 jedec = id[0];
524 jedec = jedec << 8;
525 jedec |= id[1];
526 jedec = jedec << 8;
527 jedec |= id[2];
528
529 for (tmp = 0, info = dataflash_data;
530 tmp < ARRAY_SIZE(dataflash_data);
531 tmp++, info++) {
532 if (info->jedec_id == jedec) {
533 if (info->flags & SUP_POW2PS) {
534 status = dataflash_status(spi);
535 if (status < 0) {
536 debug("SPI DataFlash: status error %d\n",
537 status);
538 return NULL;
539 }
540 if (status & 0x1) {
541 if (info->flags & IS_POW2PS)
542 return info;
543 } else {
544 if (!(info->flags & IS_POW2PS))
545 return info;
546 }
547 } else {
548 return info;
549 }
550 }
551 }
552
553 /*
554 * Treat other chips as errors ... we won't know the right page
555 * size (it might be binary) even when we can tell which density
556 * class is involved (legacy chip id scheme).
557 */
558 printf("SPI DataFlash: Unsupported flash IDs: ");
559 printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
560 id[0], jedec, id[3] << 8 | id[4]);
561 return NULL;
562 }
563
564 /*
565 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
566 * or else the ID code embedded in the status bits:
567 *
568 * Device Density ID code #Pages PageSize Offset
569 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
570 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
571 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
572 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
573 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
574 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
575 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
576 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
577 */
578 static int spi_dataflash_probe(struct udevice *dev)
579 {
580 struct spi_slave *spi = dev_get_parent_priv(dev);
581 struct spi_flash *spi_flash;
582 struct flash_info *info;
583 u8 idcode[5];
584 int ret, status = 0;
585
586 spi_flash = dev_get_uclass_priv(dev);
587 spi_flash->dev = dev;
588
589 ret = spi_claim_bus(spi);
590 if (ret)
591 return ret;
592
593 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
594 if (ret) {
595 printf("SPI DataFlash: Failed to get idcodes\n");
596 goto err_read_cmd;
597 }
598
599 /*
600 * Try to detect dataflash by JEDEC ID.
601 * If it succeeds we know we have either a C or D part.
602 * D will support power of 2 pagesize option.
603 * Both support the security register, though with different
604 * write procedures.
605 */
606 info = jedec_probe(spi, idcode);
607 if (info != NULL)
608 add_dataflash(dev, info->name, info->nr_pages,
609 info->pagesize, info->pageoffset,
610 (info->flags & SUP_POW2PS) ? 'd' : 'c');
611 else {
612 /*
613 * Older chips support only legacy commands, identifing
614 * capacity using bits in the status byte.
615 */
616 status = dataflash_status(spi);
617 if (status <= 0 || status == 0xff) {
618 printf("SPI DataFlash: read status error %d\n", status);
619 if (status == 0 || status == 0xff)
620 status = -ENODEV;
621 goto err_read_cmd;
622 }
623 /*
624 * if there's a device there, assume it's dataflash.
625 * board setup should have set spi->max_speed_max to
626 * match f(car) for continuous reads, mode 0 or 3.
627 */
628 switch (status & 0x3c) {
629 case 0x0c: /* 0 0 1 1 x x */
630 status = add_dataflash(dev, "AT45DB011B",
631 512, 264, 9, 0);
632 break;
633 case 0x14: /* 0 1 0 1 x x */
634 status = add_dataflash(dev, "AT45DB021B",
635 1024, 264, 9, 0);
636 break;
637 case 0x1c: /* 0 1 1 1 x x */
638 status = add_dataflash(dev, "AT45DB041x",
639 2048, 264, 9, 0);
640 break;
641 case 0x24: /* 1 0 0 1 x x */
642 status = add_dataflash(dev, "AT45DB081B",
643 4096, 264, 9, 0);
644 break;
645 case 0x2c: /* 1 0 1 1 x x */
646 status = add_dataflash(dev, "AT45DB161x",
647 4096, 528, 10, 0);
648 break;
649 case 0x34: /* 1 1 0 1 x x */
650 status = add_dataflash(dev, "AT45DB321x",
651 8192, 528, 10, 0);
652 break;
653 case 0x38: /* 1 1 1 x x x */
654 case 0x3c:
655 status = add_dataflash(dev, "AT45DB642x",
656 8192, 1056, 11, 0);
657 break;
658 /* obsolete AT45DB1282 not (yet?) supported */
659 default:
660 dev_info(&spi->dev, "unsupported device (%x)\n",
661 status & 0x3c);
662 status = -ENODEV;
663 goto err_read_cmd;
664 }
665 }
666
667 /* Assign spi data */
668 spi_flash->spi = spi;
669 spi_flash->memory_map = spi->memory_map;
670 spi_flash->dual_flash = spi->option;
671
672 spi_release_bus(spi);
673
674 return 0;
675
676 err_read_cmd:
677 spi_release_bus(spi);
678
679 return status;
680 }
681
682 static const struct dm_spi_flash_ops spi_dataflash_ops = {
683 .read = spi_dataflash_read,
684 .write = spi_dataflash_write,
685 .erase = spi_dataflash_erase,
686 };
687
688 static const struct udevice_id spi_dataflash_ids[] = {
689 { .compatible = "atmel,at45", },
690 { .compatible = "atmel,dataflash", },
691 { }
692 };
693
694 U_BOOT_DRIVER(spi_dataflash) = {
695 .name = "spi_dataflash",
696 .id = UCLASS_SPI_FLASH,
697 .of_match = spi_dataflash_ids,
698 .probe = spi_dataflash_probe,
699 .priv_auto_alloc_size = sizeof(struct dataflash),
700 .ops = &spi_dataflash_ops,
701 };
"Das U-Boot" Source Tree