drivers/mtd/spi/sf_internal.h

   1 /*
   2  * SPI flash internal definitions
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _SF_INTERNAL_H_
  11 #define _SF_INTERNAL_H_
  12
  13 #include <linux/types.h>
  14 #include <linux/compiler.h>
  15
  16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
  17 enum spi_dual_flash {
  18         SF_SINGLE_FLASH = 0,
  19         SF_DUAL_STACKED_FLASH   = 1 << 0,
  20         SF_DUAL_PARALLEL_FLASH  = 1 << 1,
  21 };
  22
  23 /* Enum list - Full read commands */
  24 enum spi_read_cmds {
  25         ARRAY_SLOW              = 1 << 0,
  26         ARRAY_FAST              = 1 << 1,
  27         DUAL_OUTPUT_FAST        = 1 << 2,
  28         DUAL_IO_FAST            = 1 << 3,
  29         QUAD_OUTPUT_FAST        = 1 << 4,
  30         QUAD_IO_FAST            = 1 << 5,
  31 };
  32
  33 /* Normal - Extended - Full command set */
  34 #define RD_NORM         (ARRAY_SLOW | ARRAY_FAST)
  35 #define RD_EXTN         (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
  36 #define RD_FULL         (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
  37
  38 /* sf param flags */
  39 enum {
  40 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  41         SECT_4K         = 1 << 0,
  42 #else
  43         SECT_4K         = 0 << 0,
  44 #endif
  45         SECT_32K        = 1 << 1,
  46         E_FSR           = 1 << 2,
  47         SST_BP          = 1 << 3,
  48         SST_WP          = 1 << 4,
  49         WR_QPP          = 1 << 5,
  50 };
  51
  52 #define SST_WR          (SST_BP | SST_WP)
  53
  54 enum spi_nor_option_flags {
  55         SNOR_F_SST_WR           = (1 << 0),
  56         SNOR_F_USE_FSR          = (1 << 1),
  57 };
  58
  59 #define SPI_FLASH_3B_ADDR_LEN           3
  60 #define SPI_FLASH_CMD_LEN               (1 + SPI_FLASH_3B_ADDR_LEN)
  61 #define SPI_FLASH_16MB_BOUN             0x1000000
  62
  63 /* CFI Manufacture ID's */
  64 #define SPI_FLASH_CFI_MFR_SPANSION      0x01
  65 #define SPI_FLASH_CFI_MFR_STMICRO       0x20
  66 #define SPI_FLASH_CFI_MFR_MACRONIX      0xc2
  67 #define SPI_FLASH_CFI_MFR_SST           0xbf
  68 #define SPI_FLASH_CFI_MFR_WINBOND       0xef
  69
  70 /* Erase commands */
  71 #define CMD_ERASE_4K                    0x20
  72 #define CMD_ERASE_32K                   0x52
  73 #define CMD_ERASE_CHIP                  0xc7
  74 #define CMD_ERASE_64K                   0xd8
  75
  76 /* Write commands */
  77 #define CMD_WRITE_STATUS                0x01
  78 #define CMD_PAGE_PROGRAM                0x02
  79 #define CMD_WRITE_DISABLE               0x04
  80 #define CMD_READ_STATUS                 0x05
  81 #define CMD_QUAD_PAGE_PROGRAM           0x32
  82 #define CMD_READ_STATUS1                0x35
  83 #define CMD_WRITE_ENABLE                0x06
  84 #define CMD_READ_CONFIG                 0x35
  85 #define CMD_FLAG_STATUS                 0x70
  86
  87 /* Read commands */
  88 #define CMD_READ_ARRAY_SLOW             0x03
  89 #define CMD_READ_ARRAY_FAST             0x0b
  90 #define CMD_READ_DUAL_OUTPUT_FAST       0x3b
  91 #define CMD_READ_DUAL_IO_FAST           0xbb
  92 #define CMD_READ_QUAD_OUTPUT_FAST       0x6b
  93 #define CMD_READ_QUAD_IO_FAST           0xeb
  94 #define CMD_READ_ID                     0x9f
  95
  96 /* Bank addr access commands */
  97 #ifdef CONFIG_SPI_FLASH_BAR
  98 # define CMD_BANKADDR_BRWR              0x17
  99 # define CMD_BANKADDR_BRRD              0x16
 100 # define CMD_EXTNADDR_WREAR             0xC5
 101 # define CMD_EXTNADDR_RDEAR             0xC8
 102 #endif
 103
 104 /* Common status */
 105 #define STATUS_WIP                      (1 << 0)
 106 #define STATUS_QEB_WINSPAN              (1 << 1)
 107 #define STATUS_QEB_MXIC         (1 << 6)
 108 #define STATUS_PEC                      (1 << 7)
 109 #define SR_BP0                          BIT(2)  /* Block protect 0 */
 110 #define SR_BP1                          BIT(3)  /* Block protect 1 */
 111 #define SR_BP2                          BIT(4)  /* Block protect 2 */
 112
 113 /* Flash timeout values */
 114 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
 115 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
 116 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
 117
 118 /* SST specific */
 119 #ifdef CONFIG_SPI_FLASH_SST
 120 # define CMD_SST_BP             0x02    /* Byte Program */
 121 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
 122
 123 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 124                 const void *buf);
 125 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 126                 const void *buf);
 127 #endif
 128
 129 /**
 130  * struct spi_flash_params - SPI/QSPI flash device params structure
 131  *
 132  * @name:               Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
 133  * @jedec:              Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
 134  * @ext_jedec:          Device ext_jedec ID
 135  * @sector_size:        Isn't necessarily a sector size from vendor,
 136  *                      the size listed here is what works with CMD_ERASE_64K
 137  * @nr_sectors:         No.of sectors on this device
 138  * @e_rd_cmd:           Enum list for read commands
 139  * @flags:              Important param, for flash specific behaviour
 140  */
 141 struct spi_flash_params {
 142         const char *name;
 143         u32 jedec;
 144         u16 ext_jedec;
 145         u32 sector_size;
 146         u32 nr_sectors;
 147         u8 e_rd_cmd;
 148         u16 flags;
 149 };
 150
 151 extern const struct spi_flash_params spi_flash_params_table[];
 152
 153 /* Send a single-byte command to the device and read the response */
 154 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
 155
 156 /*
 157  * Send a multi-byte command to the device and read the response. Used
 158  * for flash array reads, etc.
 159  */
 160 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
 161                 size_t cmd_len, void *data, size_t data_len);
 162
 163 /*
 164  * Send a multi-byte command to the device followed by (optional)
 165  * data. Used for programming the flash array, etc.
 166  */
 167 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
 168                 const void *data, size_t data_len);
 169
 170
 171 /* Flash erase(sectors) operation, support all possible erase commands */
 172 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
 173
 174 /* Read the status register */
 175 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
 176
 177 /* Program the status register */
 178 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
 179
 180 /* Lock stmicro spi flash region */
 181 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
 182
 183 /* Unlock stmicro spi flash region */
 184 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
 185
 186 /* Check if a stmicro spi flash region is completely locked */
 187 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
 188
 189 /* Read the config register */
 190 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
 191
 192 /* Program the config register */
 193 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
 194
 195 /* Enable writing on the SPI flash */
 196 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 197 {
 198         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 199 }
 200
 201 /* Disable writing on the SPI flash */
 202 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 203 {
 204         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 205 }
 206
 207 /*
 208  * Send the read status command to the device and wait for the wip
 209  * (write-in-progress) bit to clear itself.
 210  */
 211 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 212
 213 /*
 214  * Used for spi_flash write operation
 215  * - SPI claim
 216  * - spi_flash_cmd_write_enable
 217  * - spi_flash_cmd_write
 218  * - spi_flash_cmd_wait_ready
 219  * - SPI release
 220  */
 221 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 222                 size_t cmd_len, const void *buf, size_t buf_len);
 223
 224 /*
 225  * Flash write operation, support all possible write commands.
 226  * Write the requested data out breaking it up into multiple write
 227  * commands as needed per the write size.
 228  */
 229 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 230                 size_t len, const void *buf);
 231
 232 /*
 233  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 234  * bus. Used as common part of the ->read() operation.
 235  */
 236 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 237                 size_t cmd_len, void *data, size_t data_len);
 238
 239 /* Flash read operation, support all possible read commands */
 240 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 241                 size_t len, void *data);
 242
 243 #ifdef CONFIG_SPI_FLASH_MTD
 244 int spi_flash_mtd_register(struct spi_flash *flash);
 245 void spi_flash_mtd_unregister(void);
 246 #endif
 247
 248 #endif /* _SF_INTERNAL_H_ */