drivers/mtd/spi/sf_internal.h

   1 /*
   2  * SPI flash internal definitions
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _SF_INTERNAL_H_
  11 #define _SF_INTERNAL_H_
  12
  13 #define SPI_FLASH_16MB_BOUN             0x1000000
  14
  15 /* SECT flags */
  16 #define SECT_4K                         (1 << 1)
  17 #define SECT_32K                        (1 << 2)
  18 #define E_FSR                           (1 << 3)
  19
  20 /* Erase commands */
  21 #define CMD_ERASE_4K                    0x20
  22 #define CMD_ERASE_32K                   0x52
  23 #define CMD_ERASE_CHIP                  0xc7
  24 #define CMD_ERASE_64K                   0xd8
  25
  26 /* Write commands */
  27 #define CMD_WRITE_STATUS                0x01
  28 #define CMD_PAGE_PROGRAM                0x02
  29 #define CMD_WRITE_DISABLE               0x04
  30 #define CMD_READ_STATUS                 0x05
  31 #define CMD_QUAD_PAGE_PROGRAM           0x32
  32 #define CMD_READ_STATUS1                0x35
  33 #define CMD_WRITE_ENABLE                0x06
  34 #define CMD_READ_CONFIG                 0x35
  35 #define CMD_FLAG_STATUS                 0x70
  36
  37 /* Read commands */
  38 #define CMD_READ_ARRAY_SLOW             0x03
  39 #define CMD_READ_ARRAY_FAST             0x0b
  40 #define CMD_READ_DUAL_OUTPUT_FAST       0x3b
  41 #define CMD_READ_DUAL_IO_FAST           0xbb
  42 #define CMD_READ_QUAD_OUTPUT_FAST       0x6b
  43 #define CMD_READ_ID                     0x9f
  44
  45 /* Bank addr access commands */
  46 #ifdef CONFIG_SPI_FLASH_BAR
  47 # define CMD_BANKADDR_BRWR              0x17
  48 # define CMD_BANKADDR_BRRD              0x16
  49 # define CMD_EXTNADDR_WREAR             0xC5
  50 # define CMD_EXTNADDR_RDEAR             0xC8
  51 #endif
  52
  53 /* Common status */
  54 #define STATUS_WIP                      0x01
  55 #define STATUS_PEC                      0x80
  56
  57 /* Flash timeout values */
  58 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
  59 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
  60 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
  61
  62 /* SST specific */
  63 #ifdef CONFIG_SPI_FLASH_SST
  64 # define SST_WP                 0x01    /* Supports AAI word program */
  65 # define CMD_SST_BP             0x02    /* Byte Program */
  66 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
  67
  68 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  69                 const void *buf);
  70 #endif
  71
  72 /* Send a single-byte command to the device and read the response */
  73 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
  74
  75 /*
  76  * Send a multi-byte command to the device and read the response. Used
  77  * for flash array reads, etc.
  78  */
  79 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
  80                 size_t cmd_len, void *data, size_t data_len);
  81
  82 /*
  83  * Send a multi-byte command to the device followed by (optional)
  84  * data. Used for programming the flash array, etc.
  85  */
  86 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
  87                 const void *data, size_t data_len);
  88
  89
  90 /* Flash erase(sectors) operation, support all possible erase commands */
  91 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
  92
  93 /* Program the status register */
  94 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
  95
  96 /* Set quad enbale bit */
  97 int spi_flash_set_qeb(struct spi_flash *flash);
  98
  99 /* Enable writing on the SPI flash */
 100 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 101 {
 102         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 103 }
 104
 105 /* Disable writing on the SPI flash */
 106 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 107 {
 108         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 109 }
 110
 111 /*
 112  * Send the read status command to the device and wait for the wip
 113  * (write-in-progress) bit to clear itself.
 114  */
 115 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 116
 117 /*
 118  * Used for spi_flash write operation
 119  * - SPI claim
 120  * - spi_flash_cmd_write_enable
 121  * - spi_flash_cmd_write
 122  * - spi_flash_cmd_wait_ready
 123  * - SPI release
 124  */
 125 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 126                 size_t cmd_len, const void *buf, size_t buf_len);
 127
 128 /*
 129  * Flash write operation, support all possible write commands.
 130  * Write the requested data out breaking it up into multiple write
 131  * commands as needed per the write size.
 132  */
 133 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 134                 size_t len, const void *buf);
 135
 136 /*
 137  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 138  * bus. Used as common part of the ->read() operation.
 139  */
 140 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 141                 size_t cmd_len, void *data, size_t data_len);
 142
 143 /* Flash read operation, support all possible read commands */
 144 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 145                 size_t len, void *data);
 146
 147 #endif /* _SF_INTERNAL_H_ */