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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/spi/spi_flash_internal.h
86966f61e9c64f3d3e7d0f745f47ab74f5d1780e
2 * SPI flash internal definitions
4 * Copyright (C) 2008 Atmel Corporation
7 /* Common parameters -- kind of high, but they should only occur when there
8 * is a problem (and well your system already is broken), so err on the side
9 * of caution in case we're dealing with slower SPI buses and/or processors.
11 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
12 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
13 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
16 #define CMD_READ_ID 0x9f
18 #define CMD_READ_ARRAY_SLOW 0x03
19 #define CMD_READ_ARRAY_FAST 0x0b
21 #define CMD_WRITE_STATUS 0x01
22 #define CMD_PAGE_PROGRAM 0x02
23 #define CMD_WRITE_DISABLE 0x04
24 #define CMD_READ_STATUS 0x05
25 #define CMD_FLAG_STATUS 0x70
26 #define CMD_WRITE_ENABLE 0x06
27 #define CMD_ERASE_4K 0x20
28 #define CMD_ERASE_32K 0x52
29 #define CMD_ERASE_64K 0xd8
30 #define CMD_ERASE_CHIP 0xc7
32 #define SPI_FLASH_16MB_BOUN 0x1000000
34 #ifdef CONFIG_SPI_FLASH_BAR
35 /* Bank addr access commands */
36 # define CMD_BANKADDR_BRWR 0x17
37 # define CMD_BANKADDR_BRRD 0x16
38 # define CMD_EXTNADDR_WREAR 0xC5
39 # define CMD_EXTNADDR_RDEAR 0xC8
43 #define STATUS_WIP 0x01
44 #define STATUS_PEC 0x80
46 /* Send a single-byte command to the device and read the response */
47 int spi_flash_cmd(struct spi_slave
*spi
, u8 cmd
, void *response
, size_t len
);
50 * Send a multi-byte command to the device and read the response. Used
51 * for flash array reads, etc.
53 int spi_flash_cmd_read(struct spi_slave
*spi
, const u8
*cmd
,
54 size_t cmd_len
, void *data
, size_t data_len
);
56 int spi_flash_cmd_read_fast(struct spi_flash
*flash
, u32 offset
,
57 size_t len
, void *data
);
60 * Send a multi-byte command to the device followed by (optional)
61 * data. Used for programming the flash array, etc.
63 int spi_flash_cmd_write(struct spi_slave
*spi
, const u8
*cmd
, size_t cmd_len
,
64 const void *data
, size_t data_len
);
67 * Write the requested data out breaking it up into multiple write
68 * commands as needed per the write size.
70 int spi_flash_cmd_write_multi(struct spi_flash
*flash
, u32 offset
,
71 size_t len
, const void *buf
);
73 #ifdef CONFIG_SPI_FLASH_SST
74 int sst_write_wp(struct spi_flash
*flash
, u32 offset
, size_t len
,
79 * Enable writing on the SPI flash.
81 static inline int spi_flash_cmd_write_enable(struct spi_flash
*flash
)
83 return spi_flash_cmd(flash
->spi
, CMD_WRITE_ENABLE
, NULL
, 0);
87 * Disable writing on the SPI flash.
89 static inline int spi_flash_cmd_write_disable(struct spi_flash
*flash
)
91 return spi_flash_cmd(flash
->spi
, CMD_WRITE_DISABLE
, NULL
, 0);
94 /* Program the status register. */
95 int spi_flash_cmd_write_status(struct spi_flash
*flash
, u8 sr
);
97 #ifdef CONFIG_SPI_FLASH_BAR
98 /* Program the bank address register */
99 int spi_flash_cmd_bankaddr_write(struct spi_flash
*flash
, u8 bank_sel
);
103 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
104 * bus. Used as common part of the ->read() operation.
106 int spi_flash_read_common(struct spi_flash
*flash
, const u8
*cmd
,
107 size_t cmd_len
, void *data
, size_t data_len
);
109 * Used for spi_flash write operation
111 * - spi_flash_cmd_write_enable
112 * - spi_flash_cmd_write
113 * - spi_flash_cmd_wait_ready
116 int spi_flash_write_common(struct spi_flash
*flash
, const u8
*cmd
,
117 size_t cmd_len
, const void *buf
, size_t buf_len
);
120 * Send the read status command to the device and wait for the wip
121 * (write-in-progress) bit to clear itself.
123 int spi_flash_cmd_wait_ready(struct spi_flash
*flash
, unsigned long timeout
);
126 int spi_flash_cmd_erase(struct spi_flash
*flash
, u32 offset
, size_t len
);