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[people/arne_f/kernel.git] / drivers / net / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/gfp.h>
68 #include <linux/mii.h>
69 #include <linux/if_vlan.h>
70 #include <linux/crc32.h>
71 #include <linux/in.h>
72 #include <linux/ip.h>
73 #include <linux/tcp.h>
74 #include <linux/udp.h>
75 #include <linux/cache.h>
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/uaccess.h>
79
80 /* VLAN tagging feature enable/disable */
81 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
82 #define CP_VLAN_TAG_USED 1
83 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
84 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
85 #else
86 #define CP_VLAN_TAG_USED 0
87 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
88 do { (tx_desc)->opts2 = 0; } while (0)
89 #endif
90
91 /* These identify the driver base version and may not be removed. */
92 static char version[] =
93 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
94
95 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
96 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
97 MODULE_VERSION(DRV_VERSION);
98 MODULE_LICENSE("GPL");
99
100 static int debug = -1;
101 module_param(debug, int, 0);
102 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
103
104 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
105 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
106 static int multicast_filter_limit = 32;
107 module_param(multicast_filter_limit, int, 0);
108 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
109
110 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK)
113 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
114 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
115 #define CP_REGS_SIZE (0xff + 1)
116 #define CP_REGS_VER 1 /* version 1 */
117 #define CP_RX_RING_SIZE 64
118 #define CP_TX_RING_SIZE 64
119 #define CP_RING_BYTES \
120 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
121 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 CP_STATS_SIZE)
123 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
124 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
125 #define TX_BUFFS_AVAIL(CP) \
126 (((CP)->tx_tail <= (CP)->tx_head) ? \
127 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
128 (CP)->tx_tail - (CP)->tx_head - 1)
129
130 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
131 #define CP_INTERNAL_PHY 32
132
133 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define TX_TIMEOUT (6*HZ)
141
142 /* hardware minimum and maximum for a single frame's data payload */
143 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144 #define CP_MAX_MTU 4096
145
146 enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299 };
300
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305 struct cp_desc {
306 __le32 opts1;
307 __le32 opts2;
308 __le64 addr;
309 };
310
311 struct cp_dma_stats {
312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
325 } __attribute__((packed));
326
327 struct cp_extra_stats {
328 unsigned long rx_frags;
329 };
330
331 struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
337 struct napi_struct napi;
338
339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
343 struct cp_extra_stats cp_stats;
344
345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
347 struct cp_desc *rx_ring;
348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
352 struct cp_desc *tx_ring;
353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
357
358 #if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360 #endif
361 dma_addr_t ring_dma;
362
363 struct mii_if_info mii_if;
364 };
365
366 #define cpr8(reg) readb(cp->regs + (reg))
367 #define cpr16(reg) readw(cp->regs + (reg))
368 #define cpr32(reg) readl(cp->regs + (reg))
369 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
370 #define cpw16(reg,val) writew((val), cp->regs + (reg))
371 #define cpw32(reg,val) writel((val), cp->regs + (reg))
372 #define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376 #define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380 #define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386 static void __cp_set_rx_mode (struct net_device *dev);
387 static void cp_tx (struct cp_private *cp);
388 static void cp_clean_rings (struct cp_private *cp);
389 #ifdef CONFIG_NET_POLL_CONTROLLER
390 static void cp_poll_controller(struct net_device *dev);
391 #endif
392 static int cp_get_eeprom_len(struct net_device *dev);
393 static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395 static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
397
398 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
401 { },
402 };
403 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405 static struct {
406 const char str[ETH_GSTRING_LEN];
407 } ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422 };
423
424
425 #if CP_VLAN_TAG_USED
426 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427 {
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
437
438 cpw16(CpCmd, cp->cpcmd);
439 spin_unlock_irqrestore(&cp->lock, flags);
440 }
441 #endif /* CP_VLAN_TAG_USED */
442
443 static inline void cp_set_rxbufsize (struct cp_private *cp)
444 {
445 unsigned int mtu = cp->dev->mtu;
446
447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452 }
453
454 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456 {
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
461
462 #if CP_VLAN_TAG_USED
463 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
465 swab16(le32_to_cpu(desc->opts2) & 0xffff));
466 } else
467 #endif
468 netif_receive_skb(skb);
469 }
470
471 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473 {
474 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
475 rx_tail, status, len);
476 cp->dev->stats.rx_errors++;
477 if (status & RxErrFrame)
478 cp->dev->stats.rx_frame_errors++;
479 if (status & RxErrCRC)
480 cp->dev->stats.rx_crc_errors++;
481 if ((status & RxErrRunt) || (status & RxErrLong))
482 cp->dev->stats.rx_length_errors++;
483 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
484 cp->dev->stats.rx_length_errors++;
485 if (status & RxErrFIFO)
486 cp->dev->stats.rx_fifo_errors++;
487 }
488
489 static inline unsigned int cp_rx_csum_ok (u32 status)
490 {
491 unsigned int protocol = (status >> 16) & 0x3;
492
493 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
494 return 1;
495 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
496 return 1;
497 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
498 return 1;
499 return 0;
500 }
501
502 static int cp_rx_poll(struct napi_struct *napi, int budget)
503 {
504 struct cp_private *cp = container_of(napi, struct cp_private, napi);
505 struct net_device *dev = cp->dev;
506 unsigned int rx_tail = cp->rx_tail;
507 int rx;
508
509 rx_status_loop:
510 rx = 0;
511 cpw16(IntrStatus, cp_rx_intr_mask);
512
513 while (1) {
514 u32 status, len;
515 dma_addr_t mapping;
516 struct sk_buff *skb, *new_skb;
517 struct cp_desc *desc;
518 const unsigned buflen = cp->rx_buf_sz;
519
520 skb = cp->rx_skb[rx_tail];
521 BUG_ON(!skb);
522
523 desc = &cp->rx_ring[rx_tail];
524 status = le32_to_cpu(desc->opts1);
525 if (status & DescOwn)
526 break;
527
528 len = (status & 0x1fff) - 4;
529 mapping = le64_to_cpu(desc->addr);
530
531 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
532 /* we don't support incoming fragmented frames.
533 * instead, we attempt to ensure that the
534 * pre-allocated RX skbs are properly sized such
535 * that RX fragments are never encountered
536 */
537 cp_rx_err_acct(cp, rx_tail, status, len);
538 dev->stats.rx_dropped++;
539 cp->cp_stats.rx_frags++;
540 goto rx_next;
541 }
542
543 if (status & (RxError | RxErrFIFO)) {
544 cp_rx_err_acct(cp, rx_tail, status, len);
545 goto rx_next;
546 }
547
548 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
549 rx_tail, status, len);
550
551 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
552 if (!new_skb) {
553 dev->stats.rx_dropped++;
554 goto rx_next;
555 }
556
557 dma_unmap_single(&cp->pdev->dev, mapping,
558 buflen, PCI_DMA_FROMDEVICE);
559
560 /* Handle checksum offloading for incoming packets. */
561 if (cp_rx_csum_ok(status))
562 skb->ip_summed = CHECKSUM_UNNECESSARY;
563 else
564 skb->ip_summed = CHECKSUM_NONE;
565
566 skb_put(skb, len);
567
568 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
569 PCI_DMA_FROMDEVICE);
570 cp->rx_skb[rx_tail] = new_skb;
571
572 cp_rx_skb(cp, skb, desc);
573 rx++;
574
575 rx_next:
576 cp->rx_ring[rx_tail].opts2 = 0;
577 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
578 if (rx_tail == (CP_RX_RING_SIZE - 1))
579 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
580 cp->rx_buf_sz);
581 else
582 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
583 rx_tail = NEXT_RX(rx_tail);
584
585 if (rx >= budget)
586 break;
587 }
588
589 cp->rx_tail = rx_tail;
590
591 /* if we did not reach work limit, then we're done with
592 * this round of polling
593 */
594 if (rx < budget) {
595 unsigned long flags;
596
597 if (cpr16(IntrStatus) & cp_rx_intr_mask)
598 goto rx_status_loop;
599
600 spin_lock_irqsave(&cp->lock, flags);
601 cpw16_f(IntrMask, cp_intr_mask);
602 __napi_complete(napi);
603 spin_unlock_irqrestore(&cp->lock, flags);
604 }
605
606 return rx;
607 }
608
609 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
610 {
611 struct net_device *dev = dev_instance;
612 struct cp_private *cp;
613 u16 status;
614
615 if (unlikely(dev == NULL))
616 return IRQ_NONE;
617 cp = netdev_priv(dev);
618
619 status = cpr16(IntrStatus);
620 if (!status || (status == 0xFFFF))
621 return IRQ_NONE;
622
623 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
624 status, cpr8(Cmd), cpr16(CpCmd));
625
626 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
627
628 spin_lock(&cp->lock);
629
630 /* close possible race's with dev_close */
631 if (unlikely(!netif_running(dev))) {
632 cpw16(IntrMask, 0);
633 spin_unlock(&cp->lock);
634 return IRQ_HANDLED;
635 }
636
637 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
638 if (napi_schedule_prep(&cp->napi)) {
639 cpw16_f(IntrMask, cp_norx_intr_mask);
640 __napi_schedule(&cp->napi);
641 }
642
643 if (status & (TxOK | TxErr | TxEmpty | SWInt))
644 cp_tx(cp);
645 if (status & LinkChg)
646 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
647
648 spin_unlock(&cp->lock);
649
650 if (status & PciErr) {
651 u16 pci_status;
652
653 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
654 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
655 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
656 status, pci_status);
657
658 /* TODO: reset hardware */
659 }
660
661 return IRQ_HANDLED;
662 }
663
664 #ifdef CONFIG_NET_POLL_CONTROLLER
665 /*
666 * Polling receive - used by netconsole and other diagnostic tools
667 * to allow network i/o with interrupts disabled.
668 */
669 static void cp_poll_controller(struct net_device *dev)
670 {
671 disable_irq(dev->irq);
672 cp_interrupt(dev->irq, dev);
673 enable_irq(dev->irq);
674 }
675 #endif
676
677 static void cp_tx (struct cp_private *cp)
678 {
679 unsigned tx_head = cp->tx_head;
680 unsigned tx_tail = cp->tx_tail;
681
682 while (tx_tail != tx_head) {
683 struct cp_desc *txd = cp->tx_ring + tx_tail;
684 struct sk_buff *skb;
685 u32 status;
686
687 rmb();
688 status = le32_to_cpu(txd->opts1);
689 if (status & DescOwn)
690 break;
691
692 skb = cp->tx_skb[tx_tail];
693 BUG_ON(!skb);
694
695 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
696 le32_to_cpu(txd->opts1) & 0xffff,
697 PCI_DMA_TODEVICE);
698
699 if (status & LastFrag) {
700 if (status & (TxError | TxFIFOUnder)) {
701 netif_dbg(cp, tx_err, cp->dev,
702 "tx err, status 0x%x\n", status);
703 cp->dev->stats.tx_errors++;
704 if (status & TxOWC)
705 cp->dev->stats.tx_window_errors++;
706 if (status & TxMaxCol)
707 cp->dev->stats.tx_aborted_errors++;
708 if (status & TxLinkFail)
709 cp->dev->stats.tx_carrier_errors++;
710 if (status & TxFIFOUnder)
711 cp->dev->stats.tx_fifo_errors++;
712 } else {
713 cp->dev->stats.collisions +=
714 ((status >> TxColCntShift) & TxColCntMask);
715 cp->dev->stats.tx_packets++;
716 cp->dev->stats.tx_bytes += skb->len;
717 netif_dbg(cp, tx_done, cp->dev,
718 "tx done, slot %d\n", tx_tail);
719 }
720 dev_kfree_skb_irq(skb);
721 }
722
723 cp->tx_skb[tx_tail] = NULL;
724
725 tx_tail = NEXT_TX(tx_tail);
726 }
727
728 cp->tx_tail = tx_tail;
729
730 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
731 netif_wake_queue(cp->dev);
732 }
733
734 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
735 struct net_device *dev)
736 {
737 struct cp_private *cp = netdev_priv(dev);
738 unsigned entry;
739 u32 eor, flags;
740 unsigned long intr_flags;
741 #if CP_VLAN_TAG_USED
742 u32 vlan_tag = 0;
743 #endif
744 int mss = 0;
745
746 spin_lock_irqsave(&cp->lock, intr_flags);
747
748 /* This is a hard error, log it. */
749 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
750 netif_stop_queue(dev);
751 spin_unlock_irqrestore(&cp->lock, intr_flags);
752 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
753 return NETDEV_TX_BUSY;
754 }
755
756 #if CP_VLAN_TAG_USED
757 if (cp->vlgrp && vlan_tx_tag_present(skb))
758 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
759 #endif
760
761 entry = cp->tx_head;
762 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
763 if (dev->features & NETIF_F_TSO)
764 mss = skb_shinfo(skb)->gso_size;
765
766 if (skb_shinfo(skb)->nr_frags == 0) {
767 struct cp_desc *txd = &cp->tx_ring[entry];
768 u32 len;
769 dma_addr_t mapping;
770
771 len = skb->len;
772 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
773 CP_VLAN_TX_TAG(txd, vlan_tag);
774 txd->addr = cpu_to_le64(mapping);
775 wmb();
776
777 flags = eor | len | DescOwn | FirstFrag | LastFrag;
778
779 if (mss)
780 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
781 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
782 const struct iphdr *ip = ip_hdr(skb);
783 if (ip->protocol == IPPROTO_TCP)
784 flags |= IPCS | TCPCS;
785 else if (ip->protocol == IPPROTO_UDP)
786 flags |= IPCS | UDPCS;
787 else
788 WARN_ON(1); /* we need a WARN() */
789 }
790
791 txd->opts1 = cpu_to_le32(flags);
792 wmb();
793
794 cp->tx_skb[entry] = skb;
795 entry = NEXT_TX(entry);
796 } else {
797 struct cp_desc *txd;
798 u32 first_len, first_eor;
799 dma_addr_t first_mapping;
800 int frag, first_entry = entry;
801 const struct iphdr *ip = ip_hdr(skb);
802
803 /* We must give this initial chunk to the device last.
804 * Otherwise we could race with the device.
805 */
806 first_eor = eor;
807 first_len = skb_headlen(skb);
808 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
809 first_len, PCI_DMA_TODEVICE);
810 cp->tx_skb[entry] = skb;
811 entry = NEXT_TX(entry);
812
813 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
814 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
815 u32 len;
816 u32 ctrl;
817 dma_addr_t mapping;
818
819 len = this_frag->size;
820 mapping = dma_map_single(&cp->pdev->dev,
821 ((void *) page_address(this_frag->page) +
822 this_frag->page_offset),
823 len, PCI_DMA_TODEVICE);
824 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
825
826 ctrl = eor | len | DescOwn;
827
828 if (mss)
829 ctrl |= LargeSend |
830 ((mss & MSSMask) << MSSShift);
831 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
832 if (ip->protocol == IPPROTO_TCP)
833 ctrl |= IPCS | TCPCS;
834 else if (ip->protocol == IPPROTO_UDP)
835 ctrl |= IPCS | UDPCS;
836 else
837 BUG();
838 }
839
840 if (frag == skb_shinfo(skb)->nr_frags - 1)
841 ctrl |= LastFrag;
842
843 txd = &cp->tx_ring[entry];
844 CP_VLAN_TX_TAG(txd, vlan_tag);
845 txd->addr = cpu_to_le64(mapping);
846 wmb();
847
848 txd->opts1 = cpu_to_le32(ctrl);
849 wmb();
850
851 cp->tx_skb[entry] = skb;
852 entry = NEXT_TX(entry);
853 }
854
855 txd = &cp->tx_ring[first_entry];
856 CP_VLAN_TX_TAG(txd, vlan_tag);
857 txd->addr = cpu_to_le64(first_mapping);
858 wmb();
859
860 if (skb->ip_summed == CHECKSUM_PARTIAL) {
861 if (ip->protocol == IPPROTO_TCP)
862 txd->opts1 = cpu_to_le32(first_eor | first_len |
863 FirstFrag | DescOwn |
864 IPCS | TCPCS);
865 else if (ip->protocol == IPPROTO_UDP)
866 txd->opts1 = cpu_to_le32(first_eor | first_len |
867 FirstFrag | DescOwn |
868 IPCS | UDPCS);
869 else
870 BUG();
871 } else
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn);
874 wmb();
875 }
876 cp->tx_head = entry;
877 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
878 entry, skb->len);
879 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
880 netif_stop_queue(dev);
881
882 spin_unlock_irqrestore(&cp->lock, intr_flags);
883
884 cpw8(TxPoll, NormalTxPoll);
885 dev->trans_start = jiffies;
886
887 return NETDEV_TX_OK;
888 }
889
890 /* Set or clear the multicast filter for this adaptor.
891 This routine is not state sensitive and need not be SMP locked. */
892
893 static void __cp_set_rx_mode (struct net_device *dev)
894 {
895 struct cp_private *cp = netdev_priv(dev);
896 u32 mc_filter[2]; /* Multicast hash filter */
897 int rx_mode;
898 u32 tmp;
899
900 /* Note: do not reorder, GCC is clever about common statements. */
901 if (dev->flags & IFF_PROMISC) {
902 /* Unconditionally log net taps. */
903 rx_mode =
904 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
905 AcceptAllPhys;
906 mc_filter[1] = mc_filter[0] = 0xffffffff;
907 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
908 (dev->flags & IFF_ALLMULTI)) {
909 /* Too many to filter perfectly -- accept all multicasts. */
910 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
911 mc_filter[1] = mc_filter[0] = 0xffffffff;
912 } else {
913 struct dev_mc_list *mclist;
914 rx_mode = AcceptBroadcast | AcceptMyPhys;
915 mc_filter[1] = mc_filter[0] = 0;
916 netdev_for_each_mc_addr(mclist, dev) {
917 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
918
919 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
920 rx_mode |= AcceptMulticast;
921 }
922 }
923
924 /* We can safely update without stopping the chip. */
925 tmp = cp_rx_config | rx_mode;
926 if (cp->rx_config != tmp) {
927 cpw32_f (RxConfig, tmp);
928 cp->rx_config = tmp;
929 }
930 cpw32_f (MAR0 + 0, mc_filter[0]);
931 cpw32_f (MAR0 + 4, mc_filter[1]);
932 }
933
934 static void cp_set_rx_mode (struct net_device *dev)
935 {
936 unsigned long flags;
937 struct cp_private *cp = netdev_priv(dev);
938
939 spin_lock_irqsave (&cp->lock, flags);
940 __cp_set_rx_mode(dev);
941 spin_unlock_irqrestore (&cp->lock, flags);
942 }
943
944 static void __cp_get_stats(struct cp_private *cp)
945 {
946 /* only lower 24 bits valid; write any value to clear */
947 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
948 cpw32 (RxMissed, 0);
949 }
950
951 static struct net_device_stats *cp_get_stats(struct net_device *dev)
952 {
953 struct cp_private *cp = netdev_priv(dev);
954 unsigned long flags;
955
956 /* The chip only need report frame silently dropped. */
957 spin_lock_irqsave(&cp->lock, flags);
958 if (netif_running(dev) && netif_device_present(dev))
959 __cp_get_stats(cp);
960 spin_unlock_irqrestore(&cp->lock, flags);
961
962 return &dev->stats;
963 }
964
965 static void cp_stop_hw (struct cp_private *cp)
966 {
967 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
968 cpw16_f(IntrMask, 0);
969 cpw8(Cmd, 0);
970 cpw16_f(CpCmd, 0);
971 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
972
973 cp->rx_tail = 0;
974 cp->tx_head = cp->tx_tail = 0;
975 }
976
977 static void cp_reset_hw (struct cp_private *cp)
978 {
979 unsigned work = 1000;
980
981 cpw8(Cmd, CmdReset);
982
983 while (work--) {
984 if (!(cpr8(Cmd) & CmdReset))
985 return;
986
987 schedule_timeout_uninterruptible(10);
988 }
989
990 netdev_err(cp->dev, "hardware reset timeout\n");
991 }
992
993 static inline void cp_start_hw (struct cp_private *cp)
994 {
995 cpw16(CpCmd, cp->cpcmd);
996 cpw8(Cmd, RxOn | TxOn);
997 }
998
999 static void cp_init_hw (struct cp_private *cp)
1000 {
1001 struct net_device *dev = cp->dev;
1002 dma_addr_t ring_dma;
1003
1004 cp_reset_hw(cp);
1005
1006 cpw8_f (Cfg9346, Cfg9346_Unlock);
1007
1008 /* Restore our idea of the MAC address. */
1009 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1010 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1011
1012 cp_start_hw(cp);
1013 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1014
1015 __cp_set_rx_mode(dev);
1016 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1017
1018 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1019 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1020 cpw8(Config3, PARMEnable);
1021 cp->wol_enabled = 0;
1022
1023 cpw8(Config5, cpr8(Config5) & PMEStatus);
1024
1025 cpw32_f(HiTxRingAddr, 0);
1026 cpw32_f(HiTxRingAddr + 4, 0);
1027
1028 ring_dma = cp->ring_dma;
1029 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1030 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1031
1032 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1033 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1034 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1035
1036 cpw16(MultiIntr, 0);
1037
1038 cpw16_f(IntrMask, cp_intr_mask);
1039
1040 cpw8_f(Cfg9346, Cfg9346_Lock);
1041 }
1042
1043 static int cp_refill_rx(struct cp_private *cp)
1044 {
1045 struct net_device *dev = cp->dev;
1046 unsigned i;
1047
1048 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1049 struct sk_buff *skb;
1050 dma_addr_t mapping;
1051
1052 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1053 if (!skb)
1054 goto err_out;
1055
1056 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1057 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1058 cp->rx_skb[i] = skb;
1059
1060 cp->rx_ring[i].opts2 = 0;
1061 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1062 if (i == (CP_RX_RING_SIZE - 1))
1063 cp->rx_ring[i].opts1 =
1064 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1065 else
1066 cp->rx_ring[i].opts1 =
1067 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1068 }
1069
1070 return 0;
1071
1072 err_out:
1073 cp_clean_rings(cp);
1074 return -ENOMEM;
1075 }
1076
1077 static void cp_init_rings_index (struct cp_private *cp)
1078 {
1079 cp->rx_tail = 0;
1080 cp->tx_head = cp->tx_tail = 0;
1081 }
1082
1083 static int cp_init_rings (struct cp_private *cp)
1084 {
1085 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1086 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1087
1088 cp_init_rings_index(cp);
1089
1090 return cp_refill_rx (cp);
1091 }
1092
1093 static int cp_alloc_rings (struct cp_private *cp)
1094 {
1095 void *mem;
1096
1097 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1098 &cp->ring_dma, GFP_KERNEL);
1099 if (!mem)
1100 return -ENOMEM;
1101
1102 cp->rx_ring = mem;
1103 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1104
1105 return cp_init_rings(cp);
1106 }
1107
1108 static void cp_clean_rings (struct cp_private *cp)
1109 {
1110 struct cp_desc *desc;
1111 unsigned i;
1112
1113 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1114 if (cp->rx_skb[i]) {
1115 desc = cp->rx_ring + i;
1116 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1117 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1118 dev_kfree_skb(cp->rx_skb[i]);
1119 }
1120 }
1121
1122 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1123 if (cp->tx_skb[i]) {
1124 struct sk_buff *skb = cp->tx_skb[i];
1125
1126 desc = cp->tx_ring + i;
1127 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1128 le32_to_cpu(desc->opts1) & 0xffff,
1129 PCI_DMA_TODEVICE);
1130 if (le32_to_cpu(desc->opts1) & LastFrag)
1131 dev_kfree_skb(skb);
1132 cp->dev->stats.tx_dropped++;
1133 }
1134 }
1135
1136 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1137 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1138
1139 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1140 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1141 }
1142
1143 static void cp_free_rings (struct cp_private *cp)
1144 {
1145 cp_clean_rings(cp);
1146 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1147 cp->ring_dma);
1148 cp->rx_ring = NULL;
1149 cp->tx_ring = NULL;
1150 }
1151
1152 static int cp_open (struct net_device *dev)
1153 {
1154 struct cp_private *cp = netdev_priv(dev);
1155 int rc;
1156
1157 netif_dbg(cp, ifup, dev, "enabling interface\n");
1158
1159 rc = cp_alloc_rings(cp);
1160 if (rc)
1161 return rc;
1162
1163 napi_enable(&cp->napi);
1164
1165 cp_init_hw(cp);
1166
1167 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1168 if (rc)
1169 goto err_out_hw;
1170
1171 netif_carrier_off(dev);
1172 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1173 netif_start_queue(dev);
1174
1175 return 0;
1176
1177 err_out_hw:
1178 napi_disable(&cp->napi);
1179 cp_stop_hw(cp);
1180 cp_free_rings(cp);
1181 return rc;
1182 }
1183
1184 static int cp_close (struct net_device *dev)
1185 {
1186 struct cp_private *cp = netdev_priv(dev);
1187 unsigned long flags;
1188
1189 napi_disable(&cp->napi);
1190
1191 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1192
1193 spin_lock_irqsave(&cp->lock, flags);
1194
1195 netif_stop_queue(dev);
1196 netif_carrier_off(dev);
1197
1198 cp_stop_hw(cp);
1199
1200 spin_unlock_irqrestore(&cp->lock, flags);
1201
1202 free_irq(dev->irq, dev);
1203
1204 cp_free_rings(cp);
1205 return 0;
1206 }
1207
1208 static void cp_tx_timeout(struct net_device *dev)
1209 {
1210 struct cp_private *cp = netdev_priv(dev);
1211 unsigned long flags;
1212 int rc;
1213
1214 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1215 cpr8(Cmd), cpr16(CpCmd),
1216 cpr16(IntrStatus), cpr16(IntrMask));
1217
1218 spin_lock_irqsave(&cp->lock, flags);
1219
1220 cp_stop_hw(cp);
1221 cp_clean_rings(cp);
1222 rc = cp_init_rings(cp);
1223 cp_start_hw(cp);
1224
1225 netif_wake_queue(dev);
1226
1227 spin_unlock_irqrestore(&cp->lock, flags);
1228
1229 return;
1230 }
1231
1232 #ifdef BROKEN
1233 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1234 {
1235 struct cp_private *cp = netdev_priv(dev);
1236 int rc;
1237 unsigned long flags;
1238
1239 /* check for invalid MTU, according to hardware limits */
1240 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1241 return -EINVAL;
1242
1243 /* if network interface not up, no need for complexity */
1244 if (!netif_running(dev)) {
1245 dev->mtu = new_mtu;
1246 cp_set_rxbufsize(cp); /* set new rx buf size */
1247 return 0;
1248 }
1249
1250 spin_lock_irqsave(&cp->lock, flags);
1251
1252 cp_stop_hw(cp); /* stop h/w and free rings */
1253 cp_clean_rings(cp);
1254
1255 dev->mtu = new_mtu;
1256 cp_set_rxbufsize(cp); /* set new rx buf size */
1257
1258 rc = cp_init_rings(cp); /* realloc and restart h/w */
1259 cp_start_hw(cp);
1260
1261 spin_unlock_irqrestore(&cp->lock, flags);
1262
1263 return rc;
1264 }
1265 #endif /* BROKEN */
1266
1267 static const char mii_2_8139_map[8] = {
1268 BasicModeCtrl,
1269 BasicModeStatus,
1270 0,
1271 0,
1272 NWayAdvert,
1273 NWayLPAR,
1274 NWayExpansion,
1275 0
1276 };
1277
1278 static int mdio_read(struct net_device *dev, int phy_id, int location)
1279 {
1280 struct cp_private *cp = netdev_priv(dev);
1281
1282 return location < 8 && mii_2_8139_map[location] ?
1283 readw(cp->regs + mii_2_8139_map[location]) : 0;
1284 }
1285
1286
1287 static void mdio_write(struct net_device *dev, int phy_id, int location,
1288 int value)
1289 {
1290 struct cp_private *cp = netdev_priv(dev);
1291
1292 if (location == 0) {
1293 cpw8(Cfg9346, Cfg9346_Unlock);
1294 cpw16(BasicModeCtrl, value);
1295 cpw8(Cfg9346, Cfg9346_Lock);
1296 } else if (location < 8 && mii_2_8139_map[location])
1297 cpw16(mii_2_8139_map[location], value);
1298 }
1299
1300 /* Set the ethtool Wake-on-LAN settings */
1301 static int netdev_set_wol (struct cp_private *cp,
1302 const struct ethtool_wolinfo *wol)
1303 {
1304 u8 options;
1305
1306 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1307 /* If WOL is being disabled, no need for complexity */
1308 if (wol->wolopts) {
1309 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1310 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1311 }
1312
1313 cpw8 (Cfg9346, Cfg9346_Unlock);
1314 cpw8 (Config3, options);
1315 cpw8 (Cfg9346, Cfg9346_Lock);
1316
1317 options = 0; /* Paranoia setting */
1318 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1319 /* If WOL is being disabled, no need for complexity */
1320 if (wol->wolopts) {
1321 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1322 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1323 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1324 }
1325
1326 cpw8 (Config5, options);
1327
1328 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1329
1330 return 0;
1331 }
1332
1333 /* Get the ethtool Wake-on-LAN settings */
1334 static void netdev_get_wol (struct cp_private *cp,
1335 struct ethtool_wolinfo *wol)
1336 {
1337 u8 options;
1338
1339 wol->wolopts = 0; /* Start from scratch */
1340 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1341 WAKE_MCAST | WAKE_UCAST;
1342 /* We don't need to go on if WOL is disabled */
1343 if (!cp->wol_enabled) return;
1344
1345 options = cpr8 (Config3);
1346 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1347 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1348
1349 options = 0; /* Paranoia setting */
1350 options = cpr8 (Config5);
1351 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1352 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1353 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1354 }
1355
1356 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1357 {
1358 struct cp_private *cp = netdev_priv(dev);
1359
1360 strcpy (info->driver, DRV_NAME);
1361 strcpy (info->version, DRV_VERSION);
1362 strcpy (info->bus_info, pci_name(cp->pdev));
1363 }
1364
1365 static int cp_get_regs_len(struct net_device *dev)
1366 {
1367 return CP_REGS_SIZE;
1368 }
1369
1370 static int cp_get_sset_count (struct net_device *dev, int sset)
1371 {
1372 switch (sset) {
1373 case ETH_SS_STATS:
1374 return CP_NUM_STATS;
1375 default:
1376 return -EOPNOTSUPP;
1377 }
1378 }
1379
1380 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1381 {
1382 struct cp_private *cp = netdev_priv(dev);
1383 int rc;
1384 unsigned long flags;
1385
1386 spin_lock_irqsave(&cp->lock, flags);
1387 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1388 spin_unlock_irqrestore(&cp->lock, flags);
1389
1390 return rc;
1391 }
1392
1393 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1394 {
1395 struct cp_private *cp = netdev_priv(dev);
1396 int rc;
1397 unsigned long flags;
1398
1399 spin_lock_irqsave(&cp->lock, flags);
1400 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1401 spin_unlock_irqrestore(&cp->lock, flags);
1402
1403 return rc;
1404 }
1405
1406 static int cp_nway_reset(struct net_device *dev)
1407 {
1408 struct cp_private *cp = netdev_priv(dev);
1409 return mii_nway_restart(&cp->mii_if);
1410 }
1411
1412 static u32 cp_get_msglevel(struct net_device *dev)
1413 {
1414 struct cp_private *cp = netdev_priv(dev);
1415 return cp->msg_enable;
1416 }
1417
1418 static void cp_set_msglevel(struct net_device *dev, u32 value)
1419 {
1420 struct cp_private *cp = netdev_priv(dev);
1421 cp->msg_enable = value;
1422 }
1423
1424 static u32 cp_get_rx_csum(struct net_device *dev)
1425 {
1426 struct cp_private *cp = netdev_priv(dev);
1427 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1428 }
1429
1430 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1431 {
1432 struct cp_private *cp = netdev_priv(dev);
1433 u16 cmd = cp->cpcmd, newcmd;
1434
1435 newcmd = cmd;
1436
1437 if (data)
1438 newcmd |= RxChkSum;
1439 else
1440 newcmd &= ~RxChkSum;
1441
1442 if (newcmd != cmd) {
1443 unsigned long flags;
1444
1445 spin_lock_irqsave(&cp->lock, flags);
1446 cp->cpcmd = newcmd;
1447 cpw16_f(CpCmd, newcmd);
1448 spin_unlock_irqrestore(&cp->lock, flags);
1449 }
1450
1451 return 0;
1452 }
1453
1454 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1455 void *p)
1456 {
1457 struct cp_private *cp = netdev_priv(dev);
1458 unsigned long flags;
1459
1460 if (regs->len < CP_REGS_SIZE)
1461 return /* -EINVAL */;
1462
1463 regs->version = CP_REGS_VER;
1464
1465 spin_lock_irqsave(&cp->lock, flags);
1466 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1467 spin_unlock_irqrestore(&cp->lock, flags);
1468 }
1469
1470 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474
1475 spin_lock_irqsave (&cp->lock, flags);
1476 netdev_get_wol (cp, wol);
1477 spin_unlock_irqrestore (&cp->lock, flags);
1478 }
1479
1480 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1481 {
1482 struct cp_private *cp = netdev_priv(dev);
1483 unsigned long flags;
1484 int rc;
1485
1486 spin_lock_irqsave (&cp->lock, flags);
1487 rc = netdev_set_wol (cp, wol);
1488 spin_unlock_irqrestore (&cp->lock, flags);
1489
1490 return rc;
1491 }
1492
1493 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1494 {
1495 switch (stringset) {
1496 case ETH_SS_STATS:
1497 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1498 break;
1499 default:
1500 BUG();
1501 break;
1502 }
1503 }
1504
1505 static void cp_get_ethtool_stats (struct net_device *dev,
1506 struct ethtool_stats *estats, u64 *tmp_stats)
1507 {
1508 struct cp_private *cp = netdev_priv(dev);
1509 struct cp_dma_stats *nic_stats;
1510 dma_addr_t dma;
1511 int i;
1512
1513 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1514 &dma, GFP_KERNEL);
1515 if (!nic_stats)
1516 return;
1517
1518 /* begin NIC statistics dump */
1519 cpw32(StatsAddr + 4, (u64)dma >> 32);
1520 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1521 cpr32(StatsAddr);
1522
1523 for (i = 0; i < 1000; i++) {
1524 if ((cpr32(StatsAddr) & DumpStats) == 0)
1525 break;
1526 udelay(10);
1527 }
1528 cpw32(StatsAddr, 0);
1529 cpw32(StatsAddr + 4, 0);
1530 cpr32(StatsAddr);
1531
1532 i = 0;
1533 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1534 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1535 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1536 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1537 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1538 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1539 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1540 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1543 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1545 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1546 tmp_stats[i++] = cp->cp_stats.rx_frags;
1547 BUG_ON(i != CP_NUM_STATS);
1548
1549 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1550 }
1551
1552 static const struct ethtool_ops cp_ethtool_ops = {
1553 .get_drvinfo = cp_get_drvinfo,
1554 .get_regs_len = cp_get_regs_len,
1555 .get_sset_count = cp_get_sset_count,
1556 .get_settings = cp_get_settings,
1557 .set_settings = cp_set_settings,
1558 .nway_reset = cp_nway_reset,
1559 .get_link = ethtool_op_get_link,
1560 .get_msglevel = cp_get_msglevel,
1561 .set_msglevel = cp_set_msglevel,
1562 .get_rx_csum = cp_get_rx_csum,
1563 .set_rx_csum = cp_set_rx_csum,
1564 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1565 .set_sg = ethtool_op_set_sg,
1566 .set_tso = ethtool_op_set_tso,
1567 .get_regs = cp_get_regs,
1568 .get_wol = cp_get_wol,
1569 .set_wol = cp_set_wol,
1570 .get_strings = cp_get_strings,
1571 .get_ethtool_stats = cp_get_ethtool_stats,
1572 .get_eeprom_len = cp_get_eeprom_len,
1573 .get_eeprom = cp_get_eeprom,
1574 .set_eeprom = cp_set_eeprom,
1575 };
1576
1577 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1578 {
1579 struct cp_private *cp = netdev_priv(dev);
1580 int rc;
1581 unsigned long flags;
1582
1583 if (!netif_running(dev))
1584 return -EINVAL;
1585
1586 spin_lock_irqsave(&cp->lock, flags);
1587 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1588 spin_unlock_irqrestore(&cp->lock, flags);
1589 return rc;
1590 }
1591
1592 static int cp_set_mac_address(struct net_device *dev, void *p)
1593 {
1594 struct cp_private *cp = netdev_priv(dev);
1595 struct sockaddr *addr = p;
1596
1597 if (!is_valid_ether_addr(addr->sa_data))
1598 return -EADDRNOTAVAIL;
1599
1600 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1601
1602 spin_lock_irq(&cp->lock);
1603
1604 cpw8_f(Cfg9346, Cfg9346_Unlock);
1605 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1606 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1607 cpw8_f(Cfg9346, Cfg9346_Lock);
1608
1609 spin_unlock_irq(&cp->lock);
1610
1611 return 0;
1612 }
1613
1614 /* Serial EEPROM section. */
1615
1616 /* EEPROM_Ctrl bits. */
1617 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1618 #define EE_CS 0x08 /* EEPROM chip select. */
1619 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1620 #define EE_WRITE_0 0x00
1621 #define EE_WRITE_1 0x02
1622 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1623 #define EE_ENB (0x80 | EE_CS)
1624
1625 /* Delay between EEPROM clock transitions.
1626 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1627 */
1628
1629 #define eeprom_delay() readl(ee_addr)
1630
1631 /* The EEPROM commands include the alway-set leading bit. */
1632 #define EE_EXTEND_CMD (4)
1633 #define EE_WRITE_CMD (5)
1634 #define EE_READ_CMD (6)
1635 #define EE_ERASE_CMD (7)
1636
1637 #define EE_EWDS_ADDR (0)
1638 #define EE_WRAL_ADDR (1)
1639 #define EE_ERAL_ADDR (2)
1640 #define EE_EWEN_ADDR (3)
1641
1642 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1643
1644 static void eeprom_cmd_start(void __iomem *ee_addr)
1645 {
1646 writeb (EE_ENB & ~EE_CS, ee_addr);
1647 writeb (EE_ENB, ee_addr);
1648 eeprom_delay ();
1649 }
1650
1651 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1652 {
1653 int i;
1654
1655 /* Shift the command bits out. */
1656 for (i = cmd_len - 1; i >= 0; i--) {
1657 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1658 writeb (EE_ENB | dataval, ee_addr);
1659 eeprom_delay ();
1660 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1661 eeprom_delay ();
1662 }
1663 writeb (EE_ENB, ee_addr);
1664 eeprom_delay ();
1665 }
1666
1667 static void eeprom_cmd_end(void __iomem *ee_addr)
1668 {
1669 writeb (~EE_CS, ee_addr);
1670 eeprom_delay ();
1671 }
1672
1673 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1674 int addr_len)
1675 {
1676 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1677
1678 eeprom_cmd_start(ee_addr);
1679 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1680 eeprom_cmd_end(ee_addr);
1681 }
1682
1683 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1684 {
1685 int i;
1686 u16 retval = 0;
1687 void __iomem *ee_addr = ioaddr + Cfg9346;
1688 int read_cmd = location | (EE_READ_CMD << addr_len);
1689
1690 eeprom_cmd_start(ee_addr);
1691 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1692
1693 for (i = 16; i > 0; i--) {
1694 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1695 eeprom_delay ();
1696 retval =
1697 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1698 0);
1699 writeb (EE_ENB, ee_addr);
1700 eeprom_delay ();
1701 }
1702
1703 eeprom_cmd_end(ee_addr);
1704
1705 return retval;
1706 }
1707
1708 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1709 int addr_len)
1710 {
1711 int i;
1712 void __iomem *ee_addr = ioaddr + Cfg9346;
1713 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1714
1715 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1716
1717 eeprom_cmd_start(ee_addr);
1718 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1719 eeprom_cmd(ee_addr, val, 16);
1720 eeprom_cmd_end(ee_addr);
1721
1722 eeprom_cmd_start(ee_addr);
1723 for (i = 0; i < 20000; i++)
1724 if (readb(ee_addr) & EE_DATA_READ)
1725 break;
1726 eeprom_cmd_end(ee_addr);
1727
1728 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1729 }
1730
1731 static int cp_get_eeprom_len(struct net_device *dev)
1732 {
1733 struct cp_private *cp = netdev_priv(dev);
1734 int size;
1735
1736 spin_lock_irq(&cp->lock);
1737 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1738 spin_unlock_irq(&cp->lock);
1739
1740 return size;
1741 }
1742
1743 static int cp_get_eeprom(struct net_device *dev,
1744 struct ethtool_eeprom *eeprom, u8 *data)
1745 {
1746 struct cp_private *cp = netdev_priv(dev);
1747 unsigned int addr_len;
1748 u16 val;
1749 u32 offset = eeprom->offset >> 1;
1750 u32 len = eeprom->len;
1751 u32 i = 0;
1752
1753 eeprom->magic = CP_EEPROM_MAGIC;
1754
1755 spin_lock_irq(&cp->lock);
1756
1757 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1758
1759 if (eeprom->offset & 1) {
1760 val = read_eeprom(cp->regs, offset, addr_len);
1761 data[i++] = (u8)(val >> 8);
1762 offset++;
1763 }
1764
1765 while (i < len - 1) {
1766 val = read_eeprom(cp->regs, offset, addr_len);
1767 data[i++] = (u8)val;
1768 data[i++] = (u8)(val >> 8);
1769 offset++;
1770 }
1771
1772 if (i < len) {
1773 val = read_eeprom(cp->regs, offset, addr_len);
1774 data[i] = (u8)val;
1775 }
1776
1777 spin_unlock_irq(&cp->lock);
1778 return 0;
1779 }
1780
1781 static int cp_set_eeprom(struct net_device *dev,
1782 struct ethtool_eeprom *eeprom, u8 *data)
1783 {
1784 struct cp_private *cp = netdev_priv(dev);
1785 unsigned int addr_len;
1786 u16 val;
1787 u32 offset = eeprom->offset >> 1;
1788 u32 len = eeprom->len;
1789 u32 i = 0;
1790
1791 if (eeprom->magic != CP_EEPROM_MAGIC)
1792 return -EINVAL;
1793
1794 spin_lock_irq(&cp->lock);
1795
1796 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1797
1798 if (eeprom->offset & 1) {
1799 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1800 val |= (u16)data[i++] << 8;
1801 write_eeprom(cp->regs, offset, val, addr_len);
1802 offset++;
1803 }
1804
1805 while (i < len - 1) {
1806 val = (u16)data[i++];
1807 val |= (u16)data[i++] << 8;
1808 write_eeprom(cp->regs, offset, val, addr_len);
1809 offset++;
1810 }
1811
1812 if (i < len) {
1813 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1814 val |= (u16)data[i];
1815 write_eeprom(cp->regs, offset, val, addr_len);
1816 }
1817
1818 spin_unlock_irq(&cp->lock);
1819 return 0;
1820 }
1821
1822 /* Put the board into D3cold state and wait for WakeUp signal */
1823 static void cp_set_d3_state (struct cp_private *cp)
1824 {
1825 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1826 pci_set_power_state (cp->pdev, PCI_D3hot);
1827 }
1828
1829 static const struct net_device_ops cp_netdev_ops = {
1830 .ndo_open = cp_open,
1831 .ndo_stop = cp_close,
1832 .ndo_validate_addr = eth_validate_addr,
1833 .ndo_set_mac_address = cp_set_mac_address,
1834 .ndo_set_multicast_list = cp_set_rx_mode,
1835 .ndo_get_stats = cp_get_stats,
1836 .ndo_do_ioctl = cp_ioctl,
1837 .ndo_start_xmit = cp_start_xmit,
1838 .ndo_tx_timeout = cp_tx_timeout,
1839 #if CP_VLAN_TAG_USED
1840 .ndo_vlan_rx_register = cp_vlan_rx_register,
1841 #endif
1842 #ifdef BROKEN
1843 .ndo_change_mtu = cp_change_mtu,
1844 #endif
1845
1846 #ifdef CONFIG_NET_POLL_CONTROLLER
1847 .ndo_poll_controller = cp_poll_controller,
1848 #endif
1849 };
1850
1851 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1852 {
1853 struct net_device *dev;
1854 struct cp_private *cp;
1855 int rc;
1856 void __iomem *regs;
1857 resource_size_t pciaddr;
1858 unsigned int addr_len, i, pci_using_dac;
1859
1860 #ifndef MODULE
1861 static int version_printed;
1862 if (version_printed++ == 0)
1863 pr_info("%s", version);
1864 #endif
1865
1866 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1867 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1868 dev_info(&pdev->dev,
1869 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1870 pdev->vendor, pdev->device, pdev->revision);
1871 return -ENODEV;
1872 }
1873
1874 dev = alloc_etherdev(sizeof(struct cp_private));
1875 if (!dev)
1876 return -ENOMEM;
1877 SET_NETDEV_DEV(dev, &pdev->dev);
1878
1879 cp = netdev_priv(dev);
1880 cp->pdev = pdev;
1881 cp->dev = dev;
1882 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1883 spin_lock_init (&cp->lock);
1884 cp->mii_if.dev = dev;
1885 cp->mii_if.mdio_read = mdio_read;
1886 cp->mii_if.mdio_write = mdio_write;
1887 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1888 cp->mii_if.phy_id_mask = 0x1f;
1889 cp->mii_if.reg_num_mask = 0x1f;
1890 cp_set_rxbufsize(cp);
1891
1892 rc = pci_enable_device(pdev);
1893 if (rc)
1894 goto err_out_free;
1895
1896 rc = pci_set_mwi(pdev);
1897 if (rc)
1898 goto err_out_disable;
1899
1900 rc = pci_request_regions(pdev, DRV_NAME);
1901 if (rc)
1902 goto err_out_mwi;
1903
1904 pciaddr = pci_resource_start(pdev, 1);
1905 if (!pciaddr) {
1906 rc = -EIO;
1907 dev_err(&pdev->dev, "no MMIO resource\n");
1908 goto err_out_res;
1909 }
1910 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1911 rc = -EIO;
1912 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1913 (unsigned long long)pci_resource_len(pdev, 1));
1914 goto err_out_res;
1915 }
1916
1917 /* Configure DMA attributes. */
1918 if ((sizeof(dma_addr_t) > 4) &&
1919 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1920 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1921 pci_using_dac = 1;
1922 } else {
1923 pci_using_dac = 0;
1924
1925 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1926 if (rc) {
1927 dev_err(&pdev->dev,
1928 "No usable DMA configuration, aborting\n");
1929 goto err_out_res;
1930 }
1931 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1932 if (rc) {
1933 dev_err(&pdev->dev,
1934 "No usable consistent DMA configuration, aborting\n");
1935 goto err_out_res;
1936 }
1937 }
1938
1939 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1940 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1941
1942 regs = ioremap(pciaddr, CP_REGS_SIZE);
1943 if (!regs) {
1944 rc = -EIO;
1945 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1946 (unsigned long long)pci_resource_len(pdev, 1),
1947 (unsigned long long)pciaddr);
1948 goto err_out_res;
1949 }
1950 dev->base_addr = (unsigned long) regs;
1951 cp->regs = regs;
1952
1953 cp_stop_hw(cp);
1954
1955 /* read MAC address from EEPROM */
1956 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1957 for (i = 0; i < 3; i++)
1958 ((__le16 *) (dev->dev_addr))[i] =
1959 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1960 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1961
1962 dev->netdev_ops = &cp_netdev_ops;
1963 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1964 dev->ethtool_ops = &cp_ethtool_ops;
1965 dev->watchdog_timeo = TX_TIMEOUT;
1966
1967 #if CP_VLAN_TAG_USED
1968 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1969 #endif
1970
1971 if (pci_using_dac)
1972 dev->features |= NETIF_F_HIGHDMA;
1973
1974 #if 0 /* disabled by default until verified */
1975 dev->features |= NETIF_F_TSO;
1976 #endif
1977
1978 dev->irq = pdev->irq;
1979
1980 rc = register_netdev(dev);
1981 if (rc)
1982 goto err_out_iomap;
1983
1984 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1985 dev->base_addr, dev->dev_addr, dev->irq);
1986
1987 pci_set_drvdata(pdev, dev);
1988
1989 /* enable busmastering and memory-write-invalidate */
1990 pci_set_master(pdev);
1991
1992 if (cp->wol_enabled)
1993 cp_set_d3_state (cp);
1994
1995 return 0;
1996
1997 err_out_iomap:
1998 iounmap(regs);
1999 err_out_res:
2000 pci_release_regions(pdev);
2001 err_out_mwi:
2002 pci_clear_mwi(pdev);
2003 err_out_disable:
2004 pci_disable_device(pdev);
2005 err_out_free:
2006 free_netdev(dev);
2007 return rc;
2008 }
2009
2010 static void cp_remove_one (struct pci_dev *pdev)
2011 {
2012 struct net_device *dev = pci_get_drvdata(pdev);
2013 struct cp_private *cp = netdev_priv(dev);
2014
2015 unregister_netdev(dev);
2016 iounmap(cp->regs);
2017 if (cp->wol_enabled)
2018 pci_set_power_state (pdev, PCI_D0);
2019 pci_release_regions(pdev);
2020 pci_clear_mwi(pdev);
2021 pci_disable_device(pdev);
2022 pci_set_drvdata(pdev, NULL);
2023 free_netdev(dev);
2024 }
2025
2026 #ifdef CONFIG_PM
2027 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2028 {
2029 struct net_device *dev = pci_get_drvdata(pdev);
2030 struct cp_private *cp = netdev_priv(dev);
2031 unsigned long flags;
2032
2033 if (!netif_running(dev))
2034 return 0;
2035
2036 netif_device_detach (dev);
2037 netif_stop_queue (dev);
2038
2039 spin_lock_irqsave (&cp->lock, flags);
2040
2041 /* Disable Rx and Tx */
2042 cpw16 (IntrMask, 0);
2043 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2044
2045 spin_unlock_irqrestore (&cp->lock, flags);
2046
2047 pci_save_state(pdev);
2048 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2049 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2050
2051 return 0;
2052 }
2053
2054 static int cp_resume (struct pci_dev *pdev)
2055 {
2056 struct net_device *dev = pci_get_drvdata (pdev);
2057 struct cp_private *cp = netdev_priv(dev);
2058 unsigned long flags;
2059
2060 if (!netif_running(dev))
2061 return 0;
2062
2063 netif_device_attach (dev);
2064
2065 pci_set_power_state(pdev, PCI_D0);
2066 pci_restore_state(pdev);
2067 pci_enable_wake(pdev, PCI_D0, 0);
2068
2069 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2070 cp_init_rings_index (cp);
2071 cp_init_hw (cp);
2072 netif_start_queue (dev);
2073
2074 spin_lock_irqsave (&cp->lock, flags);
2075
2076 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2077
2078 spin_unlock_irqrestore (&cp->lock, flags);
2079
2080 return 0;
2081 }
2082 #endif /* CONFIG_PM */
2083
2084 static struct pci_driver cp_driver = {
2085 .name = DRV_NAME,
2086 .id_table = cp_pci_tbl,
2087 .probe = cp_init_one,
2088 .remove = cp_remove_one,
2089 #ifdef CONFIG_PM
2090 .resume = cp_resume,
2091 .suspend = cp_suspend,
2092 #endif
2093 };
2094
2095 static int __init cp_init (void)
2096 {
2097 #ifdef MODULE
2098 pr_info("%s", version);
2099 #endif
2100 return pci_register_driver(&cp_driver);
2101 }
2102
2103 static void __exit cp_exit (void)
2104 {
2105 pci_unregister_driver (&cp_driver);
2106 }
2107
2108 module_init(cp_init);
2109 module_exit(cp_exit);
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