]> git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/net/ag7xxx.c
projects / thirdparty / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
common: Drop net.h from common header
[thirdparty/u-boot.git] / drivers / net / ag7xxx.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Atheros AR71xx / AR9xxx GMAC driver
4 *
5 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
7 */
8
9 #include <common.h>
10 #include <clock_legacy.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <miiphy.h>
15 #include <malloc.h>
16 #include <net.h>
17 #include <asm/cache.h>
18 #include <linux/compiler.h>
19 #include <linux/err.h>
20 #include <linux/mii.h>
21 #include <wait_bit.h>
22 #include <asm/io.h>
23
24 #include <mach/ath79.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 enum ag7xxx_model {
29 AG7XXX_MODEL_AG933X,
30 AG7XXX_MODEL_AG934X,
31 AG7XXX_MODEL_AG953X,
32 AG7XXX_MODEL_AG956X
33 };
34
35 /* MAC Configuration 1 */
36 #define AG7XXX_ETH_CFG1 0x00
37 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
38 #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
39 #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
40 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
41 #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
42 #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
43
44 /* MAC Configuration 2 */
45 #define AG7XXX_ETH_CFG2 0x04
46 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
47 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
48 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
49 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
50 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
51 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
52 #define AG7XXX_ETH_CFG2_FDX BIT(0)
53
54 /* MII Configuration */
55 #define AG7XXX_ETH_MII_MGMT_CFG 0x20
56 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
57
58 /* MII Command */
59 #define AG7XXX_ETH_MII_MGMT_CMD 0x24
60 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
61
62 /* MII Address */
63 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
64 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
65
66 /* MII Control */
67 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
68
69 /* MII Status */
70 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
71
72 /* MII Indicators */
73 #define AG7XXX_ETH_MII_MGMT_IND 0x34
74 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
75 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
76
77 /* STA Address 1 & 2 */
78 #define AG7XXX_ETH_ADDR1 0x40
79 #define AG7XXX_ETH_ADDR2 0x44
80
81 /* ETH Configuration 0 - 5 */
82 #define AG7XXX_ETH_FIFO_CFG_0 0x48
83 #define AG7XXX_ETH_FIFO_CFG_1 0x4c
84 #define AG7XXX_ETH_FIFO_CFG_2 0x50
85 #define AG7XXX_ETH_FIFO_CFG_3 0x54
86 #define AG7XXX_ETH_FIFO_CFG_4 0x58
87 #define AG7XXX_ETH_FIFO_CFG_5 0x5c
88
89 /* DMA Transfer Control for Queue 0 */
90 #define AG7XXX_ETH_DMA_TX_CTRL 0x180
91 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
92
93 /* Descriptor Address for Queue 0 Tx */
94 #define AG7XXX_ETH_DMA_TX_DESC 0x184
95
96 /* DMA Tx Status */
97 #define AG7XXX_ETH_DMA_TX_STATUS 0x188
98
99 /* Rx Control */
100 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
101 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
102
103 /* Pointer to Rx Descriptor */
104 #define AG7XXX_ETH_DMA_RX_DESC 0x190
105
106 /* Rx Status */
107 #define AG7XXX_ETH_DMA_RX_STATUS 0x194
108
109 /* Custom register at 0x1805002C */
110 #define AG7XXX_ETH_XMII 0x2C
111 #define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
112 #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
113 #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
114 #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
115 (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
116 #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
117 #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
118 #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
119 (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
120 #define AG7XXX_ETH_XMII_GIGE BIT(25)
121
122 /* Custom register at 0x18070000 */
123 #define AG7XXX_GMAC_ETH_CFG 0x00
124 #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
125 #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
126 #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
127 (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
128 #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
129 #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
130 #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
131 (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
132 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
133 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
134 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
135 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
136 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
137 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
138 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
139 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
140 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
141
142 #define CONFIG_TX_DESCR_NUM 8
143 #define CONFIG_RX_DESCR_NUM 8
144 #define CONFIG_ETH_BUFSIZE 2048
145 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
146 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
147
148 /* DMA descriptor. */
149 struct ag7xxx_dma_desc {
150 u32 data_addr;
151 #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
152 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
153 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
154 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
155 u32 config;
156 u32 next_desc;
157 u32 _pad[5];
158 };
159
160 struct ar7xxx_eth_priv {
161 struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
162 struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
163 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
164 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
165
166 void __iomem *regs;
167 void __iomem *phyregs;
168
169 struct eth_device *dev;
170 struct phy_device *phydev;
171 struct mii_dev *bus;
172
173 u32 interface;
174 u32 tx_currdescnum;
175 u32 rx_currdescnum;
176 enum ag7xxx_model model;
177 };
178
179 /*
180 * Switch and MDIO access
181 */
182 static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
183 {
184 struct ar7xxx_eth_priv *priv = bus->priv;
185 void __iomem *regs = priv->phyregs;
186 int ret;
187
188 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
189 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
190 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
191 writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
192 regs + AG7XXX_ETH_MII_MGMT_CMD);
193
194 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
195 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
196 if (ret)
197 return ret;
198
199 *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
200 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
201
202 return 0;
203 }
204
205 static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
206 {
207 struct ar7xxx_eth_priv *priv = bus->priv;
208 void __iomem *regs = priv->phyregs;
209 int ret;
210
211 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
212 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
213 writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
214
215 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
216 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
217
218 return ret;
219 }
220
221 static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
222 {
223 struct ar7xxx_eth_priv *priv = bus->priv;
224 u32 phy_addr;
225 u32 reg_addr;
226 u32 phy_temp;
227 u32 reg_temp;
228 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
229 u16 rv = 0;
230 int ret;
231
232 if (priv->model == AG7XXX_MODEL_AG933X ||
233 priv->model == AG7XXX_MODEL_AG953X) {
234 phy_addr = 0x1f;
235 reg_addr = 0x10;
236 } else if (priv->model == AG7XXX_MODEL_AG934X ||
237 priv->model == AG7XXX_MODEL_AG956X) {
238 phy_addr = 0x18;
239 reg_addr = 0x00;
240 } else
241 return -EINVAL;
242
243 if (priv->model == AG7XXX_MODEL_AG956X)
244 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
245 else
246 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
247 if (ret)
248 return ret;
249
250 phy_temp = ((reg >> 6) & 0x7) | 0x10;
251 if (priv->model == AG7XXX_MODEL_AG956X)
252 reg_temp = reg_temp_w & 0x1f;
253 else
254 reg_temp = (reg >> 1) & 0x1e;
255 *val = 0;
256
257 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
258 if (ret < 0)
259 return ret;
260 *val |= rv;
261
262 if (priv->model == AG7XXX_MODEL_AG956X) {
263 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
264 reg_temp = (reg_temp_w + 1) & 0x1f;
265 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
266 } else {
267 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
268 }
269 if (ret < 0)
270 return ret;
271 *val |= (rv << 16);
272
273 return 0;
274 }
275
276 static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
277 {
278 struct ar7xxx_eth_priv *priv = bus->priv;
279 u32 phy_addr;
280 u32 reg_addr;
281 u32 phy_temp;
282 u32 reg_temp;
283 u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
284 int ret;
285
286 if (priv->model == AG7XXX_MODEL_AG933X ||
287 priv->model == AG7XXX_MODEL_AG953X) {
288 phy_addr = 0x1f;
289 reg_addr = 0x10;
290 } else if (priv->model == AG7XXX_MODEL_AG934X ||
291 priv->model == AG7XXX_MODEL_AG956X) {
292 phy_addr = 0x18;
293 reg_addr = 0x00;
294 } else
295 return -EINVAL;
296
297 if (priv->model == AG7XXX_MODEL_AG956X)
298 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
299 else
300 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
301 if (ret)
302 return ret;
303
304 if (priv->model == AG7XXX_MODEL_AG956X) {
305 reg_temp = (reg_temp_w + 1) & 0x1f;
306 phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
307 } else {
308 phy_temp = ((reg >> 6) & 0x7) | 0x10;
309 reg_temp = (reg >> 1) & 0x1e;
310 }
311
312 /*
313 * The switch on AR933x has some special register behavior, which
314 * expects particular write order of their nibbles:
315 * 0x40 ..... MSB first, LSB second
316 * 0x50 ..... MSB first, LSB second
317 * 0x98 ..... LSB first, MSB second
318 * others ... don't care
319 */
320 if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
321 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
322 if (ret < 0)
323 return ret;
324
325 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
326 if (ret < 0)
327 return ret;
328 } else {
329 if (priv->model == AG7XXX_MODEL_AG956X)
330 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
331 else
332 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
333 if (ret < 0)
334 return ret;
335
336 if (priv->model == AG7XXX_MODEL_AG956X) {
337 phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
338 reg_temp = reg_temp_w & 0x1f;
339 }
340
341 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
342 if (ret < 0)
343 return ret;
344 }
345
346 return 0;
347 }
348
349 static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
350 {
351 u32 data;
352 unsigned long start;
353 int ret;
354 /* No idea if this is long enough or too long */
355 int timeout_ms = 1000;
356
357 /* Dummy read followed by PHY read/write command. */
358 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
359 if (ret < 0)
360 return ret;
361 data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
362 ret = ag7xxx_switch_reg_write(bus, 0x98, data);
363 if (ret < 0)
364 return ret;
365
366 start = get_timer(0);
367
368 /* Wait for operation to finish */
369 do {
370 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
371 if (ret < 0)
372 return ret;
373
374 if (get_timer(start) > timeout_ms)
375 return -ETIMEDOUT;
376 } while (data & BIT(31));
377
378 return data & 0xffff;
379 }
380
381 static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
382 {
383 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
384 }
385
386 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
387 u16 val)
388 {
389 int ret;
390
391 ret = ag7xxx_mdio_rw(bus, addr, reg, val);
392 if (ret < 0)
393 return ret;
394 return 0;
395 }
396
397 /*
398 * DMA ring handlers
399 */
400 static void ag7xxx_dma_clean_tx(struct udevice *dev)
401 {
402 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
403 struct ag7xxx_dma_desc *curr, *next;
404 u32 start, end;
405 int i;
406
407 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
408 curr = &priv->tx_mac_descrtable[i];
409 next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
410
411 curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
412 curr->config = AG7XXX_DMADESC_IS_EMPTY;
413 curr->next_desc = virt_to_phys(next);
414 }
415
416 priv->tx_currdescnum = 0;
417
418 /* Cache: Flush descriptors, don't care about buffers. */
419 start = (u32)(&priv->tx_mac_descrtable[0]);
420 end = start + sizeof(priv->tx_mac_descrtable);
421 flush_dcache_range(start, end);
422 }
423
424 static void ag7xxx_dma_clean_rx(struct udevice *dev)
425 {
426 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
427 struct ag7xxx_dma_desc *curr, *next;
428 u32 start, end;
429 int i;
430
431 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
432 curr = &priv->rx_mac_descrtable[i];
433 next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
434
435 curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
436 curr->config = AG7XXX_DMADESC_IS_EMPTY;
437 curr->next_desc = virt_to_phys(next);
438 }
439
440 priv->rx_currdescnum = 0;
441
442 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
443 start = (u32)(&priv->rx_mac_descrtable[0]);
444 end = start + sizeof(priv->rx_mac_descrtable);
445 flush_dcache_range(start, end);
446 invalidate_dcache_range(start, end);
447
448 start = (u32)&priv->rxbuffs;
449 end = start + sizeof(priv->rxbuffs);
450 invalidate_dcache_range(start, end);
451 }
452
453 /*
454 * Ethernet I/O
455 */
456 static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
457 {
458 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
459 struct ag7xxx_dma_desc *curr;
460 u32 start, end;
461
462 curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
463
464 /* Cache: Invalidate descriptor. */
465 start = (u32)curr;
466 end = start + sizeof(*curr);
467 invalidate_dcache_range(start, end);
468
469 if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
470 printf("ag7xxx: Out of TX DMA descriptors!\n");
471 return -EPERM;
472 }
473
474 /* Copy the packet into the data buffer. */
475 memcpy(phys_to_virt(curr->data_addr), packet, length);
476 curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
477
478 /* Cache: Flush descriptor, Flush buffer. */
479 start = (u32)curr;
480 end = start + sizeof(*curr);
481 flush_dcache_range(start, end);
482 start = (u32)phys_to_virt(curr->data_addr);
483 end = start + length;
484 flush_dcache_range(start, end);
485
486 /* Load the DMA descriptor and start TX DMA. */
487 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
488 priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
489
490 /* Switch to next TX descriptor. */
491 priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
492
493 return 0;
494 }
495
496 static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
497 {
498 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
499 struct ag7xxx_dma_desc *curr;
500 u32 start, end, length;
501
502 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
503
504 /* Cache: Invalidate descriptor. */
505 start = (u32)curr;
506 end = start + sizeof(*curr);
507 invalidate_dcache_range(start, end);
508
509 /* No packets received. */
510 if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
511 return -EAGAIN;
512
513 length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
514
515 /* Cache: Invalidate buffer. */
516 start = (u32)phys_to_virt(curr->data_addr);
517 end = start + length;
518 invalidate_dcache_range(start, end);
519
520 /* Receive one packet and return length. */
521 *packetp = phys_to_virt(curr->data_addr);
522 return length;
523 }
524
525 static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
526 int length)
527 {
528 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
529 struct ag7xxx_dma_desc *curr;
530 u32 start, end;
531
532 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
533
534 curr->config = AG7XXX_DMADESC_IS_EMPTY;
535
536 /* Cache: Flush descriptor. */
537 start = (u32)curr;
538 end = start + sizeof(*curr);
539 flush_dcache_range(start, end);
540
541 /* Switch to next RX descriptor. */
542 priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
543
544 return 0;
545 }
546
547 static int ag7xxx_eth_start(struct udevice *dev)
548 {
549 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
550
551 /* FIXME: Check if link up */
552
553 /* Clear the DMA rings. */
554 ag7xxx_dma_clean_tx(dev);
555 ag7xxx_dma_clean_rx(dev);
556
557 /* Load DMA descriptors and start the RX DMA. */
558 writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
559 priv->regs + AG7XXX_ETH_DMA_TX_DESC);
560 writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
561 priv->regs + AG7XXX_ETH_DMA_RX_DESC);
562 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
563 priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
564
565 return 0;
566 }
567
568 static void ag7xxx_eth_stop(struct udevice *dev)
569 {
570 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
571
572 /* Stop the TX DMA. */
573 writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
574 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
575 1000, 0);
576
577 /* Stop the RX DMA. */
578 writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
579 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
580 1000, 0);
581 }
582
583 /*
584 * Hardware setup
585 */
586 static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
587 {
588 struct eth_pdata *pdata = dev_get_platdata(dev);
589 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
590 unsigned char *mac = pdata->enetaddr;
591 u32 macid_lo, macid_hi;
592
593 macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
594 macid_lo = (mac[5] << 16) | (mac[4] << 24);
595
596 writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
597 writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
598
599 return 0;
600 }
601
602 static void ag7xxx_hw_setup(struct udevice *dev)
603 {
604 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
605 u32 speed;
606
607 setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
608 AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
609 AG7XXX_ETH_CFG1_SOFT_RST);
610
611 mdelay(10);
612
613 writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
614 priv->regs + AG7XXX_ETH_CFG1);
615
616 if (priv->interface == PHY_INTERFACE_MODE_RMII)
617 speed = AG7XXX_ETH_CFG2_IF_10_100;
618 else
619 speed = AG7XXX_ETH_CFG2_IF_1000;
620
621 clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
622 AG7XXX_ETH_CFG2_IF_SPEED_MASK,
623 speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
624 AG7XXX_ETH_CFG2_LEN_CHECK);
625
626 writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
627 writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
628
629 writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
630 setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
631 writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
632 writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
633 writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
634 writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
635 }
636
637 static int ag7xxx_mii_get_div(void)
638 {
639 ulong freq = get_bus_freq(0);
640
641 switch (freq / 1000000) {
642 case 150: return 0x7;
643 case 175: return 0x5;
644 case 200: return 0x4;
645 case 210: return 0x9;
646 case 220: return 0x9;
647 default: return 0x7;
648 }
649 }
650
651 static int ag7xxx_mii_setup(struct udevice *dev)
652 {
653 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
654 int i, ret, div = ag7xxx_mii_get_div();
655 u32 reg;
656
657 if (priv->model == AG7XXX_MODEL_AG933X) {
658 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
659 if (priv->interface == PHY_INTERFACE_MODE_RMII)
660 return 0;
661 }
662
663 if (priv->model == AG7XXX_MODEL_AG934X)
664 reg = 0x4;
665 else if (priv->model == AG7XXX_MODEL_AG953X)
666 reg = 0x2;
667 else if (priv->model == AG7XXX_MODEL_AG956X)
668 reg = 0x7;
669
670 if (priv->model == AG7XXX_MODEL_AG934X ||
671 priv->model == AG7XXX_MODEL_AG953X ||
672 priv->model == AG7XXX_MODEL_AG956X) {
673 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
674 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
675 writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
676 return 0;
677 }
678
679 for (i = 0; i < 10; i++) {
680 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
681 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
682 writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
683
684 /* Check the switch */
685 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
686 if (ret)
687 continue;
688
689 if (reg != 0x18007fff)
690 continue;
691
692 return 0;
693 }
694
695 return -EINVAL;
696 }
697
698 static int ag933x_phy_setup_wan(struct udevice *dev)
699 {
700 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
701
702 /* Configure switch port 4 (GMAC0) */
703 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
704 }
705
706 static int ag933x_phy_setup_lan(struct udevice *dev)
707 {
708 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
709 int i, ret;
710 u32 reg;
711
712 /* Reset the switch */
713 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
714 if (ret)
715 return ret;
716 reg |= BIT(31);
717 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
718 if (ret)
719 return ret;
720
721 do {
722 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
723 if (ret)
724 return ret;
725 } while (reg & BIT(31));
726
727 /* Configure switch ports 0...3 (GMAC1) */
728 for (i = 0; i < 4; i++) {
729 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
730 if (ret)
731 return ret;
732 }
733
734 /* Enable CPU port */
735 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
736 if (ret)
737 return ret;
738
739 for (i = 0; i < 4; i++) {
740 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
741 if (ret)
742 return ret;
743 }
744
745 /* QM Control */
746 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
747 if (ret)
748 return ret;
749
750 /* Disable Atheros header */
751 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
752 if (ret)
753 return ret;
754
755 /* Tag priority mapping */
756 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
757 if (ret)
758 return ret;
759
760 /* Enable ARP packets to the CPU */
761 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
762 if (ret)
763 return ret;
764 reg |= 0x100000;
765 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
766 if (ret)
767 return ret;
768
769 return 0;
770 }
771
772 static int ag953x_phy_setup_wan(struct udevice *dev)
773 {
774 int ret;
775 u32 reg = 0;
776 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
777
778 /* Set wan port connect to GE0 */
779 ret = ag7xxx_switch_reg_read(priv->bus, 0x8, &reg);
780 if (ret)
781 return ret;
782
783 ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
784 if (ret)
785 return ret;
786
787 /* Configure switch port 4 (GMAC0) */
788 ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
789 if (ret)
790 return ret;
791
792 return 0;
793 }
794
795 static int ag953x_phy_setup_lan(struct udevice *dev)
796 {
797 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
798 int i, ret;
799 u32 reg = 0;
800
801 /* Reset the switch */
802 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
803 if (ret)
804 return ret;
805
806 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
807 if (ret)
808 return ret;
809
810 do {
811 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
812 if (ret)
813 return ret;
814 } while (reg & BIT(31));
815
816 ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
817 if (ret)
818 return ret;
819
820 /* Set GMII mode */
821 ret = ag7xxx_switch_reg_read(priv->bus, 0x4, &reg);
822 if (ret)
823 return ret;
824
825 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
826 if (ret)
827 return ret;
828
829 /* Configure switch ports 0...4 (GMAC1) */
830 for (i = 0; i < 5; i++) {
831 ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
832 if (ret)
833 return ret;
834 }
835
836 for (i = 0; i < 5; i++) {
837 ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
838 if (ret)
839 return ret;
840 }
841
842 /* QM Control */
843 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
844 if (ret)
845 return ret;
846
847 /* Disable Atheros header */
848 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
849 if (ret)
850 return ret;
851
852 /* Tag priority mapping */
853 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
854 if (ret)
855 return ret;
856
857 /* Enable ARP packets to the CPU */
858 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
859 if (ret)
860 return ret;
861
862 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
863 if (ret)
864 return ret;
865
866 /* Enable broadcast packets to the CPU */
867 ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, &reg);
868 if (ret)
869 return ret;
870
871 ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
872 if (ret)
873 return ret;
874
875 return 0;
876 }
877
878 static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
879 {
880 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
881 int ret;
882
883 if (priv->model == AG7XXX_MODEL_AG953X ||
884 priv->model == AG7XXX_MODEL_AG956X) {
885 ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
886 ADVERTISE_ALL);
887 } else {
888 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
889 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
890 ADVERTISE_PAUSE_ASYM);
891 }
892 if (ret)
893 return ret;
894
895 if (priv->model == AG7XXX_MODEL_AG934X) {
896 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
897 ADVERTISE_1000FULL);
898 if (ret)
899 return ret;
900 } else if (priv->model == AG7XXX_MODEL_AG956X) {
901 ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
902 ADVERTISE_1000FULL);
903 if (ret)
904 return ret;
905 }
906
907 if (priv->model == AG7XXX_MODEL_AG953X ||
908 priv->model == AG7XXX_MODEL_AG956X)
909 return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
910 BMCR_ANENABLE | BMCR_RESET);
911
912 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
913 BMCR_ANENABLE | BMCR_RESET);
914 }
915
916 static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
917 {
918 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
919 int ret;
920 u16 reg;
921
922 if (priv->model == AG7XXX_MODEL_AG953X ||
923 priv->model == AG7XXX_MODEL_AG956X) {
924 do {
925 ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg);
926 if (ret < 0)
927 return ret;
928 mdelay(10);
929 } while (reg & BMCR_RESET);
930 } else {
931 do {
932 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
933 if (ret < 0)
934 return ret;
935 mdelay(10);
936 } while (ret & BMCR_RESET);
937 }
938
939 return 0;
940 }
941
942 static int ag933x_phy_setup_common(struct udevice *dev)
943 {
944 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
945 int i, ret, phymax;
946 u16 reg;
947
948 if (priv->model == AG7XXX_MODEL_AG933X)
949 phymax = 4;
950 else if (priv->model == AG7XXX_MODEL_AG934X ||
951 priv->model == AG7XXX_MODEL_AG953X ||
952 priv->model == AG7XXX_MODEL_AG956X)
953 phymax = 5;
954 else
955 return -EINVAL;
956
957 if (priv->interface == PHY_INTERFACE_MODE_RMII) {
958 ret = ag933x_phy_setup_reset_set(dev, phymax);
959 if (ret)
960 return ret;
961
962 ret = ag933x_phy_setup_reset_fin(dev, phymax);
963 if (ret)
964 return ret;
965
966 /* Read out link status */
967 if (priv->model == AG7XXX_MODEL_AG953X)
968 ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, &reg);
969 else
970 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
971 if (ret < 0)
972 return ret;
973
974 return 0;
975 }
976
977 /* Switch ports */
978 for (i = 0; i < phymax; i++) {
979 ret = ag933x_phy_setup_reset_set(dev, i);
980 if (ret)
981 return ret;
982 }
983
984 for (i = 0; i < phymax; i++) {
985 ret = ag933x_phy_setup_reset_fin(dev, i);
986 if (ret)
987 return ret;
988 }
989
990 for (i = 0; i < phymax; i++) {
991 /* Read out link status */
992 if (priv->model == AG7XXX_MODEL_AG953X ||
993 priv->model == AG7XXX_MODEL_AG956X)
994 ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg);
995 else
996 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
997 if (ret < 0)
998 return ret;
999 }
1000
1001 return 0;
1002 }
1003
1004 static int ag934x_phy_setup(struct udevice *dev)
1005 {
1006 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1007 int i, ret;
1008 u32 reg;
1009
1010 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1011 if (ret)
1012 return ret;
1013 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
1014 if (ret)
1015 return ret;
1016 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
1017 if (ret)
1018 return ret;
1019 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
1020 if (ret)
1021 return ret;
1022 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1023 if (ret)
1024 return ret;
1025
1026 /* AR8327/AR8328 v1.0 fixup */
1027 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
1028 if (ret)
1029 return ret;
1030 if ((reg & 0xffff) == 0x1201) {
1031 for (i = 0; i < 5; i++) {
1032 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
1033 if (ret)
1034 return ret;
1035 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
1036 if (ret)
1037 return ret;
1038 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
1039 if (ret)
1040 return ret;
1041 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
1042 if (ret)
1043 return ret;
1044 }
1045 }
1046
1047 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
1048 if (ret)
1049 return ret;
1050 reg &= ~0x70000;
1051 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
1052 if (ret)
1053 return ret;
1054
1055 return 0;
1056 }
1057
1058 static int ag956x_phy_setup(struct udevice *dev)
1059 {
1060 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1061 int i, ret;
1062 u32 reg, ctrl;
1063
1064 ret = ag7xxx_switch_reg_read(priv->bus, 0x0, &reg);
1065 if (ret)
1066 return ret;
1067 if ((reg & 0xffff) >= 0x1301)
1068 ctrl = 0xc74164de;
1069 else
1070 ctrl = 0xc74164d0;
1071
1072 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
1073 if (ret)
1074 return ret;
1075
1076 ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
1077 if (ret)
1078 return ret;
1079
1080 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
1081 if (ret)
1082 return ret;
1083
1084 /*
1085 * Values suggested by the switch team when s17 in sgmii
1086 * configuration. 0x10(S17_PWS_REG) = 0x602613a0
1087 */
1088 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
1089 if (ret)
1090 return ret;
1091
1092 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
1093 if (ret)
1094 return ret;
1095
1096 /* AR8337/AR8334 v1.0 fixup */
1097 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
1098 if (ret)
1099 return ret;
1100 if ((reg & 0xffff) == 0x1301) {
1101 for (i = 0; i < 5; i++) {
1102 /* Turn on Gigabit clock */
1103 ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
1104 if (ret)
1105 return ret;
1106 ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
1107 if (ret)
1108 return ret;
1109 }
1110 }
1111
1112 return 0;
1113 }
1114
1115 static int ag7xxx_mac_probe(struct udevice *dev)
1116 {
1117 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1118 int ret;
1119
1120 ag7xxx_hw_setup(dev);
1121 ret = ag7xxx_mii_setup(dev);
1122 if (ret)
1123 return ret;
1124
1125 ag7xxx_eth_write_hwaddr(dev);
1126
1127 if (priv->model == AG7XXX_MODEL_AG933X) {
1128 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1129 ret = ag933x_phy_setup_wan(dev);
1130 else
1131 ret = ag933x_phy_setup_lan(dev);
1132 } else if (priv->model == AG7XXX_MODEL_AG953X) {
1133 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1134 ret = ag953x_phy_setup_wan(dev);
1135 else
1136 ret = ag953x_phy_setup_lan(dev);
1137 } else if (priv->model == AG7XXX_MODEL_AG934X) {
1138 ret = ag934x_phy_setup(dev);
1139 } else if (priv->model == AG7XXX_MODEL_AG956X) {
1140 ret = ag956x_phy_setup(dev);
1141 } else {
1142 return -EINVAL;
1143 }
1144
1145 if (ret)
1146 return ret;
1147
1148 return ag933x_phy_setup_common(dev);
1149 }
1150
1151 static int ag7xxx_mdio_probe(struct udevice *dev)
1152 {
1153 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1154 struct mii_dev *bus = mdio_alloc();
1155
1156 if (!bus)
1157 return -ENOMEM;
1158
1159 bus->read = ag7xxx_mdio_read;
1160 bus->write = ag7xxx_mdio_write;
1161 snprintf(bus->name, sizeof(bus->name), dev->name);
1162
1163 bus->priv = (void *)priv;
1164
1165 return mdio_register(bus);
1166 }
1167
1168 static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
1169 {
1170 int offset;
1171
1172 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
1173 if (offset <= 0) {
1174 debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
1175 return -EINVAL;
1176 }
1177
1178 offset = fdt_parent_offset(gd->fdt_blob, offset);
1179 if (offset <= 0) {
1180 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
1181 __func__, offset);
1182 return -EINVAL;
1183 }
1184
1185 offset = fdt_parent_offset(gd->fdt_blob, offset);
1186 if (offset <= 0) {
1187 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
1188 __func__, offset);
1189 return -EINVAL;
1190 }
1191
1192 return offset;
1193 }
1194
1195 static int ag7xxx_eth_probe(struct udevice *dev)
1196 {
1197 struct eth_pdata *pdata = dev_get_platdata(dev);
1198 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1199 void __iomem *iobase, *phyiobase;
1200 int ret, phyreg;
1201
1202 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1203 ret = ag7xxx_get_phy_iface_offset(dev);
1204 if (ret <= 0)
1205 return ret;
1206 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
1207
1208 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
1209 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
1210
1211 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
1212 __func__, iobase, phyiobase, priv);
1213 priv->regs = iobase;
1214 priv->phyregs = phyiobase;
1215 priv->interface = pdata->phy_interface;
1216 priv->model = dev_get_driver_data(dev);
1217
1218 ret = ag7xxx_mdio_probe(dev);
1219 if (ret)
1220 return ret;
1221
1222 priv->bus = miiphy_get_dev_by_name(dev->name);
1223
1224 ret = ag7xxx_mac_probe(dev);
1225 debug("%s, ret=%d\n", __func__, ret);
1226
1227 return ret;
1228 }
1229
1230 static int ag7xxx_eth_remove(struct udevice *dev)
1231 {
1232 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1233
1234 free(priv->phydev);
1235 mdio_unregister(priv->bus);
1236 mdio_free(priv->bus);
1237
1238 return 0;
1239 }
1240
1241 static const struct eth_ops ag7xxx_eth_ops = {
1242 .start = ag7xxx_eth_start,
1243 .send = ag7xxx_eth_send,
1244 .recv = ag7xxx_eth_recv,
1245 .free_pkt = ag7xxx_eth_free_pkt,
1246 .stop = ag7xxx_eth_stop,
1247 .write_hwaddr = ag7xxx_eth_write_hwaddr,
1248 };
1249
1250 static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
1251 {
1252 struct eth_pdata *pdata = dev_get_platdata(dev);
1253 const char *phy_mode;
1254 int ret;
1255
1256 pdata->iobase = devfdt_get_addr(dev);
1257 pdata->phy_interface = -1;
1258
1259 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1260 ret = ag7xxx_get_phy_iface_offset(dev);
1261 if (ret <= 0)
1262 return ret;
1263
1264 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
1265 if (phy_mode)
1266 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1267 if (pdata->phy_interface == -1) {
1268 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1269 return -EINVAL;
1270 }
1271
1272 return 0;
1273 }
1274
1275 static const struct udevice_id ag7xxx_eth_ids[] = {
1276 { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
1277 { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
1278 { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
1279 { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
1280 { }
1281 };
1282
1283 U_BOOT_DRIVER(eth_ag7xxx) = {
1284 .name = "eth_ag7xxx",
1285 .id = UCLASS_ETH,
1286 .of_match = ag7xxx_eth_ids,
1287 .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
1288 .probe = ag7xxx_eth_probe,
1289 .remove = ag7xxx_eth_remove,
1290 .ops = &ag7xxx_eth_ops,
1291 .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
1292 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1293 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1294 };
"Das U-Boot" Source Tree