2 * Atheros AR71xx / AR9xxx GMAC driver
4 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/compiler.h>
15 #include <linux/err.h>
16 #include <linux/mii.h>
20 #include <mach/ath79.h>
22 DECLARE_GLOBAL_DATA_PTR
;
29 /* MAC Configuration 1 */
30 #define AG7XXX_ETH_CFG1 0x00
31 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
32 #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
33 #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
34 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
35 #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
36 #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
38 /* MAC Configuration 2 */
39 #define AG7XXX_ETH_CFG2 0x04
40 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
41 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
42 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
43 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
44 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
45 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
46 #define AG7XXX_ETH_CFG2_FDX BIT(0)
48 /* MII Configuration */
49 #define AG7XXX_ETH_MII_MGMT_CFG 0x20
50 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
53 #define AG7XXX_ETH_MII_MGMT_CMD 0x24
54 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
57 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
58 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
61 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
64 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
67 #define AG7XXX_ETH_MII_MGMT_IND 0x34
68 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
69 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
71 /* STA Address 1 & 2 */
72 #define AG7XXX_ETH_ADDR1 0x40
73 #define AG7XXX_ETH_ADDR2 0x44
75 /* ETH Configuration 0 - 5 */
76 #define AG7XXX_ETH_FIFO_CFG_0 0x48
77 #define AG7XXX_ETH_FIFO_CFG_1 0x4c
78 #define AG7XXX_ETH_FIFO_CFG_2 0x50
79 #define AG7XXX_ETH_FIFO_CFG_3 0x54
80 #define AG7XXX_ETH_FIFO_CFG_4 0x58
81 #define AG7XXX_ETH_FIFO_CFG_5 0x5c
83 /* DMA Transfer Control for Queue 0 */
84 #define AG7XXX_ETH_DMA_TX_CTRL 0x180
85 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
87 /* Descriptor Address for Queue 0 Tx */
88 #define AG7XXX_ETH_DMA_TX_DESC 0x184
91 #define AG7XXX_ETH_DMA_TX_STATUS 0x188
94 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
95 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
97 /* Pointer to Rx Descriptor */
98 #define AG7XXX_ETH_DMA_RX_DESC 0x190
101 #define AG7XXX_ETH_DMA_RX_STATUS 0x194
103 /* Custom register at 0x18070000 */
104 #define AG7XXX_GMAC_ETH_CFG 0x00
105 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
106 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
107 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
108 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
109 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
110 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
111 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
112 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
113 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
115 #define CONFIG_TX_DESCR_NUM 8
116 #define CONFIG_RX_DESCR_NUM 8
117 #define CONFIG_ETH_BUFSIZE 2048
118 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
119 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
121 /* DMA descriptor. */
122 struct ag7xxx_dma_desc
{
124 #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
125 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
126 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
127 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
133 struct ar7xxx_eth_priv
{
134 struct ag7xxx_dma_desc tx_mac_descrtable
[CONFIG_TX_DESCR_NUM
];
135 struct ag7xxx_dma_desc rx_mac_descrtable
[CONFIG_RX_DESCR_NUM
];
136 char txbuffs
[TX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
137 char rxbuffs
[RX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
140 void __iomem
*phyregs
;
142 struct eth_device
*dev
;
143 struct phy_device
*phydev
;
149 enum ag7xxx_model model
;
153 * Switch and MDIO access
155 static int ag7xxx_switch_read(struct mii_dev
*bus
, int addr
, int reg
, u16
*val
)
157 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
158 void __iomem
*regs
= priv
->phyregs
;
161 writel(0x0, regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
162 writel((addr
<< AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT
) | reg
,
163 regs
+ AG7XXX_ETH_MII_MGMT_ADDRESS
);
164 writel(AG7XXX_ETH_MII_MGMT_CMD_READ
,
165 regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
167 ret
= wait_for_bit_le32(regs
+ AG7XXX_ETH_MII_MGMT_IND
,
168 AG7XXX_ETH_MII_MGMT_IND_BUSY
, 0, 1000, 0);
172 *val
= readl(regs
+ AG7XXX_ETH_MII_MGMT_STATUS
) & 0xffff;
173 writel(0x0, regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
178 static int ag7xxx_switch_write(struct mii_dev
*bus
, int addr
, int reg
, u16 val
)
180 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
181 void __iomem
*regs
= priv
->phyregs
;
184 writel((addr
<< AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT
) | reg
,
185 regs
+ AG7XXX_ETH_MII_MGMT_ADDRESS
);
186 writel(val
, regs
+ AG7XXX_ETH_MII_MGMT_CTRL
);
188 ret
= wait_for_bit_le32(regs
+ AG7XXX_ETH_MII_MGMT_IND
,
189 AG7XXX_ETH_MII_MGMT_IND_BUSY
, 0, 1000, 0);
194 static int ag7xxx_switch_reg_read(struct mii_dev
*bus
, int reg
, u32
*val
)
196 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
204 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
207 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
213 ret
= ag7xxx_switch_write(bus
, phy_addr
, reg_addr
, reg
>> 9);
217 phy_temp
= ((reg
>> 6) & 0x7) | 0x10;
218 reg_temp
= (reg
>> 1) & 0x1e;
221 ret
= ag7xxx_switch_read(bus
, phy_temp
, reg_temp
| 0, &rv
);
226 ret
= ag7xxx_switch_read(bus
, phy_temp
, reg_temp
| 1, &rv
);
234 static int ag7xxx_switch_reg_write(struct mii_dev
*bus
, int reg
, u32 val
)
236 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
243 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
246 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
252 ret
= ag7xxx_switch_write(bus
, phy_addr
, reg_addr
, reg
>> 9);
256 phy_temp
= ((reg
>> 6) & 0x7) | 0x10;
257 reg_temp
= (reg
>> 1) & 0x1e;
260 * The switch on AR933x has some special register behavior, which
261 * expects particular write order of their nibbles:
262 * 0x40 ..... MSB first, LSB second
263 * 0x50 ..... MSB first, LSB second
264 * 0x98 ..... LSB first, MSB second
265 * others ... don't care
267 if ((priv
->model
== AG7XXX_MODEL_AG933X
) && (reg
== 0x98)) {
268 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 0, val
& 0xffff);
272 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 1, val
>> 16);
276 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 1, val
>> 16);
280 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 0, val
& 0xffff);
288 static int ag7xxx_mdio_rw(struct mii_dev
*bus
, int addr
, int reg
, u32 val
)
293 /* No idea if this is long enough or too long */
294 int timeout_ms
= 1000;
296 /* Dummy read followed by PHY read/write command. */
297 ret
= ag7xxx_switch_reg_read(bus
, 0x98, &data
);
300 data
= val
| (reg
<< 16) | (addr
<< 21) | BIT(30) | BIT(31);
301 ret
= ag7xxx_switch_reg_write(bus
, 0x98, data
);
305 start
= get_timer(0);
307 /* Wait for operation to finish */
309 ret
= ag7xxx_switch_reg_read(bus
, 0x98, &data
);
313 if (get_timer(start
) > timeout_ms
)
315 } while (data
& BIT(31));
317 return data
& 0xffff;
320 static int ag7xxx_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
322 return ag7xxx_mdio_rw(bus
, addr
, reg
, BIT(27));
325 static int ag7xxx_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
330 ret
= ag7xxx_mdio_rw(bus
, addr
, reg
, val
);
339 static void ag7xxx_dma_clean_tx(struct udevice
*dev
)
341 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
342 struct ag7xxx_dma_desc
*curr
, *next
;
346 for (i
= 0; i
< CONFIG_TX_DESCR_NUM
; i
++) {
347 curr
= &priv
->tx_mac_descrtable
[i
];
348 next
= &priv
->tx_mac_descrtable
[(i
+ 1) % CONFIG_TX_DESCR_NUM
];
350 curr
->data_addr
= virt_to_phys(&priv
->txbuffs
[i
* CONFIG_ETH_BUFSIZE
]);
351 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
352 curr
->next_desc
= virt_to_phys(next
);
355 priv
->tx_currdescnum
= 0;
357 /* Cache: Flush descriptors, don't care about buffers. */
358 start
= (u32
)(&priv
->tx_mac_descrtable
[0]);
359 end
= start
+ sizeof(priv
->tx_mac_descrtable
);
360 flush_dcache_range(start
, end
);
363 static void ag7xxx_dma_clean_rx(struct udevice
*dev
)
365 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
366 struct ag7xxx_dma_desc
*curr
, *next
;
370 for (i
= 0; i
< CONFIG_RX_DESCR_NUM
; i
++) {
371 curr
= &priv
->rx_mac_descrtable
[i
];
372 next
= &priv
->rx_mac_descrtable
[(i
+ 1) % CONFIG_RX_DESCR_NUM
];
374 curr
->data_addr
= virt_to_phys(&priv
->rxbuffs
[i
* CONFIG_ETH_BUFSIZE
]);
375 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
376 curr
->next_desc
= virt_to_phys(next
);
379 priv
->rx_currdescnum
= 0;
381 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
382 start
= (u32
)(&priv
->rx_mac_descrtable
[0]);
383 end
= start
+ sizeof(priv
->rx_mac_descrtable
);
384 flush_dcache_range(start
, end
);
385 invalidate_dcache_range(start
, end
);
387 start
= (u32
)&priv
->rxbuffs
;
388 end
= start
+ sizeof(priv
->rxbuffs
);
389 invalidate_dcache_range(start
, end
);
395 static int ag7xxx_eth_send(struct udevice
*dev
, void *packet
, int length
)
397 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
398 struct ag7xxx_dma_desc
*curr
;
401 curr
= &priv
->tx_mac_descrtable
[priv
->tx_currdescnum
];
403 /* Cache: Invalidate descriptor. */
405 end
= start
+ sizeof(*curr
);
406 invalidate_dcache_range(start
, end
);
408 if (!(curr
->config
& AG7XXX_DMADESC_IS_EMPTY
)) {
409 printf("ag7xxx: Out of TX DMA descriptors!\n");
413 /* Copy the packet into the data buffer. */
414 memcpy(phys_to_virt(curr
->data_addr
), packet
, length
);
415 curr
->config
= length
& AG7XXX_DMADESC_PKT_SIZE_MASK
;
417 /* Cache: Flush descriptor, Flush buffer. */
419 end
= start
+ sizeof(*curr
);
420 flush_dcache_range(start
, end
);
421 start
= (u32
)phys_to_virt(curr
->data_addr
);
422 end
= start
+ length
;
423 flush_dcache_range(start
, end
);
425 /* Load the DMA descriptor and start TX DMA. */
426 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE
,
427 priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
);
429 /* Switch to next TX descriptor. */
430 priv
->tx_currdescnum
= (priv
->tx_currdescnum
+ 1) % CONFIG_TX_DESCR_NUM
;
435 static int ag7xxx_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
437 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
438 struct ag7xxx_dma_desc
*curr
;
439 u32 start
, end
, length
;
441 curr
= &priv
->rx_mac_descrtable
[priv
->rx_currdescnum
];
443 /* Cache: Invalidate descriptor. */
445 end
= start
+ sizeof(*curr
);
446 invalidate_dcache_range(start
, end
);
448 /* No packets received. */
449 if (curr
->config
& AG7XXX_DMADESC_IS_EMPTY
)
452 length
= curr
->config
& AG7XXX_DMADESC_PKT_SIZE_MASK
;
454 /* Cache: Invalidate buffer. */
455 start
= (u32
)phys_to_virt(curr
->data_addr
);
456 end
= start
+ length
;
457 invalidate_dcache_range(start
, end
);
459 /* Receive one packet and return length. */
460 *packetp
= phys_to_virt(curr
->data_addr
);
464 static int ag7xxx_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
467 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
468 struct ag7xxx_dma_desc
*curr
;
471 curr
= &priv
->rx_mac_descrtable
[priv
->rx_currdescnum
];
473 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
475 /* Cache: Flush descriptor. */
477 end
= start
+ sizeof(*curr
);
478 flush_dcache_range(start
, end
);
480 /* Switch to next RX descriptor. */
481 priv
->rx_currdescnum
= (priv
->rx_currdescnum
+ 1) % CONFIG_RX_DESCR_NUM
;
486 static int ag7xxx_eth_start(struct udevice
*dev
)
488 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
490 /* FIXME: Check if link up */
492 /* Clear the DMA rings. */
493 ag7xxx_dma_clean_tx(dev
);
494 ag7xxx_dma_clean_rx(dev
);
496 /* Load DMA descriptors and start the RX DMA. */
497 writel(virt_to_phys(&priv
->tx_mac_descrtable
[priv
->tx_currdescnum
]),
498 priv
->regs
+ AG7XXX_ETH_DMA_TX_DESC
);
499 writel(virt_to_phys(&priv
->rx_mac_descrtable
[priv
->rx_currdescnum
]),
500 priv
->regs
+ AG7XXX_ETH_DMA_RX_DESC
);
501 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE
,
502 priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
);
507 static void ag7xxx_eth_stop(struct udevice
*dev
)
509 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
511 /* Stop the TX DMA. */
512 writel(0, priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
);
513 wait_for_bit_le32(priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
, ~0, 0,
516 /* Stop the RX DMA. */
517 writel(0, priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
);
518 wait_for_bit_le32(priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
, ~0, 0,
525 static int ag7xxx_eth_write_hwaddr(struct udevice
*dev
)
527 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
528 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
529 unsigned char *mac
= pdata
->enetaddr
;
530 u32 macid_lo
, macid_hi
;
532 macid_hi
= mac
[3] | (mac
[2] << 8) | (mac
[1] << 16) | (mac
[0] << 24);
533 macid_lo
= (mac
[5] << 16) | (mac
[4] << 24);
535 writel(macid_lo
, priv
->regs
+ AG7XXX_ETH_ADDR1
);
536 writel(macid_hi
, priv
->regs
+ AG7XXX_ETH_ADDR2
);
541 static void ag7xxx_hw_setup(struct udevice
*dev
)
543 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
546 setbits_be32(priv
->regs
+ AG7XXX_ETH_CFG1
,
547 AG7XXX_ETH_CFG1_RX_RST
| AG7XXX_ETH_CFG1_TX_RST
|
548 AG7XXX_ETH_CFG1_SOFT_RST
);
552 writel(AG7XXX_ETH_CFG1_RX_EN
| AG7XXX_ETH_CFG1_TX_EN
,
553 priv
->regs
+ AG7XXX_ETH_CFG1
);
555 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
556 speed
= AG7XXX_ETH_CFG2_IF_10_100
;
558 speed
= AG7XXX_ETH_CFG2_IF_1000
;
560 clrsetbits_be32(priv
->regs
+ AG7XXX_ETH_CFG2
,
561 AG7XXX_ETH_CFG2_IF_SPEED_MASK
,
562 speed
| AG7XXX_ETH_CFG2_PAD_CRC_EN
|
563 AG7XXX_ETH_CFG2_LEN_CHECK
);
565 writel(0xfff0000, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_1
);
566 writel(0x1fff, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_2
);
568 writel(0x1f00, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_0
);
569 setbits_be32(priv
->regs
+ AG7XXX_ETH_FIFO_CFG_4
, 0x3ffff);
570 writel(0x10ffff, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_1
);
571 writel(0xaaa0555, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_2
);
572 writel(0x7eccf, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_5
);
573 writel(0x1f00140, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_3
);
576 static int ag7xxx_mii_get_div(void)
578 ulong freq
= get_bus_freq(0);
580 switch (freq
/ 1000000) {
581 case 150: return 0x7;
582 case 175: return 0x5;
583 case 200: return 0x4;
584 case 210: return 0x9;
585 case 220: return 0x9;
590 static int ag7xxx_mii_setup(struct udevice
*dev
)
592 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
593 int i
, ret
, div
= ag7xxx_mii_get_div();
596 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
597 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
598 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
602 if (priv
->model
== AG7XXX_MODEL_AG934X
) {
603 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET
| 0x4,
604 priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
605 writel(0x4, priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
609 for (i
= 0; i
< 10; i
++) {
610 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET
| div
,
611 priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
612 writel(div
, priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
614 /* Check the switch */
615 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x10c, ®
);
619 if (reg
!= 0x18007fff)
628 static int ag933x_phy_setup_wan(struct udevice
*dev
)
630 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
632 /* Configure switch port 4 (GMAC0) */
633 return ag7xxx_mdio_write(priv
->bus
, 4, 0, MII_BMCR
, 0x9000);
636 static int ag933x_phy_setup_lan(struct udevice
*dev
)
638 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
642 /* Reset the switch */
643 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
647 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0, reg
);
652 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
655 } while (reg
& BIT(31));
657 /* Configure switch ports 0...3 (GMAC1) */
658 for (i
= 0; i
< 4; i
++) {
659 ret
= ag7xxx_mdio_write(priv
->bus
, 0x4, 0, MII_BMCR
, 0x9000);
664 /* Enable CPU port */
665 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x78, BIT(8));
669 for (i
= 0; i
< 4; i
++) {
670 ret
= ag7xxx_switch_reg_write(priv
->bus
, i
* 0x100, BIT(9));
676 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x38, 0xc000050e);
680 /* Disable Atheros header */
681 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x104, 0x4004);
685 /* Tag priority mapping */
686 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x70, 0xfa50);
690 /* Enable ARP packets to the CPU */
691 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x5c, ®
);
695 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x5c, reg
);
702 static int ag933x_phy_setup_reset_set(struct udevice
*dev
, int port
)
704 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
707 ret
= ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_ADVERTISE
,
708 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
709 ADVERTISE_PAUSE_ASYM
);
713 if (priv
->model
== AG7XXX_MODEL_AG934X
) {
714 ret
= ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_CTRL1000
,
720 return ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_BMCR
,
721 BMCR_ANENABLE
| BMCR_RESET
);
724 static int ag933x_phy_setup_reset_fin(struct udevice
*dev
, int port
)
726 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
730 ret
= ag7xxx_mdio_read(priv
->bus
, port
, 0, MII_BMCR
);
734 } while (ret
& BMCR_RESET
);
739 static int ag933x_phy_setup_common(struct udevice
*dev
)
741 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
744 if (priv
->model
== AG7XXX_MODEL_AG933X
)
746 else if (priv
->model
== AG7XXX_MODEL_AG934X
)
751 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
) {
752 ret
= ag933x_phy_setup_reset_set(dev
, phymax
);
756 ret
= ag933x_phy_setup_reset_fin(dev
, phymax
);
760 /* Read out link status */
761 ret
= ag7xxx_mdio_read(priv
->bus
, phymax
, 0, MII_MIPSCR
);
769 for (i
= 0; i
< phymax
; i
++) {
770 ret
= ag933x_phy_setup_reset_set(dev
, i
);
775 for (i
= 0; i
< phymax
; i
++) {
776 ret
= ag933x_phy_setup_reset_fin(dev
, i
);
781 for (i
= 0; i
< phymax
; i
++) {
782 /* Read out link status */
783 ret
= ag7xxx_mdio_read(priv
->bus
, i
, 0, MII_MIPSCR
);
791 static int ag934x_phy_setup(struct udevice
*dev
)
793 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
797 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x624, 0x7f7f7f7f);
800 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x10, 0x40000000);
803 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x4, 0x07600000);
806 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0xc, 0x01000000);
809 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x7c, 0x0000007e);
813 /* AR8327/AR8328 v1.0 fixup */
814 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
817 if ((reg
& 0xffff) == 0x1201) {
818 for (i
= 0; i
< 5; i
++) {
819 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1d, 0x0);
822 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1e, 0x02ea);
825 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1d, 0x3d);
828 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1e, 0x68a0);
834 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x66c, ®
);
838 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x66c, reg
);
845 static int ag7xxx_mac_probe(struct udevice
*dev
)
847 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
850 ag7xxx_hw_setup(dev
);
851 ret
= ag7xxx_mii_setup(dev
);
855 ag7xxx_eth_write_hwaddr(dev
);
857 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
858 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
859 ret
= ag933x_phy_setup_wan(dev
);
861 ret
= ag933x_phy_setup_lan(dev
);
862 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
863 ret
= ag934x_phy_setup(dev
);
871 return ag933x_phy_setup_common(dev
);
874 static int ag7xxx_mdio_probe(struct udevice
*dev
)
876 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
877 struct mii_dev
*bus
= mdio_alloc();
882 bus
->read
= ag7xxx_mdio_read
;
883 bus
->write
= ag7xxx_mdio_write
;
884 snprintf(bus
->name
, sizeof(bus
->name
), dev
->name
);
886 bus
->priv
= (void *)priv
;
888 return mdio_register(bus
);
891 static int ag7xxx_get_phy_iface_offset(struct udevice
*dev
)
895 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev_of_offset(dev
), "phy");
897 debug("%s: PHY OF node not found (ret=%i)\n", __func__
, offset
);
901 offset
= fdt_parent_offset(gd
->fdt_blob
, offset
);
903 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
908 offset
= fdt_parent_offset(gd
->fdt_blob
, offset
);
910 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
918 static int ag7xxx_eth_probe(struct udevice
*dev
)
920 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
921 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
922 void __iomem
*iobase
, *phyiobase
;
925 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
926 ret
= ag7xxx_get_phy_iface_offset(dev
);
929 phyreg
= fdtdec_get_int(gd
->fdt_blob
, ret
, "reg", -1);
931 iobase
= map_physmem(pdata
->iobase
, 0x200, MAP_NOCACHE
);
932 phyiobase
= map_physmem(phyreg
, 0x200, MAP_NOCACHE
);
934 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
935 __func__
, iobase
, phyiobase
, priv
);
937 priv
->phyregs
= phyiobase
;
938 priv
->interface
= pdata
->phy_interface
;
939 priv
->model
= dev_get_driver_data(dev
);
941 ret
= ag7xxx_mdio_probe(dev
);
945 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
947 ret
= ag7xxx_mac_probe(dev
);
948 debug("%s, ret=%d\n", __func__
, ret
);
953 static int ag7xxx_eth_remove(struct udevice
*dev
)
955 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
958 mdio_unregister(priv
->bus
);
959 mdio_free(priv
->bus
);
964 static const struct eth_ops ag7xxx_eth_ops
= {
965 .start
= ag7xxx_eth_start
,
966 .send
= ag7xxx_eth_send
,
967 .recv
= ag7xxx_eth_recv
,
968 .free_pkt
= ag7xxx_eth_free_pkt
,
969 .stop
= ag7xxx_eth_stop
,
970 .write_hwaddr
= ag7xxx_eth_write_hwaddr
,
973 static int ag7xxx_eth_ofdata_to_platdata(struct udevice
*dev
)
975 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
976 const char *phy_mode
;
979 pdata
->iobase
= devfdt_get_addr(dev
);
980 pdata
->phy_interface
= -1;
982 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
983 ret
= ag7xxx_get_phy_iface_offset(dev
);
987 phy_mode
= fdt_getprop(gd
->fdt_blob
, ret
, "phy-mode", NULL
);
989 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
990 if (pdata
->phy_interface
== -1) {
991 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
998 static const struct udevice_id ag7xxx_eth_ids
[] = {
999 { .compatible
= "qca,ag933x-mac", .data
= AG7XXX_MODEL_AG933X
},
1000 { .compatible
= "qca,ag934x-mac", .data
= AG7XXX_MODEL_AG934X
},
1004 U_BOOT_DRIVER(eth_ag7xxx
) = {
1005 .name
= "eth_ag7xxx",
1007 .of_match
= ag7xxx_eth_ids
,
1008 .ofdata_to_platdata
= ag7xxx_eth_ofdata_to_platdata
,
1009 .probe
= ag7xxx_eth_probe
,
1010 .remove
= ag7xxx_eth_remove
,
1011 .ops
= &ag7xxx_eth_ops
,
1012 .priv_auto_alloc_size
= sizeof(struct ar7xxx_eth_priv
),
1013 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
1014 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,