2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <fdt_support.h>
18 #include <asm/cache.h>
19 #include <asm/dma-mapping.h>
21 #include "altera_tse.h"
23 DECLARE_GLOBAL_DATA_PTR
;
25 static inline void alt_sgdma_construct_descriptor(
26 struct alt_sgdma_descriptor
*desc
,
27 struct alt_sgdma_descriptor
*next
,
33 int write_fixed_or_sop
)
38 * Mark the "next" descriptor as "not" owned by hardware. This prevents
39 * The SGDMA controller from continuing to process the chain.
41 next
->descriptor_control
= next
->descriptor_control
&
42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
;
44 memset(desc
, 0, sizeof(struct alt_sgdma_descriptor
));
45 desc
->source
= virt_to_phys(read_addr
);
46 desc
->destination
= virt_to_phys(write_addr
);
47 desc
->next
= virt_to_phys(next
);
48 desc
->bytes_to_transfer
= length_or_eop
;
51 * Set the descriptor control block as follows:
52 * - Set "owned by hardware" bit
53 * - Optionally set "generate EOP" bit
54 * - Optionally set the "read from fixed address" bit
55 * - Optionally set the "write to fixed address bit (which serves
56 * serves as a "generate SOP" control bit in memory-to-stream mode).
57 * - Set the 4-bit atlantic channel, if specified
59 * Note this step is performed after all other descriptor information
60 * has been filled out so that, if the controller already happens to be
61 * pointing at this descriptor, it will not run (via the "owned by
62 * hardware" bit) until all other descriptor has been set up.
64 val
= ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
;
66 val
|= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK
;
68 val
|= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK
;
69 if (write_fixed_or_sop
)
70 val
|= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK
;
71 desc
->descriptor_control
= val
;
74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers
*regs
)
79 /* Wait for the descriptor (chain) to complete */
82 status
= readl(®s
->status
);
83 if (!(status
& ALT_SGDMA_STATUS_BUSY_MSK
))
85 if (get_timer(ctime
) > ALT_TSE_SGDMA_BUSY_TIMEOUT
) {
87 debug("sgdma timeout\n");
93 writel(0, ®s
->control
);
95 writel(0xff, ®s
->status
);
100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers
*regs
,
101 struct alt_sgdma_descriptor
*desc
)
105 /* Point the controller at the descriptor */
106 writel(virt_to_phys(desc
), ®s
->next_descriptor_pointer
);
109 * Set up SGDMA controller to:
110 * - Disable interrupt generation
111 * - Run once a valid descriptor is written to controller
112 * - Stop on an error with any particular descriptor
114 val
= ALT_SGDMA_CONTROL_RUN_MSK
| ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK
;
115 writel(val
, ®s
->control
);
120 static void tse_adjust_link(struct altera_tse_priv
*priv
,
121 struct phy_device
*phydev
)
123 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
127 debug("%s: No link.\n", phydev
->dev
->name
);
131 refvar
= readl(&mac_dev
->command_config
);
134 refvar
|= ALTERA_TSE_CMD_HD_ENA_MSK
;
136 refvar
&= ~ALTERA_TSE_CMD_HD_ENA_MSK
;
138 switch (phydev
->speed
) {
140 refvar
|= ALTERA_TSE_CMD_ETH_SPEED_MSK
;
141 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
144 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
145 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
148 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
149 refvar
|= ALTERA_TSE_CMD_ENA_10_MSK
;
152 writel(refvar
, &mac_dev
->command_config
);
155 static int altera_tse_send_sgdma(struct udevice
*dev
, void *packet
, int length
)
157 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
158 struct alt_sgdma_descriptor
*tx_desc
= priv
->tx_desc
;
160 alt_sgdma_construct_descriptor(
163 packet
, /* read addr */
164 NULL
, /* write addr */
165 length
, /* length or EOP ,will change for each tx */
168 1 /* write fixed or sop */
171 /* send the packet */
172 alt_sgdma_start_transfer(priv
->sgdma_tx
, tx_desc
);
173 alt_sgdma_wait_transfer(priv
->sgdma_tx
);
174 debug("sent %d bytes\n", tx_desc
->actual_bytes_transferred
);
176 return tx_desc
->actual_bytes_transferred
;
179 static int altera_tse_recv_sgdma(struct udevice
*dev
, int flags
,
182 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
183 struct alt_sgdma_descriptor
*rx_desc
= priv
->rx_desc
;
186 if (rx_desc
->descriptor_status
&
187 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK
) {
188 alt_sgdma_wait_transfer(priv
->sgdma_rx
);
189 packet_length
= rx_desc
->actual_bytes_transferred
;
190 debug("recv %d bytes\n", packet_length
);
191 *packetp
= priv
->rx_buf
;
193 return packet_length
;
199 static int altera_tse_free_pkt_sgdma(struct udevice
*dev
, uchar
*packet
,
202 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
203 struct alt_sgdma_descriptor
*rx_desc
= priv
->rx_desc
;
205 alt_sgdma_construct_descriptor(
208 NULL
, /* read addr */
209 priv
->rx_buf
, /* write addr */
210 0, /* length or EOP */
213 0 /* write fixed or sop */
216 /* setup the sgdma */
217 alt_sgdma_start_transfer(priv
->sgdma_rx
, rx_desc
);
218 debug("recv setup\n");
223 static void altera_tse_stop_mac(struct altera_tse_priv
*priv
)
225 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
230 writel(ALTERA_TSE_CMD_SW_RESET_MSK
, &mac_dev
->command_config
);
231 ctime
= get_timer(0);
233 status
= readl(&mac_dev
->command_config
);
234 if (!(status
& ALTERA_TSE_CMD_SW_RESET_MSK
))
236 if (get_timer(ctime
) > ALT_TSE_SW_RESET_TIMEOUT
) {
237 debug("Reset mac timeout\n");
243 static void altera_tse_stop_sgdma(struct udevice
*dev
)
245 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
246 struct alt_sgdma_registers
*rx_sgdma
= priv
->sgdma_rx
;
247 struct alt_sgdma_registers
*tx_sgdma
= priv
->sgdma_tx
;
248 struct alt_sgdma_descriptor
*rx_desc
= priv
->rx_desc
;
251 /* clear rx desc & wait for sgdma to complete */
252 rx_desc
->descriptor_control
= 0;
253 writel(0, &rx_sgdma
->control
);
254 ret
= alt_sgdma_wait_transfer(rx_sgdma
);
255 if (ret
== -ETIMEDOUT
)
256 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
,
259 writel(0, &tx_sgdma
->control
);
260 ret
= alt_sgdma_wait_transfer(tx_sgdma
);
261 if (ret
== -ETIMEDOUT
)
262 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
,
266 static void msgdma_reset(struct msgdma_csr
*csr
)
272 writel(MSGDMA_CSR_STAT_MASK
, &csr
->status
);
273 writel(MSGDMA_CSR_CTL_RESET
, &csr
->control
);
274 ctime
= get_timer(0);
276 status
= readl(&csr
->status
);
277 if (!(status
& MSGDMA_CSR_STAT_RESETTING
))
279 if (get_timer(ctime
) > ALT_TSE_SW_RESET_TIMEOUT
) {
280 debug("Reset msgdma timeout\n");
285 writel(MSGDMA_CSR_STAT_MASK
, &csr
->status
);
288 static u32
msgdma_wait(struct msgdma_csr
*csr
)
293 /* Wait for the descriptor to complete */
294 ctime
= get_timer(0);
296 status
= readl(&csr
->status
);
297 if (!(status
& MSGDMA_CSR_STAT_BUSY
))
299 if (get_timer(ctime
) > ALT_TSE_SGDMA_BUSY_TIMEOUT
) {
300 debug("sgdma timeout\n");
305 writel(MSGDMA_CSR_STAT_MASK
, &csr
->status
);
310 static int altera_tse_send_msgdma(struct udevice
*dev
, void *packet
,
313 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
314 struct msgdma_extended_desc
*desc
= priv
->tx_desc
;
315 u32 tx_buf
= virt_to_phys(packet
);
318 writel(tx_buf
, &desc
->read_addr_lo
);
319 writel(0, &desc
->read_addr_hi
);
320 writel(0, &desc
->write_addr_lo
);
321 writel(0, &desc
->write_addr_hi
);
322 writel(length
, &desc
->len
);
323 writel(0, &desc
->burst_seq_num
);
324 writel(MSGDMA_DESC_TX_STRIDE
, &desc
->stride
);
325 writel(MSGDMA_DESC_CTL_TX_SINGLE
, &desc
->control
);
326 status
= msgdma_wait(priv
->sgdma_tx
);
327 debug("sent %d bytes, status %08x\n", length
, status
);
332 static int altera_tse_recv_msgdma(struct udevice
*dev
, int flags
,
335 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
336 struct msgdma_csr
*csr
= priv
->sgdma_rx
;
337 struct msgdma_response
*resp
= priv
->rx_resp
;
338 u32 level
, length
, status
;
340 level
= readl(&csr
->resp_fill_level
);
341 if (level
& 0xffff) {
342 length
= readl(&resp
->bytes_transferred
);
343 status
= readl(&resp
->status
);
344 debug("recv %d bytes, status %08x\n", length
, status
);
345 *packetp
= priv
->rx_buf
;
353 static int altera_tse_free_pkt_msgdma(struct udevice
*dev
, uchar
*packet
,
356 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
357 struct msgdma_extended_desc
*desc
= priv
->rx_desc
;
358 u32 rx_buf
= virt_to_phys(priv
->rx_buf
);
360 writel(0, &desc
->read_addr_lo
);
361 writel(0, &desc
->read_addr_hi
);
362 writel(rx_buf
, &desc
->write_addr_lo
);
363 writel(0, &desc
->write_addr_hi
);
364 writel(PKTSIZE_ALIGN
, &desc
->len
);
365 writel(0, &desc
->burst_seq_num
);
366 writel(MSGDMA_DESC_RX_STRIDE
, &desc
->stride
);
367 writel(MSGDMA_DESC_CTL_RX_SINGLE
, &desc
->control
);
368 debug("recv setup\n");
373 static void altera_tse_stop_msgdma(struct udevice
*dev
)
375 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
377 msgdma_reset(priv
->sgdma_rx
);
378 msgdma_reset(priv
->sgdma_tx
);
381 static int tse_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
383 struct altera_tse_priv
*priv
= bus
->priv
;
384 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
387 /* set mdio address */
388 writel(addr
, &mac_dev
->mdio_phy1_addr
);
390 value
= readl(&mac_dev
->mdio_phy1
[reg
]);
392 return value
& 0xffff;
395 static int tse_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
398 struct altera_tse_priv
*priv
= bus
->priv
;
399 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
401 /* set mdio address */
402 writel(addr
, &mac_dev
->mdio_phy1_addr
);
404 writel(val
, &mac_dev
->mdio_phy1
[reg
]);
409 static int tse_mdio_init(const char *name
, struct altera_tse_priv
*priv
)
411 struct mii_dev
*bus
= mdio_alloc();
414 printf("Failed to allocate MDIO bus\n");
418 bus
->read
= tse_mdio_read
;
419 bus
->write
= tse_mdio_write
;
420 snprintf(bus
->name
, sizeof(bus
->name
), "%s", name
);
422 bus
->priv
= (void *)priv
;
424 return mdio_register(bus
);
427 static int tse_phy_init(struct altera_tse_priv
*priv
, void *dev
)
429 struct phy_device
*phydev
;
430 unsigned int mask
= 0xffffffff;
433 mask
= 1 << priv
->phyaddr
;
435 phydev
= phy_find_by_mask(priv
->bus
, mask
, priv
->interface
);
439 phy_connect_dev(phydev
, dev
);
441 phydev
->supported
&= PHY_GBIT_FEATURES
;
442 phydev
->advertising
= phydev
->supported
;
444 priv
->phydev
= phydev
;
450 static int altera_tse_write_hwaddr(struct udevice
*dev
)
452 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
453 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
454 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
455 u8
*hwaddr
= pdata
->enetaddr
;
458 mac_lo
= (hwaddr
[3] << 24) | (hwaddr
[2] << 16) |
459 (hwaddr
[1] << 8) | hwaddr
[0];
460 mac_hi
= (hwaddr
[5] << 8) | hwaddr
[4];
461 debug("Set MAC address to 0x%04x%08x\n", mac_hi
, mac_lo
);
463 writel(mac_lo
, &mac_dev
->mac_addr_0
);
464 writel(mac_hi
, &mac_dev
->mac_addr_1
);
465 writel(mac_lo
, &mac_dev
->supp_mac_addr_0_0
);
466 writel(mac_hi
, &mac_dev
->supp_mac_addr_0_1
);
467 writel(mac_lo
, &mac_dev
->supp_mac_addr_1_0
);
468 writel(mac_hi
, &mac_dev
->supp_mac_addr_1_1
);
469 writel(mac_lo
, &mac_dev
->supp_mac_addr_2_0
);
470 writel(mac_hi
, &mac_dev
->supp_mac_addr_2_1
);
471 writel(mac_lo
, &mac_dev
->supp_mac_addr_3_0
);
472 writel(mac_hi
, &mac_dev
->supp_mac_addr_3_1
);
477 static int altera_tse_send(struct udevice
*dev
, void *packet
, int length
)
479 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
480 unsigned long tx_buf
= (unsigned long)packet
;
482 flush_dcache_range(tx_buf
, tx_buf
+ length
);
484 return priv
->ops
->send(dev
, packet
, length
);
487 static int altera_tse_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
489 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
491 return priv
->ops
->recv(dev
, flags
, packetp
);
494 static int altera_tse_free_pkt(struct udevice
*dev
, uchar
*packet
,
497 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
498 unsigned long rx_buf
= (unsigned long)priv
->rx_buf
;
500 invalidate_dcache_range(rx_buf
, rx_buf
+ PKTSIZE_ALIGN
);
502 return priv
->ops
->free_pkt(dev
, packet
, length
);
505 static void altera_tse_stop(struct udevice
*dev
)
507 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
509 priv
->ops
->stop(dev
);
510 altera_tse_stop_mac(priv
);
513 static int altera_tse_start(struct udevice
*dev
)
515 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
516 struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
520 /* need to create sgdma */
521 debug("Configuring rx desc\n");
522 altera_tse_free_pkt(dev
, priv
->rx_buf
, PKTSIZE_ALIGN
);
524 debug("Configuring TSE Mac\n");
525 /* Initialize MAC registers */
526 writel(PKTSIZE_ALIGN
, &mac_dev
->max_frame_length
);
527 writel(priv
->rx_fifo_depth
- 16, &mac_dev
->rx_sel_empty_threshold
);
528 writel(0, &mac_dev
->rx_sel_full_threshold
);
529 writel(priv
->tx_fifo_depth
- 16, &mac_dev
->tx_sel_empty_threshold
);
530 writel(0, &mac_dev
->tx_sel_full_threshold
);
531 writel(8, &mac_dev
->rx_almost_empty_threshold
);
532 writel(8, &mac_dev
->rx_almost_full_threshold
);
533 writel(8, &mac_dev
->tx_almost_empty_threshold
);
534 writel(3, &mac_dev
->tx_almost_full_threshold
);
537 writel(0, &mac_dev
->rx_cmd_stat
);
538 writel(0, &mac_dev
->tx_cmd_stat
);
541 val
= ALTERA_TSE_CMD_TX_ENA_MSK
| ALTERA_TSE_CMD_RX_ENA_MSK
;
542 writel(val
, &mac_dev
->command_config
);
544 /* Start up the PHY */
545 ret
= phy_startup(priv
->phydev
);
547 debug("Could not initialize PHY %s\n",
548 priv
->phydev
->dev
->name
);
552 tse_adjust_link(priv
, priv
->phydev
);
554 if (!priv
->phydev
->link
)
560 static const struct tse_ops tse_sgdma_ops
= {
561 .send
= altera_tse_send_sgdma
,
562 .recv
= altera_tse_recv_sgdma
,
563 .free_pkt
= altera_tse_free_pkt_sgdma
,
564 .stop
= altera_tse_stop_sgdma
,
567 static const struct tse_ops tse_msgdma_ops
= {
568 .send
= altera_tse_send_msgdma
,
569 .recv
= altera_tse_recv_msgdma
,
570 .free_pkt
= altera_tse_free_pkt_msgdma
,
571 .stop
= altera_tse_stop_msgdma
,
574 static int altera_tse_probe(struct udevice
*dev
)
576 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
577 struct altera_tse_priv
*priv
= dev_get_priv(dev
);
578 void *blob
= (void *)gd
->fdt_blob
;
579 int node
= dev_of_offset(dev
);
580 const char *list
, *end
;
582 void *base
, *desc_mem
= NULL
;
583 unsigned long addr
, size
;
584 int parent
, addrc
, sizec
;
588 priv
->dma_type
= dev_get_driver_data(dev
);
589 if (priv
->dma_type
== ALT_SGDMA
)
590 priv
->ops
= &tse_sgdma_ops
;
592 priv
->ops
= &tse_msgdma_ops
;
594 * decode regs. there are multiple reg tuples, and they need to
595 * match with reg-names.
597 parent
= fdt_parent_offset(blob
, node
);
598 fdt_support_default_count_cells(blob
, parent
, &addrc
, &sizec
);
599 list
= fdt_getprop(blob
, node
, "reg-names", &len
);
603 cell
= fdt_getprop(blob
, node
, "reg", &len
);
608 addr
= fdt_translate_address((void *)blob
,
610 size
= fdt_addr_to_cpu(cell
[idx
+ addrc
]);
611 base
= map_physmem(addr
, size
, MAP_NOCACHE
);
613 if (strcmp(list
, "control_port") == 0)
614 priv
->mac_dev
= base
;
615 else if (strcmp(list
, "rx_csr") == 0)
616 priv
->sgdma_rx
= base
;
617 else if (strcmp(list
, "rx_desc") == 0)
618 priv
->rx_desc
= base
;
619 else if (strcmp(list
, "rx_resp") == 0)
620 priv
->rx_resp
= base
;
621 else if (strcmp(list
, "tx_csr") == 0)
622 priv
->sgdma_tx
= base
;
623 else if (strcmp(list
, "tx_desc") == 0)
624 priv
->tx_desc
= base
;
625 else if (strcmp(list
, "s1") == 0)
627 idx
+= addrc
+ sizec
;
630 /* decode fifo depth */
631 priv
->rx_fifo_depth
= fdtdec_get_int(blob
, node
,
633 priv
->tx_fifo_depth
= fdtdec_get_int(blob
, node
,
636 addr
= fdtdec_get_int(blob
, node
,
638 addr
= fdt_node_offset_by_phandle(blob
, addr
);
639 priv
->phyaddr
= fdtdec_get_int(blob
, addr
,
642 if (priv
->dma_type
== ALT_SGDMA
) {
643 len
= sizeof(struct alt_sgdma_descriptor
) * 4;
645 desc_mem
= dma_alloc_coherent(len
, &addr
);
649 memset(desc_mem
, 0, len
);
650 priv
->tx_desc
= desc_mem
;
651 priv
->rx_desc
= priv
->tx_desc
+
652 2 * sizeof(struct alt_sgdma_descriptor
);
654 /* allocate recv packet buffer */
655 priv
->rx_buf
= malloc_cache_aligned(PKTSIZE_ALIGN
);
659 /* stop controller */
660 debug("Reset TSE & SGDMAs\n");
661 altera_tse_stop(dev
);
664 priv
->interface
= pdata
->phy_interface
;
665 tse_mdio_init(dev
->name
, priv
);
666 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
668 ret
= tse_phy_init(priv
, dev
);
673 static int altera_tse_ofdata_to_platdata(struct udevice
*dev
)
675 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
676 const char *phy_mode
;
678 pdata
->phy_interface
= -1;
679 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
682 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
683 if (pdata
->phy_interface
== -1) {
684 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
691 static const struct eth_ops altera_tse_ops
= {
692 .start
= altera_tse_start
,
693 .send
= altera_tse_send
,
694 .recv
= altera_tse_recv
,
695 .free_pkt
= altera_tse_free_pkt
,
696 .stop
= altera_tse_stop
,
697 .write_hwaddr
= altera_tse_write_hwaddr
,
700 static const struct udevice_id altera_tse_ids
[] = {
701 { .compatible
= "altr,tse-msgdma-1.0", .data
= ALT_MSGDMA
},
702 { .compatible
= "altr,tse-1.0", .data
= ALT_SGDMA
},
706 U_BOOT_DRIVER(altera_tse
) = {
707 .name
= "altera_tse",
709 .of_match
= altera_tse_ids
,
710 .ops
= &altera_tse_ops
,
711 .ofdata_to_platdata
= altera_tse_ofdata_to_platdata
,
712 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
713 .priv_auto_alloc_size
= sizeof(struct altera_tse_priv
),
714 .probe
= altera_tse_probe
,