2 * Altera 10/100/1000 triple speed ethernet mac
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef _ALTERA_TSE_H_
12 #define _ALTERA_TSE_H_
14 #define __packed_1_ __packed __aligned(1)
21 #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
23 #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
24 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
25 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
28 * Descriptor control bit masks & offsets
30 * Note: The control byte physically occupies bits [31:24] in memory.
31 * The following bit-offsets are expressed relative to the LSB of
32 * the control register bitfield.
34 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
35 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
36 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
37 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
40 * Descriptor status bit masks & offsets
42 * Note: The status byte physically occupies bits [23:16] in memory.
43 * The following bit-offsets are expressed relative to the LSB of
44 * the status register bitfield.
46 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
49 * The SGDMA controller buffer descriptor allocates
50 * 64 bits for each address. To support ANSI C, the
51 * struct implementing a descriptor places 32-bits
52 * of padding directly above each address; each pad must
53 * be cleared when initializing a descriptor.
57 * Buffer Descriptor data structure
60 struct alt_sgdma_descriptor
{
61 u32 source
; /* the address of data to be read. */
64 u32 destination
; /* the address to write data */
67 u32 next
; /* the next descriptor in the list. */
70 u16 bytes_to_transfer
; /* the number of bytes to transfer */
74 u16 actual_bytes_transferred
;/* bytes transferred by DMA */
76 u8 descriptor_control
;
80 /* SG-DMA Control/Status Slave registers map */
82 struct alt_sgdma_registers
{
87 u32 next_descriptor_pointer
;
88 u32 descriptor_pad
[3];
93 /* mSGDMA extended descriptor format */
94 struct msgdma_extended_desc
{
95 u32 read_addr_lo
; /* data buffer source address low bits */
96 u32 write_addr_lo
; /* data buffer destination address low bits */
100 u32 read_addr_hi
; /* data buffer source address high bits */
101 u32 write_addr_hi
; /* data buffer destination address high bits */
102 u32 control
; /* characteristics of the transfer */
105 /* mSGDMA descriptor control field bit definitions */
106 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
107 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
108 #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
109 #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
110 #define MSGDMA_DESC_CTL_GO BIT(31)
112 /* Tx buffer control flags */
113 #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
114 MSGDMA_DESC_CTL_GEN_EOP | \
117 #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
118 MSGDMA_DESC_CTL_END_ON_LEN | \
121 /* mSGDMA extended descriptor stride definitions */
122 #define MSGDMA_DESC_TX_STRIDE 0x00010001
123 #define MSGDMA_DESC_RX_STRIDE 0x00010001
125 /* mSGDMA dispatcher control and status register map */
127 u32 status
; /* Read/Clear */
128 u32 control
; /* Read/Write */
130 u32 resp_fill_level
; /* bit 15:0 */
132 u32 pad
[3]; /* reserved */
135 /* mSGDMA CSR status register bit definitions */
136 #define MSGDMA_CSR_STAT_BUSY BIT(0)
137 #define MSGDMA_CSR_STAT_RESETTING BIT(6)
138 #define MSGDMA_CSR_STAT_MASK 0x3FF
140 /* mSGDMA CSR control register bit definitions */
141 #define MSGDMA_CSR_CTL_RESET BIT(1)
143 /* mSGDMA response register map */
144 struct msgdma_response
{
145 u32 bytes_transferred
;
150 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
151 #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
152 #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
153 #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
154 #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
155 #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
157 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
158 #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
160 /* MAC register Space */
163 u32 megacore_revision
;
168 u32 max_frame_length
;
170 u32 rx_sel_empty_threshold
;
171 u32 rx_sel_full_threshold
;
172 u32 tx_sel_empty_threshold
;
173 u32 tx_sel_full_threshold
;
174 u32 rx_almost_empty_threshold
;
175 u32 rx_almost_full_threshold
;
176 u32 tx_almost_empty_threshold
;
177 u32 tx_almost_full_threshold
;
183 /*FIFO control register. */
189 /*Registers 0 to 31 within PHY device 0/1 */
193 /*4 Supplemental MAC Addresses */
194 u32 supp_mac_addr_0_0
;
195 u32 supp_mac_addr_0_1
;
196 u32 supp_mac_addr_1_0
;
197 u32 supp_mac_addr_1_1
;
198 u32 supp_mac_addr_2_0
;
199 u32 supp_mac_addr_2_1
;
200 u32 supp_mac_addr_3_0
;
201 u32 supp_mac_addr_3_1
;
207 int (*send
)(struct udevice
*dev
, void *packet
, int length
);
208 int (*recv
)(struct udevice
*dev
, int flags
, uchar
**packetp
);
209 int (*free_pkt
)(struct udevice
*dev
, uchar
*packet
, int length
);
210 void (*stop
)(struct udevice
*dev
);
213 struct altera_tse_priv
{
214 struct alt_tse_mac
*mac_dev
;
217 unsigned int rx_fifo_depth
;
218 unsigned int tx_fifo_depth
;
222 unsigned char *rx_buf
;
223 unsigned int phyaddr
;
224 unsigned int interface
;
225 struct phy_device
*phydev
;
227 const struct tse_ops
*ops
;
231 #endif /* _ALTERA_TSE_H_ */