drivers/net/armada100_fec.h

   1 /*
   2  * (C) Copyright 2011
   3  * eInfochips Ltd. <www.einfochips.com>
   4  * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
   5  *
   6  * (C) Copyright 2010
   7  * Marvell Semiconductor <www.marvell.com>
   8  * Contributor: Mahavir Jain <mjain@marvell.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  26  * MA 02110-1301 USA
  27  */
  28
  29 #ifndef __ARMADA100_FEC_H__
  30 #define __ARMADA100_FEC_H__
  31
  32 #define PORT_NUM                0x0
  33
  34 /* RX & TX descriptor command */
  35 #define BUF_OWNED_BY_DMA        (1<<31)
  36
  37 /* RX descriptor status */
  38 #define RX_EN_INT               (1<<23)
  39 #define RX_FIRST_DESC           (1<<17)
  40 #define RX_LAST_DESC            (1<<16)
  41 #define RX_ERROR                (1<<15)
  42
  43 /* TX descriptor command */
  44 #define TX_EN_INT               (1<<23)
  45 #define TX_GEN_CRC              (1<<22)
  46 #define TX_ZERO_PADDING         (1<<18)
  47 #define TX_FIRST_DESC           (1<<17)
  48 #define TX_LAST_DESC            (1<<16)
  49 #define TX_ERROR                (1<<15)
  50
  51 /* smi register */
  52 #define SMI_BUSY                (1<<28) /* 0 - Write, 1 - Read  */
  53 #define SMI_R_VALID             (1<<27) /* 0 - Write, 1 - Read  */
  54 #define SMI_OP_W                (0<<26) /* Write operation      */
  55 #define SMI_OP_R                (1<<26) /* Read operation */
  56
  57 #define HASH_ADD                0
  58 #define HASH_DELETE             1
  59 #define HASH_ADDR_TABLE_SIZE    0x4000  /* 16K (1/2K address - PCR_HS == 1) */
  60 #define HOP_NUMBER              12
  61
  62 #define PHY_WAIT_ITERATIONS     1000    /* 1000 iterations * 10uS = 10mS max */
  63 #define PHY_WAIT_MICRO_SECONDS  10
  64
  65 #define ETH_HW_IP_ALIGN         2       /* hw aligns IP header */
  66 #define ETH_EXTRA_HEADER        (6+6+2+4)
  67                                         /* dest+src addr+protocol id+crc */
  68 #define MAX_PKT_SIZE            1536
  69
  70
  71 /* Bit definitions of the SDMA Config Reg */
  72 #define SDCR_BSZ_OFF            12
  73 #define SDCR_BSZ8               (3<<SDCR_BSZ_OFF)
  74 #define SDCR_BSZ4               (2<<SDCR_BSZ_OFF)
  75 #define SDCR_BSZ2               (1<<SDCR_BSZ_OFF)
  76 #define SDCR_BSZ1               (0<<SDCR_BSZ_OFF)
  77 #define SDCR_BLMR               (1<<6)
  78 #define SDCR_BLMT               (1<<7)
  79 #define SDCR_RIFB               (1<<9)
  80 #define SDCR_RC_OFF             2
  81 #define SDCR_RC_MAX_RETRANS     (0xf << SDCR_RC_OFF)
  82
  83 /* SDMA_CMD */
  84 #define SDMA_CMD_AT             (1<<31)
  85 #define SDMA_CMD_TXDL           (1<<24)
  86 #define SDMA_CMD_TXDH           (1<<23)
  87 #define SDMA_CMD_AR             (1<<15)
  88 #define SDMA_CMD_ERD            (1<<7)
  89
  90
  91 /* Bit definitions of the Port Config Reg */
  92 #define PCR_HS                  (1<<12)
  93 #define PCR_EN                  (1<<7)
  94 #define PCR_PM                  (1<<0)
  95
  96 /* Bit definitions of the Port Config Extend Reg */
  97 #define PCXR_2BSM               (1<<28)
  98 #define PCXR_DSCP_EN            (1<<21)
  99 #define PCXR_MFL_1518           (0<<14)
 100 #define PCXR_MFL_1536           (1<<14)
 101 #define PCXR_MFL_2048           (2<<14)
 102 #define PCXR_MFL_64K            (3<<14)
 103 #define PCXR_FLP                (1<<11)
 104 #define PCXR_PRIO_TX_OFF        3
 105 #define PCXR_TX_HIGH_PRI        (7<<PCXR_PRIO_TX_OFF)
 106
 107 /*
 108  *  * Bit definitions of the Interrupt Cause Reg
 109  *   * and Interrupt MASK Reg is the same
 110  *    */
 111 #define ICR_RXBUF               (1<<0)
 112 #define ICR_TXBUF_H             (1<<2)
 113 #define ICR_TXBUF_L             (1<<3)
 114 #define ICR_TXEND_H             (1<<6)
 115 #define ICR_TXEND_L             (1<<7)
 116 #define ICR_RXERR               (1<<8)
 117 #define ICR_TXERR_H             (1<<10)
 118 #define ICR_TXERR_L             (1<<11)
 119 #define ICR_TX_UDR              (1<<13)
 120 #define ICR_MII_CH              (1<<28)
 121
 122 #define ALL_INTS (ICR_TXBUF_H  | ICR_TXBUF_L  | ICR_TX_UDR |\
 123                                 ICR_TXERR_H  | ICR_TXERR_L |\
 124                                 ICR_TXEND_H  | ICR_TXEND_L |\
 125                                 ICR_RXBUF | ICR_RXERR  | ICR_MII_CH)
 126
 127 #define PHY_MASK               0x0000001f
 128
 129 #define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
 130 /* Size of a Tx/Rx descriptor used in chain list data structure */
 131 #define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
 132         (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
 133
 134 #define RX_BUF_OFFSET           0x2
 135 #define RXQ                     0x0     /* RX Queue 0 */
 136 #define TXQ                     0x1     /* TX Queue 1 */
 137
 138 struct addr_table_entry_t {
 139         u32 lo;
 140         u32 hi;
 141 };
 142
 143 /* Bit fields of a Hash Table Entry */
 144 enum hash_table_entry {
 145         HTEVALID = 1,
 146         HTESKIP = 2,
 147         HTERD = 4,
 148         HTERDBIT = 2
 149 };
 150
 151 struct tx_desc {
 152         u32 cmd_sts;            /* Command/status field */
 153         u16 reserved;
 154         u16 byte_cnt;           /* buffer byte count */
 155         u8 *buf_ptr;            /* pointer to buffer for this descriptor */
 156         struct tx_desc *nextdesc_p;     /* Pointer to next descriptor */
 157 };
 158
 159 struct rx_desc {
 160         u32 cmd_sts;            /* Descriptor command status */
 161         u16 byte_cnt;           /* Descriptor buffer byte count */
 162         u16 buf_size;           /* Buffer size */
 163         u8 *buf_ptr;            /* Descriptor buffer pointer */
 164         struct rx_desc *nxtdesc_p;      /* Next descriptor pointer */
 165 };
 166
 167 /*
 168  * Armada100 Fast Ethernet controller Registers
 169  * Refer Datasheet Appendix A.22
 170  */
 171 struct armdfec_reg {
 172         u32 phyadr;                     /* PHY Address */
 173         u32 pad1[3];
 174         u32 smi;                        /* SMI */
 175         u32 pad2[0xFB];
 176         u32 pconf;                      /* Port configuration */
 177         u32 pad3;
 178         u32 pconf_ext;                  /* Port configuration extend */
 179         u32 pad4;
 180         u32 pcmd;                       /* Port Command */
 181         u32 pad5;
 182         u32 pstatus;                    /* Port Status */
 183         u32 pad6;
 184         u32 spar;                       /* Serial Parameters */
 185         u32 pad7;
 186         u32 htpr;                       /* Hash table pointer */
 187         u32 pad8;
 188         u32 fcsal;                      /* Flow control source address low */
 189         u32 pad9;
 190         u32 fcsah;                      /* Flow control source address high */
 191         u32 pad10;
 192         u32 sdma_conf;                  /* SDMA configuration */
 193         u32 pad11;
 194         u32 sdma_cmd;                   /* SDMA command */
 195         u32 pad12;
 196         u32 ic;                         /* Interrupt cause */
 197         u32 iwc;                        /* Interrupt write to clear */
 198         u32 im;                         /* Interrupt mask */
 199         u32 pad13;
 200         u32 *eth_idscpp[4];             /* Eth0 IP Differentiated Services Code
 201                                            Point to Priority 0 Low */
 202         u32 eth_vlan_p;                 /* Eth0 VLAN Priority Tag to Priority */
 203         u32 pad14[3];
 204         struct rx_desc *rxfdp[4];       /* Ethernet First Rx Descriptor
 205                                            Pointer */
 206         u32 pad15[4];
 207         struct rx_desc *rxcdp[4];       /* Ethernet Current Rx Descriptor
 208                                            Pointer */
 209         u32 pad16[0x0C];
 210         struct tx_desc *txcdp[2];       /* Ethernet Current Tx Descriptor
 211                                            Pointer */
 212 };
 213
 214 struct armdfec_device {
 215         struct eth_device dev;
 216         struct armdfec_reg *regs;
 217         struct tx_desc *p_txdesc;
 218         struct rx_desc *p_rxdesc;
 219         struct rx_desc *p_rxdesc_curr;
 220         u8 *p_rxbuf;
 221         u8 *p_aligned_txbuf;
 222         u8 *htpr;               /* hash pointer */
 223 };
 224
 225 #endif /* __ARMADA100_FEC_H__ */