drivers/net/cs8900.h

   1 #ifndef CS8900_H
   2 #define CS8900_H
   3 /*
   4  * Cirrus Logic CS8900A Ethernet
   5  *
   6  * (C) 2009 Ben Warren , biggerbadderben@gmail.com
   7  *     Converted to use CONFIG_NET_MULTI API
   8  *
   9  * (C) Copyright 2002
  10  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11  * Marius Groeger <mgroeger@sysgo.de>
  12  *
  13  * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
  14  *
  15  * This program is loaded into SRAM in bootstrap mode, where it waits
  16  * for commands on UART1 to read and write memory, jump to code etc.
  17  * A design goal for this program is to be entirely independent of the
  18  * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
  19  * this code in bootstrap mode.  All the board specifics can be handled on
  20  * the host.
  21  *
  22  * SPDX-License-Identifier:     GPL-2.0+
  23  */
  24
  25 #include <asm/types.h>
  26 #include <config.h>
  27
  28 #define CS8900_DRIVERNAME "CS8900"
  29 /* although the registers are 16 bit, they are 32-bit aligned on the
  30    EDB7111. so we have to read them as 32-bit registers and ignore the
  31    upper 16-bits. i'm not sure if this holds for the EDB7211. */
  32
  33 #ifdef CONFIG_CS8900_BUS16
  34   /* 16 bit aligned registers, 16 bit wide */
  35   #define CS8900_REG u16
  36 #elif defined(CONFIG_CS8900_BUS32)
  37   /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
  38   #define CS8900_REG u32
  39 #else
  40   #error unknown bussize ...
  41 #endif
  42
  43 struct cs8900_regs {
  44         CS8900_REG rtdata;
  45         CS8900_REG pad0;
  46         CS8900_REG txcmd;
  47         CS8900_REG txlen;
  48         CS8900_REG isq;
  49         CS8900_REG pptr;
  50         CS8900_REG pdata;
  51 };
  52
  53 struct cs8900_priv {
  54         struct cs8900_regs *regs;
  55 };
  56
  57 #define ISQ_RxEvent     0x04
  58 #define ISQ_TxEvent     0x08
  59 #define ISQ_BufEvent    0x0C
  60 #define ISQ_RxMissEvent 0x10
  61 #define ISQ_TxColEvent  0x12
  62 #define ISQ_EventMask   0x3F
  63
  64 /* packet page register offsets */
  65
  66 /* bus interface registers */
  67 #define PP_ChipID    0x0000  /* Chip identifier - must be 0x630E */
  68 #define PP_ChipRev   0x0002  /* Chip revision, model codes */
  69
  70 #define PP_IntReg    0x0022  /* Interrupt configuration */
  71 #define PP_IntReg_IRQ0         0x0000  /* Use INTR0 pin */
  72 #define PP_IntReg_IRQ1         0x0001  /* Use INTR1 pin */
  73 #define PP_IntReg_IRQ2         0x0002  /* Use INTR2 pin */
  74 #define PP_IntReg_IRQ3         0x0003  /* Use INTR3 pin */
  75
  76 /* status and control registers */
  77
  78 #define PP_RxCFG     0x0102  /* Receiver configuration */
  79 #define PP_RxCFG_Skip1         0x0040  /* Skip (i.e. discard) current frame */
  80 #define PP_RxCFG_Stream        0x0080  /* Enable streaming mode */
  81 #define PP_RxCFG_RxOK          0x0100  /* RxOK interrupt enable */
  82 #define PP_RxCFG_RxDMAonly     0x0200  /* Use RxDMA for all frames */
  83 #define PP_RxCFG_AutoRxDMA     0x0400  /* Select RxDMA automatically */
  84 #define PP_RxCFG_BufferCRC     0x0800  /* Include CRC characters in frame */
  85 #define PP_RxCFG_CRC           0x1000  /* Enable interrupt on CRC error */
  86 #define PP_RxCFG_RUNT          0x2000  /* Enable interrupt on RUNT frames */
  87 #define PP_RxCFG_EXTRA         0x4000  /* Enable interrupt on frames with extra data */
  88
  89 #define PP_RxCTL     0x0104  /* Receiver control */
  90 #define PP_RxCTL_IAHash        0x0040  /* Accept frames that match hash */
  91 #define PP_RxCTL_Promiscuous   0x0080  /* Accept any frame */
  92 #define PP_RxCTL_RxOK          0x0100  /* Accept well formed frames */
  93 #define PP_RxCTL_Multicast     0x0200  /* Accept multicast frames */
  94 #define PP_RxCTL_IA            0x0400  /* Accept frame that matches IA */
  95 #define PP_RxCTL_Broadcast     0x0800  /* Accept broadcast frames */
  96 #define PP_RxCTL_CRC           0x1000  /* Accept frames with bad CRC */
  97 #define PP_RxCTL_RUNT          0x2000  /* Accept runt frames */
  98 #define PP_RxCTL_EXTRA         0x4000  /* Accept frames that are too long */
  99
 100 #define PP_TxCFG     0x0106  /* Transmit configuration */
 101 #define PP_TxCFG_CRS           0x0040  /* Enable interrupt on loss of carrier */
 102 #define PP_TxCFG_SQE           0x0080  /* Enable interrupt on Signal Quality Error */
 103 #define PP_TxCFG_TxOK          0x0100  /* Enable interrupt on successful xmits */
 104 #define PP_TxCFG_Late          0x0200  /* Enable interrupt on "out of window" */
 105 #define PP_TxCFG_Jabber        0x0400  /* Enable interrupt on jabber detect */
 106 #define PP_TxCFG_Collision     0x0800  /* Enable interrupt if collision */
 107 #define PP_TxCFG_16Collisions  0x8000  /* Enable interrupt if > 16 collisions */
 108
 109 #define PP_TxCmd     0x0108  /* Transmit command status */
 110 #define PP_TxCmd_TxStart_5     0x0000  /* Start after 5 bytes in buffer */
 111 #define PP_TxCmd_TxStart_381   0x0040  /* Start after 381 bytes in buffer */
 112 #define PP_TxCmd_TxStart_1021  0x0080  /* Start after 1021 bytes in buffer */
 113 #define PP_TxCmd_TxStart_Full  0x00C0  /* Start after all bytes loaded */
 114 #define PP_TxCmd_Force         0x0100  /* Discard any pending packets */
 115 #define PP_TxCmd_OneCollision  0x0200  /* Abort after a single collision */
 116 #define PP_TxCmd_NoCRC         0x1000  /* Do not add CRC */
 117 #define PP_TxCmd_NoPad         0x2000  /* Do not pad short packets */
 118
 119 #define PP_BufCFG    0x010A  /* Buffer configuration */
 120 #define PP_BufCFG_SWI          0x0040  /* Force interrupt via software */
 121 #define PP_BufCFG_RxDMA        0x0080  /* Enable interrupt on Rx DMA */
 122 #define PP_BufCFG_TxRDY        0x0100  /* Enable interrupt when ready for Tx */
 123 #define PP_BufCFG_TxUE         0x0200  /* Enable interrupt in Tx underrun */
 124 #define PP_BufCFG_RxMiss       0x0400  /* Enable interrupt on missed Rx packets */
 125 #define PP_BufCFG_Rx128        0x0800  /* Enable Rx interrupt after 128 bytes */
 126 #define PP_BufCFG_TxCol        0x1000  /* Enable int on Tx collision ctr overflow */
 127 #define PP_BufCFG_Miss         0x2000  /* Enable int on Rx miss ctr overflow */
 128 #define PP_BufCFG_RxDest       0x8000  /* Enable int on Rx dest addr match */
 129
 130 #define PP_LineCTL   0x0112  /* Line control */
 131 #define PP_LineCTL_Rx          0x0040  /* Enable receiver */
 132 #define PP_LineCTL_Tx          0x0080  /* Enable transmitter */
 133 #define PP_LineCTL_AUIonly     0x0100  /* AUI interface only */
 134 #define PP_LineCTL_AutoAUI10BT 0x0200  /* Autodetect AUI or 10BaseT interface */
 135 #define PP_LineCTL_ModBackoffE 0x0800  /* Enable modified backoff algorithm */
 136 #define PP_LineCTL_PolarityDis 0x1000  /* Disable Rx polarity autodetect */
 137 #define PP_LineCTL_2partDefDis 0x2000  /* Disable two-part defferal */
 138 #define PP_LineCTL_LoRxSquelch 0x4000  /* Reduce receiver squelch threshold */
 139
 140 #define PP_SelfCTL   0x0114  /* Chip self control */
 141 #define PP_SelfCTL_Reset       0x0040  /* Self-clearing reset */
 142 #define PP_SelfCTL_SWSuspend   0x0100  /* Initiate suspend mode */
 143 #define PP_SelfCTL_HWSleepE    0x0200  /* Enable SLEEP input */
 144 #define PP_SelfCTL_HWStandbyE  0x0400  /* Enable standby mode */
 145 #define PP_SelfCTL_HC0E        0x1000  /* use HCB0 for LINK LED */
 146 #define PP_SelfCTL_HC1E        0x2000  /* use HCB1 for BSTATUS LED */
 147 #define PP_SelfCTL_HCB0        0x4000  /* control LINK LED if HC0E set */
 148 #define PP_SelfCTL_HCB1        0x8000  /* control BSTATUS LED if HC1E set */
 149
 150 #define PP_BusCTL    0x0116  /* Bus control */
 151 #define PP_BusCTL_ResetRxDMA   0x0040  /* Reset RxDMA pointer */
 152 #define PP_BusCTL_DMAextend    0x0100  /* Extend DMA cycle */
 153 #define PP_BusCTL_UseSA        0x0200  /* Assert MEMCS16 on address decode */
 154 #define PP_BusCTL_MemoryE      0x0400  /* Enable memory mode */
 155 #define PP_BusCTL_DMAburst     0x0800  /* Limit DMA access burst */
 156 #define PP_BusCTL_IOCHRDYE     0x1000  /* Set IOCHRDY high impedence */
 157 #define PP_BusCTL_RxDMAsize    0x2000  /* Set DMA buffer size 64KB */
 158 #define PP_BusCTL_EnableIRQ    0x8000  /* Generate interrupt on interrupt event */
 159
 160 #define PP_TestCTL   0x0118  /* Test control */
 161 #define PP_TestCTL_DisableLT   0x0080  /* Disable link status */
 162 #define PP_TestCTL_ENDECloop   0x0200  /* Internal loopback */
 163 #define PP_TestCTL_AUIloop     0x0400  /* AUI loopback */
 164 #define PP_TestCTL_DisBackoff  0x0800  /* Disable backoff algorithm */
 165 #define PP_TestCTL_FDX         0x4000  /* Enable full duplex mode */
 166
 167 #define PP_ISQ       0x0120  /* Interrupt Status Queue */
 168
 169 #define PP_RER       0x0124  /* Receive event */
 170 #define PP_RER_IAHash          0x0040  /* Frame hash match */
 171 #define PP_RER_Dribble         0x0080  /* Frame had 1-7 extra bits after last byte */
 172 #define PP_RER_RxOK            0x0100  /* Frame received with no errors */
 173 #define PP_RER_Hashed          0x0200  /* Frame address hashed OK */
 174 #define PP_RER_IA              0x0400  /* Frame address matched IA */
 175 #define PP_RER_Broadcast       0x0800  /* Broadcast frame */
 176 #define PP_RER_CRC             0x1000  /* Frame had CRC error */
 177 #define PP_RER_RUNT            0x2000  /* Runt frame */
 178 #define PP_RER_EXTRA           0x4000  /* Frame was too long */
 179
 180 #define PP_TER       0x0128 /* Transmit event */
 181 #define PP_TER_CRS             0x0040  /* Carrier lost */
 182 #define PP_TER_SQE             0x0080  /* Signal Quality Error */
 183 #define PP_TER_TxOK            0x0100  /* Packet sent without error */
 184 #define PP_TER_Late            0x0200  /* Out of window */
 185 #define PP_TER_Jabber          0x0400  /* Stuck transmit? */
 186 #define PP_TER_NumCollisions   0x7800  /* Number of collisions */
 187 #define PP_TER_16Collisions    0x8000  /* > 16 collisions */
 188
 189 #define PP_BER       0x012C /* Buffer event */
 190 #define PP_BER_SWint           0x0040 /* Software interrupt */
 191 #define PP_BER_RxDMAFrame      0x0080 /* Received framed DMAed */
 192 #define PP_BER_Rdy4Tx          0x0100 /* Ready for transmission */
 193 #define PP_BER_TxUnderrun      0x0200 /* Transmit underrun */
 194 #define PP_BER_RxMiss          0x0400 /* Received frame missed */
 195 #define PP_BER_Rx128           0x0800 /* 128 bytes received */
 196 #define PP_BER_RxDest          0x8000 /* Received framed passed address filter */
 197
 198 #define PP_RxMiss    0x0130  /*  Receiver miss counter */
 199
 200 #define PP_TxCol     0x0132  /*  Transmit collision counter */
 201
 202 #define PP_LineSTAT  0x0134  /* Line status */
 203 #define PP_LineSTAT_LinkOK     0x0080  /* Line is connected and working */
 204 #define PP_LineSTAT_AUI        0x0100  /* Connected via AUI */
 205 #define PP_LineSTAT_10BT       0x0200  /* Connected via twisted pair */
 206 #define PP_LineSTAT_Polarity   0x1000  /* Line polarity OK (10BT only) */
 207 #define PP_LineSTAT_CRS        0x4000  /* Frame being received */
 208
 209 #define PP_SelfSTAT  0x0136  /* Chip self status */
 210 #define PP_SelfSTAT_33VActive  0x0040  /* supply voltage is 3.3V */
 211 #define PP_SelfSTAT_InitD      0x0080  /* Chip initialization complete */
 212 #define PP_SelfSTAT_SIBSY      0x0100  /* EEPROM is busy */
 213 #define PP_SelfSTAT_EEPROM     0x0200  /* EEPROM present */
 214 #define PP_SelfSTAT_EEPROM_OK  0x0400  /* EEPROM checks out */
 215 #define PP_SelfSTAT_ELPresent  0x0800  /* External address latch logic available */
 216 #define PP_SelfSTAT_EEsize     0x1000  /* Size of EEPROM */
 217
 218 #define PP_BusSTAT   0x0138  /* Bus status */
 219 #define PP_BusSTAT_TxBid       0x0080  /* Tx error */
 220 #define PP_BusSTAT_TxRDY       0x0100  /* Ready for Tx data */
 221
 222 #define PP_TDR       0x013C  /* AUI Time Domain Reflectometer */
 223
 224 /* initiate transmit registers */
 225
 226 #define PP_TxCommand 0x0144  /* Tx Command */
 227 #define PP_TxLength  0x0146  /* Tx Length */
 228
 229
 230 /* address filter registers */
 231
 232 #define PP_LAF       0x0150  /* Logical address filter (6 bytes) */
 233 #define PP_IA        0x0158  /* Individual address (MAC) */
 234
 235 /* EEPROM Kram */
 236 #define SI_BUSY 0x0100
 237 #define PP_EECMD 0x0040         /*  NVR Interface Command register */
 238 #define PP_EEData 0x0042        /*  NVR Interface Data Register */
 239 #define EEPROM_WRITE_EN         0x00F0
 240 #define EEPROM_WRITE_DIS        0x0000
 241 #define EEPROM_WRITE_CMD        0x0100
 242 #define EEPROM_READ_CMD         0x0200
 243 #define EEPROM_ERASE_CMD        0x0300
 244
 245 /* Exported functions */
 246 int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
 247 int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
 248
 249 #endif  /* CS8900_H */