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Merge branch 'master' of git://git.denx.de/u-boot-nds32
[people/ms/u-boot.git] / drivers / net / dc2114x.c
1 /*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5 #include <common.h>
6 #include <malloc.h>
7 #include <net.h>
8 #include <netdev.h>
9 #include <pci.h>
10
11 #undef DEBUG_SROM
12 #undef DEBUG_SROM2
13
14 #undef UPDATE_SROM
15
16 /* PCI Registers.
17 */
18 #define PCI_CFDA_PSM 0x43
19
20 #define CFRV_RN 0x000000f0 /* Revision Number */
21
22 #define WAKEUP 0x00 /* Power Saving Wakeup */
23 #define SLEEP 0x80 /* Power Saving Sleep Mode */
24
25 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
26
27 /* Ethernet chip registers.
28 */
29 #define DE4X5_BMR 0x000 /* Bus Mode Register */
30 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
31 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
32 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
33 #define DE4X5_STS 0x028 /* Status Register */
34 #define DE4X5_OMR 0x030 /* Operation Mode Register */
35 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
36 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
37
38 /* Register bits.
39 */
40 #define BMR_SWR 0x00000001 /* Software Reset */
41 #define STS_TS 0x00700000 /* Transmit Process State */
42 #define STS_RS 0x000e0000 /* Receive Process State */
43 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
44 #define OMR_SR 0x00000002 /* Start/Stop Receive */
45 #define OMR_PS 0x00040000 /* Port Select */
46 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
47 #define OMR_PM 0x00000080 /* Pass All Multicast */
48
49 /* Descriptor bits.
50 */
51 #define R_OWN 0x80000000 /* Own Bit */
52 #define RD_RER 0x02000000 /* Receive End Of Ring */
53 #define RD_LS 0x00000100 /* Last Descriptor */
54 #define RD_ES 0x00008000 /* Error Summary */
55 #define TD_TER 0x02000000 /* Transmit End Of Ring */
56 #define T_OWN 0x80000000 /* Own Bit */
57 #define TD_LS 0x40000000 /* Last Segment */
58 #define TD_FS 0x20000000 /* First Segment */
59 #define TD_ES 0x00008000 /* Error Summary */
60 #define TD_SET 0x08000000 /* Setup Packet */
61
62 /* The EEPROM commands include the alway-set leading bit. */
63 #define SROM_WRITE_CMD 5
64 #define SROM_READ_CMD 6
65 #define SROM_ERASE_CMD 7
66
67 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
68 #define SROM_RD 0x00004000 /* Read from Boot ROM */
69 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
70 #define EE_WRITE_0 0x4801
71 #define EE_WRITE_1 0x4805
72 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
73 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
74
75 #define DT_IN 0x00000004 /* Serial Data In */
76 #define DT_CLK 0x00000002 /* Serial ROM Clock */
77 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
78
79 #define POLL_DEMAND 1
80
81 #ifdef CONFIG_TULIP_FIX_DAVICOM
82 #define RESET_DM9102(dev) {\
83 unsigned long i;\
84 i=INL(dev, 0x0);\
85 udelay(1000);\
86 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
87 udelay(1000);\
88 }
89 #else
90 #define RESET_DE4X5(dev) {\
91 int i;\
92 i=INL(dev, DE4X5_BMR);\
93 udelay(1000);\
94 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
95 udelay(1000);\
96 OUTL(dev, i, DE4X5_BMR);\
97 udelay(1000);\
98 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
99 udelay(1000);\
100 }
101 #endif
102
103 #define START_DE4X5(dev) {\
104 s32 omr; \
105 omr = INL(dev, DE4X5_OMR);\
106 omr |= OMR_ST | OMR_SR;\
107 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
108 }
109
110 #define STOP_DE4X5(dev) {\
111 s32 omr; \
112 omr = INL(dev, DE4X5_OMR);\
113 omr &= ~(OMR_ST|OMR_SR);\
114 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
115 }
116
117 #define NUM_RX_DESC PKTBUFSRX
118 #ifndef CONFIG_TULIP_FIX_DAVICOM
119 #define NUM_TX_DESC 1 /* Number of TX descriptors */
120 #else
121 #define NUM_TX_DESC 4
122 #endif
123 #define RX_BUFF_SZ PKTSIZE_ALIGN
124
125 #define TOUT_LOOP 1000000
126
127 #define SETUP_FRAME_LEN 192
128 #define ETH_ALEN 6
129
130 struct de4x5_desc {
131 volatile s32 status;
132 u32 des1;
133 u32 buf;
134 u32 next;
135 };
136
137 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
138 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
139 static int rx_new; /* RX descriptor ring pointer */
140 static int tx_new; /* TX descriptor ring pointer */
141
142 static char rxRingSize;
143 static char txRingSize;
144
145 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
146 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
147 static int getfrom_srom(struct eth_device* dev, u_long addr);
148 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
149 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
150 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
151 #ifdef UPDATE_SROM
152 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
153 static void update_srom(struct eth_device *dev, bd_t *bis);
154 #endif
155 #ifndef CONFIG_TULIP_FIX_DAVICOM
156 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
157 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
158 #endif /* CONFIG_TULIP_FIX_DAVICOM */
159 static void send_setup_frame(struct eth_device* dev, bd_t * bis);
160
161 static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
162 static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
163 static int dc21x4x_recv(struct eth_device* dev);
164 static void dc21x4x_halt(struct eth_device* dev);
165 #ifdef CONFIG_TULIP_SELECT_MEDIA
166 extern void dc21x4x_select_media(struct eth_device* dev);
167 #endif
168
169 #if defined(CONFIG_E500)
170 #define phys_to_bus(a) (a)
171 #else
172 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
173 #endif
174
175 static int INL(struct eth_device* dev, u_long addr)
176 {
177 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
178 }
179
180 static void OUTL(struct eth_device* dev, int command, u_long addr)
181 {
182 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
183 }
184
185 static struct pci_device_id supported[] = {
186 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
187 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
188 #ifdef CONFIG_TULIP_FIX_DAVICOM
189 { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
190 #endif
191 { }
192 };
193
194 int dc21x4x_initialize(bd_t *bis)
195 {
196 int idx=0;
197 int card_number = 0;
198 unsigned int cfrv;
199 unsigned char timer;
200 pci_dev_t devbusfn;
201 unsigned int iobase;
202 unsigned short status;
203 struct eth_device* dev;
204
205 while(1) {
206 devbusfn = pci_find_devices(supported, idx++);
207 if (devbusfn == -1) {
208 break;
209 }
210
211 /* Get the chip configuration revision register. */
212 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
213
214 #ifndef CONFIG_TULIP_FIX_DAVICOM
215 if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
216 printf("Error: The chip is not DC21143.\n");
217 continue;
218 }
219 #endif
220
221 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
222 status |=
223 #ifdef CONFIG_TULIP_USE_IO
224 PCI_COMMAND_IO |
225 #else
226 PCI_COMMAND_MEMORY |
227 #endif
228 PCI_COMMAND_MASTER;
229 pci_write_config_word(devbusfn, PCI_COMMAND, status);
230
231 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
232 #ifdef CONFIG_TULIP_USE_IO
233 if (!(status & PCI_COMMAND_IO)) {
234 printf("Error: Can not enable I/O access.\n");
235 continue;
236 }
237 #else
238 if (!(status & PCI_COMMAND_MEMORY)) {
239 printf("Error: Can not enable MEMORY access.\n");
240 continue;
241 }
242 #endif
243
244 if (!(status & PCI_COMMAND_MASTER)) {
245 printf("Error: Can not enable Bus Mastering.\n");
246 continue;
247 }
248
249 /* Check the latency timer for values >= 0x60. */
250 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
251
252 if (timer < 0x60) {
253 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
254 }
255
256 #ifdef CONFIG_TULIP_USE_IO
257 /* read BAR for memory space access */
258 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
259 iobase &= PCI_BASE_ADDRESS_IO_MASK;
260 #else
261 /* read BAR for memory space access */
262 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
263 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
264 #endif
265 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
266
267 dev = (struct eth_device*) malloc(sizeof *dev);
268
269 if (!dev) {
270 printf("Can not allocalte memory of dc21x4x\n");
271 break;
272 }
273 memset(dev, 0, sizeof(*dev));
274
275 #ifdef CONFIG_TULIP_FIX_DAVICOM
276 sprintf(dev->name, "Davicom#%d", card_number);
277 #else
278 sprintf(dev->name, "dc21x4x#%d", card_number);
279 #endif
280
281 #ifdef CONFIG_TULIP_USE_IO
282 dev->iobase = pci_io_to_phys(devbusfn, iobase);
283 #else
284 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
285 #endif
286 dev->priv = (void*) devbusfn;
287 dev->init = dc21x4x_init;
288 dev->halt = dc21x4x_halt;
289 dev->send = dc21x4x_send;
290 dev->recv = dc21x4x_recv;
291
292 /* Ensure we're not sleeping. */
293 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
294
295 udelay(10 * 1000);
296
297 #ifndef CONFIG_TULIP_FIX_DAVICOM
298 read_hw_addr(dev, bis);
299 #endif
300 eth_register(dev);
301
302 card_number++;
303 }
304
305 return card_number;
306 }
307
308 static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
309 {
310 int i;
311 int devbusfn = (int) dev->priv;
312
313 /* Ensure we're not sleeping. */
314 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
315
316 #ifdef CONFIG_TULIP_FIX_DAVICOM
317 RESET_DM9102(dev);
318 #else
319 RESET_DE4X5(dev);
320 #endif
321
322 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
323 printf("Error: Cannot reset ethernet controller.\n");
324 return -1;
325 }
326
327 #ifdef CONFIG_TULIP_SELECT_MEDIA
328 dc21x4x_select_media(dev);
329 #else
330 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
331 #endif
332
333 for (i = 0; i < NUM_RX_DESC; i++) {
334 rx_ring[i].status = cpu_to_le32(R_OWN);
335 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
336 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
337 #ifdef CONFIG_TULIP_FIX_DAVICOM
338 rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
339 #else
340 rx_ring[i].next = 0;
341 #endif
342 }
343
344 for (i=0; i < NUM_TX_DESC; i++) {
345 tx_ring[i].status = 0;
346 tx_ring[i].des1 = 0;
347 tx_ring[i].buf = 0;
348
349 #ifdef CONFIG_TULIP_FIX_DAVICOM
350 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
351 #else
352 tx_ring[i].next = 0;
353 #endif
354 }
355
356 rxRingSize = NUM_RX_DESC;
357 txRingSize = NUM_TX_DESC;
358
359 /* Write the end of list marker to the descriptor lists. */
360 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
361 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
362
363 /* Tell the adapter where the TX/RX rings are located. */
364 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
365 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
366
367 START_DE4X5(dev);
368
369 tx_new = 0;
370 rx_new = 0;
371
372 send_setup_frame(dev, bis);
373
374 return 0;
375 }
376
377 static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
378 {
379 int status = -1;
380 int i;
381
382 if (length <= 0) {
383 printf("%s: bad packet size: %d\n", dev->name, length);
384 goto Done;
385 }
386
387 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
388 if (i >= TOUT_LOOP) {
389 printf("%s: tx error buffer not ready\n", dev->name);
390 goto Done;
391 }
392 }
393
394 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
395 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
396 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
397
398 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
399
400 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
401 if (i >= TOUT_LOOP) {
402 printf(".%s: tx buffer not ready\n", dev->name);
403 goto Done;
404 }
405 }
406
407 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
408 #if 0 /* test-only */
409 printf("TX error status = 0x%08X\n",
410 le32_to_cpu(tx_ring[tx_new].status));
411 #endif
412 tx_ring[tx_new].status = 0x0;
413 goto Done;
414 }
415
416 status = length;
417
418 Done:
419 tx_new = (tx_new+1) % NUM_TX_DESC;
420 return status;
421 }
422
423 static int dc21x4x_recv(struct eth_device* dev)
424 {
425 s32 status;
426 int length = 0;
427
428 for ( ; ; ) {
429 status = (s32)le32_to_cpu(rx_ring[rx_new].status);
430
431 if (status & R_OWN) {
432 break;
433 }
434
435 if (status & RD_LS) {
436 /* Valid frame status.
437 */
438 if (status & RD_ES) {
439
440 /* There was an error.
441 */
442 printf("RX error status = 0x%08X\n", status);
443 } else {
444 /* A valid frame received.
445 */
446 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
447
448 /* Pass the packet up to the protocol
449 * layers.
450 */
451 NetReceive(NetRxPackets[rx_new], length - 4);
452 }
453
454 /* Change buffer ownership for this frame, back
455 * to the adapter.
456 */
457 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
458 }
459
460 /* Update entry information.
461 */
462 rx_new = (rx_new + 1) % rxRingSize;
463 }
464
465 return length;
466 }
467
468 static void dc21x4x_halt(struct eth_device* dev)
469 {
470 int devbusfn = (int) dev->priv;
471
472 STOP_DE4X5(dev);
473 OUTL(dev, 0, DE4X5_SICR);
474
475 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
476 }
477
478 static void send_setup_frame(struct eth_device* dev, bd_t *bis)
479 {
480 int i;
481 char setup_frame[SETUP_FRAME_LEN];
482 char *pa = &setup_frame[0];
483
484 memset(pa, 0xff, SETUP_FRAME_LEN);
485
486 for (i = 0; i < ETH_ALEN; i++) {
487 *(pa + (i & 1)) = dev->enetaddr[i];
488 if (i & 0x01) {
489 pa += 4;
490 }
491 }
492
493 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
494 if (i >= TOUT_LOOP) {
495 printf("%s: tx error buffer not ready\n", dev->name);
496 goto Done;
497 }
498 }
499
500 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
501 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
502 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
503
504 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
505
506 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
507 if (i >= TOUT_LOOP) {
508 printf("%s: tx buffer not ready\n", dev->name);
509 goto Done;
510 }
511 }
512
513 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
514 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
515 }
516 tx_new = (tx_new+1) % NUM_TX_DESC;
517
518 Done:
519 return;
520 }
521
522 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
523 /* SROM Read and write routines.
524 */
525 static void
526 sendto_srom(struct eth_device* dev, u_int command, u_long addr)
527 {
528 OUTL(dev, command, addr);
529 udelay(1);
530 }
531
532 static int
533 getfrom_srom(struct eth_device* dev, u_long addr)
534 {
535 s32 tmp;
536
537 tmp = INL(dev, addr);
538 udelay(1);
539
540 return tmp;
541 }
542
543 /* Note: this routine returns extra data bits for size detection. */
544 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
545 {
546 int i;
547 unsigned retval = 0;
548 int read_cmd = location | (SROM_READ_CMD << addr_len);
549
550 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
551 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
552
553 #ifdef DEBUG_SROM
554 printf(" EEPROM read at %d ", location);
555 #endif
556
557 /* Shift the read command bits out. */
558 for (i = 4 + addr_len; i >= 0; i--) {
559 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
560 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
561 udelay(10);
562 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
563 udelay(10);
564 #ifdef DEBUG_SROM2
565 printf("%X", getfrom_srom(dev, ioaddr) & 15);
566 #endif
567 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
568 }
569
570 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
571
572 #ifdef DEBUG_SROM2
573 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
574 #endif
575
576 for (i = 16; i > 0; i--) {
577 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
578 udelay(10);
579 #ifdef DEBUG_SROM2
580 printf("%X", getfrom_srom(dev, ioaddr) & 15);
581 #endif
582 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
583 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
584 udelay(10);
585 }
586
587 /* Terminate the EEPROM access. */
588 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
589
590 #ifdef DEBUG_SROM2
591 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
592 #endif
593
594 return retval;
595 }
596 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
597
598 /* This executes a generic EEPROM command, typically a write or write
599 * enable. It returns the data output from the EEPROM, and thus may
600 * also be used for reads.
601 */
602 #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
603 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
604 {
605 unsigned retval = 0;
606
607 #ifdef DEBUG_SROM
608 printf(" EEPROM op 0x%x: ", cmd);
609 #endif
610
611 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
612
613 /* Shift the command bits out. */
614 do {
615 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
616 sendto_srom(dev,dataval, ioaddr);
617 udelay(10);
618
619 #ifdef DEBUG_SROM2
620 printf("%X", getfrom_srom(dev,ioaddr) & 15);
621 #endif
622
623 sendto_srom(dev,dataval | DT_CLK, ioaddr);
624 udelay(10);
625 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
626 } while (--cmd_len >= 0);
627 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
628
629 /* Terminate the EEPROM access. */
630 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
631
632 #ifdef DEBUG_SROM
633 printf(" EEPROM result is 0x%5.5x.\n", retval);
634 #endif
635
636 return retval;
637 }
638 #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
639
640 #ifndef CONFIG_TULIP_FIX_DAVICOM
641 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
642 {
643 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
644
645 return do_eeprom_cmd(dev, ioaddr,
646 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
647 | 0xffff, 3 + ee_addr_size + 16);
648 }
649 #endif /* CONFIG_TULIP_FIX_DAVICOM */
650
651 #ifdef UPDATE_SROM
652 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
653 {
654 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
655 int i;
656 unsigned short newval;
657
658 udelay(10*1000); /* test-only */
659
660 #ifdef DEBUG_SROM
661 printf("ee_addr_size=%d.\n", ee_addr_size);
662 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
663 #endif
664
665 /* Enable programming modes. */
666 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
667
668 /* Do the actual write. */
669 do_eeprom_cmd(dev, ioaddr,
670 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
671 3 + ee_addr_size + 16);
672
673 /* Poll for write finished. */
674 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
675 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
676 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
677 break;
678
679 #ifdef DEBUG_SROM
680 printf(" Write finished after %d ticks.\n", i);
681 #endif
682
683 /* Disable programming. */
684 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
685
686 /* And read the result. */
687 newval = do_eeprom_cmd(dev, ioaddr,
688 (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
689 | 0xffff, 3 + ee_addr_size + 16);
690 #ifdef DEBUG_SROM
691 printf(" New value at offset %d is %4.4x.\n", index, newval);
692 #endif
693 return 1;
694 }
695 #endif
696
697 #ifndef CONFIG_TULIP_FIX_DAVICOM
698 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
699 {
700 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
701 int i, j = 0;
702
703 for (i = 0; i < (ETH_ALEN >> 1); i++) {
704 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
705 *p = le16_to_cpu(tmp);
706 j += *p++;
707 }
708
709 if ((j == 0) || (j == 0x2fffd)) {
710 memset (dev->enetaddr, 0, ETH_ALEN);
711 debug ("Warning: can't read HW address from SROM.\n");
712 goto Done;
713 }
714
715 return;
716
717 Done:
718 #ifdef UPDATE_SROM
719 update_srom(dev, bis);
720 #endif
721 return;
722 }
723 #endif /* CONFIG_TULIP_FIX_DAVICOM */
724
725 #ifdef UPDATE_SROM
726 static void update_srom(struct eth_device *dev, bd_t *bis)
727 {
728 int i;
729 static unsigned short eeprom[0x40] = {
730 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
731 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
732 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
733 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
734 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
735 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
736 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
737 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
738 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
739 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
740 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
741 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
742 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
743 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
744 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
745 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
746 };
747 uchar enetaddr[6];
748
749 /* Ethernet Addr... */
750 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
751 return;
752 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
753 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
754 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
755
756 for (i=0; i<0x40; i++) {
757 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
758 }
759 }
760 #endif /* UPDATE_SROM */
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