drivers/net/designware.c

   1 /*
   2  * (C) Copyright 2010
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Designware ethernet IP driver for u-boot
  26  */
  27
  28 #include <common.h>
  29 #include <miiphy.h>
  30 #include <malloc.h>
  31 #include <linux/err.h>
  32 #include <asm/io.h>
  33 #include "designware.h"
  34
  35 static int configure_phy(struct eth_device *dev);
  36
  37 static void tx_descs_init(struct eth_device *dev)
  38 {
  39         struct dw_eth_dev *priv = dev->priv;
  40         struct eth_dma_regs *dma_p = priv->dma_regs_p;
  41         struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  42         char *txbuffs = &priv->txbuffs[0];
  43         struct dmamacdescr *desc_p;
  44         u32 idx;
  45
  46         for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  47                 desc_p = &desc_table_p[idx];
  48                 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
  49                 desc_p->dmamac_next = &desc_table_p[idx + 1];
  50
  51 #if defined(CONFIG_DW_ALTDESCRIPTOR)
  52                 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  53                                 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
  54                                 DESC_TXSTS_TXCHECKINSCTRL | \
  55                                 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  56
  57                 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  58                 desc_p->dmamac_cntl = 0;
  59                 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  60 #else
  61                 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  62                 desc_p->txrx_status = 0;
  63 #endif
  64         }
  65
  66         /* Correcting the last pointer of the chain */
  67         desc_p->dmamac_next = &desc_table_p[0];
  68
  69         writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  70 }
  71
  72 static void rx_descs_init(struct eth_device *dev)
  73 {
  74         struct dw_eth_dev *priv = dev->priv;
  75         struct eth_dma_regs *dma_p = priv->dma_regs_p;
  76         struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  77         char *rxbuffs = &priv->rxbuffs[0];
  78         struct dmamacdescr *desc_p;
  79         u32 idx;
  80
  81         for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  82                 desc_p = &desc_table_p[idx];
  83                 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  84                 desc_p->dmamac_next = &desc_table_p[idx + 1];
  85
  86                 desc_p->dmamac_cntl =
  87                         (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
  88                                       DESC_RXCTRL_RXCHAIN;
  89
  90                 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  91         }
  92
  93         /* Correcting the last pointer of the chain */
  94         desc_p->dmamac_next = &desc_table_p[0];
  95
  96         writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  97 }
  98
  99 static void descs_init(struct eth_device *dev)
 100 {
 101         tx_descs_init(dev);
 102         rx_descs_init(dev);
 103 }
 104
 105 static int mac_reset(struct eth_device *dev)
 106 {
 107         struct dw_eth_dev *priv = dev->priv;
 108         struct eth_mac_regs *mac_p = priv->mac_regs_p;
 109         struct eth_dma_regs *dma_p = priv->dma_regs_p;
 110
 111         ulong start;
 112         int timeout = CONFIG_MACRESET_TIMEOUT;
 113
 114         writel(DMAMAC_SRST, &dma_p->busmode);
 115         writel(MII_PORTSELECT, &mac_p->conf);
 116
 117         start = get_timer(0);
 118         while (get_timer(start) < timeout) {
 119                 if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
 120                         return 0;
 121
 122                 /* Try again after 10usec */
 123                 udelay(10);
 124         };
 125
 126         return -1;
 127 }
 128
 129 static int dw_write_hwaddr(struct eth_device *dev)
 130 {
 131         struct dw_eth_dev *priv = dev->priv;
 132         struct eth_mac_regs *mac_p = priv->mac_regs_p;
 133         u32 macid_lo, macid_hi;
 134         u8 *mac_id = &dev->enetaddr[0];
 135
 136         macid_lo = mac_id[0] + (mac_id[1] << 8) + \
 137                    (mac_id[2] << 16) + (mac_id[3] << 24);
 138         macid_hi = mac_id[4] + (mac_id[5] << 8);
 139
 140         writel(macid_hi, &mac_p->macaddr0hi);
 141         writel(macid_lo, &mac_p->macaddr0lo);
 142
 143         return 0;
 144 }
 145
 146 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 147 {
 148         struct dw_eth_dev *priv = dev->priv;
 149         struct eth_mac_regs *mac_p = priv->mac_regs_p;
 150         struct eth_dma_regs *dma_p = priv->dma_regs_p;
 151         u32 conf;
 152
 153         if (priv->phy_configured != 1)
 154                 configure_phy(dev);
 155
 156         /* Reset ethernet hardware */
 157         if (mac_reset(dev) < 0)
 158                 return -1;
 159
 160         /* Resore the HW MAC address as it has been lost during MAC reset */
 161         dw_write_hwaddr(dev);
 162
 163         writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
 164                         &dma_p->busmode);
 165
 166         writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
 167         writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
 168
 169         conf = FRAMEBURSTENABLE | DISABLERXOWN;
 170
 171         if (priv->speed != SPEED_1000M)
 172                 conf |= MII_PORTSELECT;
 173
 174         if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
 175                 (priv->interface != PHY_INTERFACE_MODE_GMII)) {
 176
 177                 if (priv->speed == SPEED_100M)
 178                         conf |= FES_100;
 179         }
 180
 181         if (priv->duplex == FULL_DUPLEX)
 182                 conf |= FULLDPLXMODE;
 183
 184         writel(conf, &mac_p->conf);
 185
 186         descs_init(dev);
 187
 188         /*
 189          * Start/Enable xfer at dma as well as mac level
 190          */
 191         writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
 192         writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
 193
 194         writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
 195
 196         return 0;
 197 }
 198
 199 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 200 {
 201         struct dw_eth_dev *priv = dev->priv;
 202         struct eth_dma_regs *dma_p = priv->dma_regs_p;
 203         u32 desc_num = priv->tx_currdescnum;
 204         struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
 205
 206         /* Check if the descriptor is owned by CPU */
 207         if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
 208                 printf("CPU not owner of tx frame\n");
 209                 return -1;
 210         }
 211
 212         memcpy((void *)desc_p->dmamac_addr, packet, length);
 213
 214 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 215         desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
 216         desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
 217                                DESC_TXCTRL_SIZE1MASK;
 218
 219         desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
 220         desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
 221 #else
 222         desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
 223                                DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
 224                                DESC_TXCTRL_TXFIRST;
 225
 226         desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
 227 #endif
 228
 229         /* Test the wrap-around condition. */
 230         if (++desc_num >= CONFIG_TX_DESCR_NUM)
 231                 desc_num = 0;
 232
 233         priv->tx_currdescnum = desc_num;
 234
 235         /* Start the transmission */
 236         writel(POLL_DATA, &dma_p->txpolldemand);
 237
 238         return 0;
 239 }
 240
 241 static int dw_eth_recv(struct eth_device *dev)
 242 {
 243         struct dw_eth_dev *priv = dev->priv;
 244         u32 desc_num = priv->rx_currdescnum;
 245         struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
 246
 247         u32 status = desc_p->txrx_status;
 248         int length = 0;
 249
 250         /* Check  if the owner is the CPU */
 251         if (!(status & DESC_RXSTS_OWNBYDMA)) {
 252
 253                 length = (status & DESC_RXSTS_FRMLENMSK) >> \
 254                          DESC_RXSTS_FRMLENSHFT;
 255
 256                 NetReceive(desc_p->dmamac_addr, length);
 257
 258                 /*
 259                  * Make the current descriptor valid again and go to
 260                  * the next one
 261                  */
 262                 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
 263
 264                 /* Test the wrap-around condition. */
 265                 if (++desc_num >= CONFIG_RX_DESCR_NUM)
 266                         desc_num = 0;
 267         }
 268
 269         priv->rx_currdescnum = desc_num;
 270
 271         return length;
 272 }
 273
 274 static void dw_eth_halt(struct eth_device *dev)
 275 {
 276         struct dw_eth_dev *priv = dev->priv;
 277
 278         mac_reset(dev);
 279         priv->tx_currdescnum = priv->rx_currdescnum = 0;
 280 }
 281
 282 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
 283 {
 284         struct dw_eth_dev *priv = dev->priv;
 285         struct eth_mac_regs *mac_p = priv->mac_regs_p;
 286         ulong start;
 287         u32 miiaddr;
 288         int timeout = CONFIG_MDIO_TIMEOUT;
 289
 290         miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
 291                   ((reg << MIIREGSHIFT) & MII_REGMSK);
 292
 293         writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
 294
 295         start = get_timer(0);
 296         while (get_timer(start) < timeout) {
 297                 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
 298                         *val = readl(&mac_p->miidata);
 299                         return 0;
 300                 }
 301
 302                 /* Try again after 10usec */
 303                 udelay(10);
 304         };
 305
 306         return -1;
 307 }
 308
 309 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
 310 {
 311         struct dw_eth_dev *priv = dev->priv;
 312         struct eth_mac_regs *mac_p = priv->mac_regs_p;
 313         ulong start;
 314         u32 miiaddr;
 315         int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
 316         u16 value;
 317
 318         writel(val, &mac_p->miidata);
 319         miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
 320                   ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
 321
 322         writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
 323
 324         start = get_timer(0);
 325         while (get_timer(start) < timeout) {
 326                 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
 327                         ret = 0;
 328                         break;
 329                 }
 330
 331                 /* Try again after 10usec */
 332                 udelay(10);
 333         };
 334
 335         /* Needed as a fix for ST-Phy */
 336         eth_mdio_read(dev, addr, reg, &value);
 337
 338         return ret;
 339 }
 340
 341 #if defined(CONFIG_DW_SEARCH_PHY)
 342 static int find_phy(struct eth_device *dev)
 343 {
 344         int phy_addr = 0;
 345         u16 ctrl, oldctrl;
 346
 347         do {
 348                 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
 349                 oldctrl = ctrl & BMCR_ANENABLE;
 350
 351                 ctrl ^= BMCR_ANENABLE;
 352                 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
 353                 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
 354                 ctrl &= BMCR_ANENABLE;
 355
 356                 if (ctrl == oldctrl) {
 357                         phy_addr++;
 358                 } else {
 359                         ctrl ^= BMCR_ANENABLE;
 360                         eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
 361
 362                         return phy_addr;
 363                 }
 364         } while (phy_addr < 32);
 365
 366         return -1;
 367 }
 368 #endif
 369
 370 static int dw_reset_phy(struct eth_device *dev)
 371 {
 372         struct dw_eth_dev *priv = dev->priv;
 373         u16 ctrl;
 374         ulong start;
 375         int timeout = CONFIG_PHYRESET_TIMEOUT;
 376         u32 phy_addr = priv->address;
 377
 378         eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
 379
 380         start = get_timer(0);
 381         while (get_timer(start) < timeout) {
 382                 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
 383                 if (!(ctrl & BMCR_RESET))
 384                         break;
 385
 386                 /* Try again after 10usec */
 387                 udelay(10);
 388         };
 389
 390         if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
 391                 return -1;
 392
 393 #ifdef CONFIG_PHY_RESET_DELAY
 394         udelay(CONFIG_PHY_RESET_DELAY);
 395 #endif
 396         return 0;
 397 }
 398
 399 static int configure_phy(struct eth_device *dev)
 400 {
 401         struct dw_eth_dev *priv = dev->priv;
 402         int phy_addr;
 403         u16 bmcr;
 404 #if defined(CONFIG_DW_AUTONEG)
 405         u16 bmsr;
 406         u32 timeout;
 407         ulong start;
 408         u16 anlpar, btsr;
 409 #else
 410         u16 ctrl;
 411 #endif
 412
 413 #if defined(CONFIG_DW_SEARCH_PHY)
 414         phy_addr = find_phy(dev);
 415         if (phy_addr >= 0)
 416                 priv->address = phy_addr;
 417         else
 418                 return -1;
 419 #else
 420         phy_addr = priv->address;
 421 #endif
 422         if (dw_reset_phy(dev) < 0)
 423                 return -1;
 424
 425 #if defined(CONFIG_DW_AUTONEG)
 426         /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
 427         eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
 428
 429         bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 430 #else
 431         bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
 432
 433 #if defined(CONFIG_DW_SPEED10M)
 434         bmcr &= ~BMCR_SPEED100;
 435 #endif
 436 #if defined(CONFIG_DW_DUPLEXHALF)
 437         bmcr &= ~BMCR_FULLDPLX;
 438 #endif
 439 #endif
 440         if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
 441                 return -1;
 442
 443         /* Read the phy status register and populate priv structure */
 444 #if defined(CONFIG_DW_AUTONEG)
 445         timeout = CONFIG_AUTONEG_TIMEOUT;
 446         start = get_timer(0);
 447
 448         while (get_timer(start) < timeout) {
 449                 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
 450                 if (bmsr & BMSR_ANEGCOMPLETE)
 451                         break;
 452
 453                 /* Try again after 10usec */
 454                 udelay(10);
 455         };
 456
 457         eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
 458         eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
 459
 460         if (bmsr & BMSR_ANEGCOMPLETE) {
 461                 if (btsr & PHY_1000BTSR_1000FD) {
 462                         priv->speed = SPEED_1000M;
 463                         bmcr |= BMCR_SPEED1000;
 464                         priv->duplex = FULL_DUPLEX;
 465                         bmcr |= BMCR_FULLDPLX;
 466                 } else if (btsr & PHY_1000BTSR_1000HD) {
 467                         priv->speed = SPEED_1000M;
 468                         bmcr |= BMCR_SPEED1000;
 469                         priv->duplex = HALF_DUPLEX;
 470                         bmcr &= ~BMCR_FULLDPLX;
 471                 } else if (anlpar & LPA_100FULL) {
 472                         priv->speed = SPEED_100M;
 473                         bmcr |= BMCR_SPEED100;
 474                         priv->duplex = FULL_DUPLEX;
 475                         bmcr |= BMCR_FULLDPLX;
 476                 } else if (anlpar & LPA_100HALF) {
 477                         priv->speed = SPEED_100M;
 478                         bmcr |= BMCR_SPEED100;
 479                         priv->duplex = HALF_DUPLEX;
 480                         bmcr &= ~BMCR_FULLDPLX;
 481                 } else if (anlpar & LPA_10FULL) {
 482                         priv->speed = SPEED_10M;
 483                         bmcr &= ~BMCR_SPEED100;
 484                         priv->duplex = FULL_DUPLEX;
 485                         bmcr |= BMCR_FULLDPLX;
 486                 } else {
 487                                 priv->speed = SPEED_10M;
 488                                 bmcr &= ~BMCR_SPEED100;
 489                                 priv->duplex = HALF_DUPLEX;
 490                                 bmcr &= ~BMCR_FULLDPLX;
 491                 }
 492                 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
 493                         return -1;
 494         } else
 495                 return -1;
 496 #else
 497         if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
 498                 return -1;
 499
 500         if (ctrl & BMCR_FULLDPLX)
 501                 priv->duplex = FULL_DUPLEX;
 502         else
 503                 priv->duplex = HALF_DUPLEX;
 504
 505         if (ctrl & BMCR_SPEED1000)
 506                 priv->speed = SPEED_1000M;
 507         else if (ctrl & BMCR_SPEED100)
 508                 priv->speed = SPEED_100M;
 509         else
 510                 priv->speed = SPEED_10M;
 511 #endif
 512         priv->phy_configured = 1;
 513
 514         return 0;
 515 }
 516
 517 #if defined(CONFIG_MII)
 518 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
 519 {
 520         struct eth_device *dev;
 521
 522         dev = eth_get_dev_by_name(devname);
 523         if (dev)
 524                 eth_mdio_read(dev, addr, reg, val);
 525
 526         return 0;
 527 }
 528
 529 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
 530 {
 531         struct eth_device *dev;
 532
 533         dev = eth_get_dev_by_name(devname);
 534         if (dev)
 535                 eth_mdio_write(dev, addr, reg, val);
 536
 537         return 0;
 538 }
 539 #endif
 540
 541 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
 542 {
 543         struct eth_device *dev;
 544         struct dw_eth_dev *priv;
 545
 546         dev = (struct eth_device *) malloc(sizeof(struct eth_device));
 547         if (!dev)
 548                 return -ENOMEM;
 549
 550         /*
 551          * Since the priv structure contains the descriptors which need a strict
 552          * buswidth alignment, memalign is used to allocate memory
 553          */
 554         priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
 555         if (!priv) {
 556                 free(dev);
 557                 return -ENOMEM;
 558         }
 559
 560         memset(dev, 0, sizeof(struct eth_device));
 561         memset(priv, 0, sizeof(struct dw_eth_dev));
 562
 563         sprintf(dev->name, "mii%d", id);
 564         dev->iobase = (int)base_addr;
 565         dev->priv = priv;
 566
 567         eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
 568
 569         priv->dev = dev;
 570         priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
 571         priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
 572                         DW_DMA_BASE_OFFSET);
 573         priv->address = phy_addr;
 574         priv->phy_configured = 0;
 575         priv->interface = interface;
 576
 577         if (mac_reset(dev) < 0)
 578                 return -1;
 579
 580         configure_phy(dev);
 581
 582         dev->init = dw_eth_init;
 583         dev->send = dw_eth_send;
 584         dev->recv = dw_eth_recv;
 585         dev->halt = dw_eth_halt;
 586         dev->write_hwaddr = dw_write_hwaddr;
 587
 588         eth_register(dev);
 589
 590 #if defined(CONFIG_MII)
 591         miiphy_register(dev->name, dw_mii_read, dw_mii_write);
 592 #endif
 593         return 1;
 594 }