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[thirdparty/u-boot.git] / drivers / net / designware.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 */
6
7 /*
8 * Designware ethernet IP driver for U-Boot
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <cpu_func.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <miiphy.h>
17 #include <malloc.h>
18 #include <pci.h>
19 #include <reset.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/compiler.h>
23 #include <linux/err.h>
24 #include <linux/kernel.h>
25 #include <asm/io.h>
26 #include <power/regulator.h>
27 #include "designware.h"
28
29 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
30 {
31 #ifdef CONFIG_DM_ETH
32 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
33 struct eth_mac_regs *mac_p = priv->mac_regs_p;
34 #else
35 struct eth_mac_regs *mac_p = bus->priv;
36 #endif
37 ulong start;
38 u16 miiaddr;
39 int timeout = CONFIG_MDIO_TIMEOUT;
40
41 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
42 ((reg << MIIREGSHIFT) & MII_REGMSK);
43
44 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
45
46 start = get_timer(0);
47 while (get_timer(start) < timeout) {
48 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
49 return readl(&mac_p->miidata);
50 udelay(10);
51 };
52
53 return -ETIMEDOUT;
54 }
55
56 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
57 u16 val)
58 {
59 #ifdef CONFIG_DM_ETH
60 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
61 struct eth_mac_regs *mac_p = priv->mac_regs_p;
62 #else
63 struct eth_mac_regs *mac_p = bus->priv;
64 #endif
65 ulong start;
66 u16 miiaddr;
67 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
68
69 writel(val, &mac_p->miidata);
70 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
71 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
72
73 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
74
75 start = get_timer(0);
76 while (get_timer(start) < timeout) {
77 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
78 ret = 0;
79 break;
80 }
81 udelay(10);
82 };
83
84 return ret;
85 }
86
87 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
88 static int dw_mdio_reset(struct mii_dev *bus)
89 {
90 struct udevice *dev = bus->priv;
91 struct dw_eth_dev *priv = dev_get_priv(dev);
92 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
93 int ret;
94
95 if (!dm_gpio_is_valid(&priv->reset_gpio))
96 return 0;
97
98 /* reset the phy */
99 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
100 if (ret)
101 return ret;
102
103 udelay(pdata->reset_delays[0]);
104
105 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
106 if (ret)
107 return ret;
108
109 udelay(pdata->reset_delays[1]);
110
111 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
112 if (ret)
113 return ret;
114
115 udelay(pdata->reset_delays[2]);
116
117 return 0;
118 }
119 #endif
120
121 static int dw_mdio_init(const char *name, void *priv)
122 {
123 struct mii_dev *bus = mdio_alloc();
124
125 if (!bus) {
126 printf("Failed to allocate MDIO bus\n");
127 return -ENOMEM;
128 }
129
130 bus->read = dw_mdio_read;
131 bus->write = dw_mdio_write;
132 snprintf(bus->name, sizeof(bus->name), "%s", name);
133 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
134 bus->reset = dw_mdio_reset;
135 #endif
136
137 bus->priv = priv;
138
139 return mdio_register(bus);
140 }
141
142 static void tx_descs_init(struct dw_eth_dev *priv)
143 {
144 struct eth_dma_regs *dma_p = priv->dma_regs_p;
145 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
146 char *txbuffs = &priv->txbuffs[0];
147 struct dmamacdescr *desc_p;
148 u32 idx;
149
150 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
151 desc_p = &desc_table_p[idx];
152 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
153 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
154
155 #if defined(CONFIG_DW_ALTDESCRIPTOR)
156 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
157 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
158 DESC_TXSTS_TXCHECKINSCTRL |
159 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
160
161 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
162 desc_p->dmamac_cntl = 0;
163 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
164 #else
165 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
166 desc_p->txrx_status = 0;
167 #endif
168 }
169
170 /* Correcting the last pointer of the chain */
171 desc_p->dmamac_next = (ulong)&desc_table_p[0];
172
173 /* Flush all Tx buffer descriptors at once */
174 flush_dcache_range((ulong)priv->tx_mac_descrtable,
175 (ulong)priv->tx_mac_descrtable +
176 sizeof(priv->tx_mac_descrtable));
177
178 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
179 priv->tx_currdescnum = 0;
180 }
181
182 static void rx_descs_init(struct dw_eth_dev *priv)
183 {
184 struct eth_dma_regs *dma_p = priv->dma_regs_p;
185 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
186 char *rxbuffs = &priv->rxbuffs[0];
187 struct dmamacdescr *desc_p;
188 u32 idx;
189
190 /* Before passing buffers to GMAC we need to make sure zeros
191 * written there right after "priv" structure allocation were
192 * flushed into RAM.
193 * Otherwise there's a chance to get some of them flushed in RAM when
194 * GMAC is already pushing data to RAM via DMA. This way incoming from
195 * GMAC data will be corrupted. */
196 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
197
198 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
199 desc_p = &desc_table_p[idx];
200 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
201 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
202
203 desc_p->dmamac_cntl =
204 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
205 DESC_RXCTRL_RXCHAIN;
206
207 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
208 }
209
210 /* Correcting the last pointer of the chain */
211 desc_p->dmamac_next = (ulong)&desc_table_p[0];
212
213 /* Flush all Rx buffer descriptors at once */
214 flush_dcache_range((ulong)priv->rx_mac_descrtable,
215 (ulong)priv->rx_mac_descrtable +
216 sizeof(priv->rx_mac_descrtable));
217
218 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
219 priv->rx_currdescnum = 0;
220 }
221
222 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
223 {
224 struct eth_mac_regs *mac_p = priv->mac_regs_p;
225 u32 macid_lo, macid_hi;
226
227 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
228 (mac_id[3] << 24);
229 macid_hi = mac_id[4] + (mac_id[5] << 8);
230
231 writel(macid_hi, &mac_p->macaddr0hi);
232 writel(macid_lo, &mac_p->macaddr0lo);
233
234 return 0;
235 }
236
237 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
238 struct phy_device *phydev)
239 {
240 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
241
242 if (!phydev->link) {
243 printf("%s: No link.\n", phydev->dev->name);
244 return 0;
245 }
246
247 if (phydev->speed != 1000)
248 conf |= MII_PORTSELECT;
249 else
250 conf &= ~MII_PORTSELECT;
251
252 if (phydev->speed == 100)
253 conf |= FES_100;
254
255 if (phydev->duplex)
256 conf |= FULLDPLXMODE;
257
258 writel(conf, &mac_p->conf);
259
260 printf("Speed: %d, %s duplex%s\n", phydev->speed,
261 (phydev->duplex) ? "full" : "half",
262 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
263
264 return 0;
265 }
266
267 static void _dw_eth_halt(struct dw_eth_dev *priv)
268 {
269 struct eth_mac_regs *mac_p = priv->mac_regs_p;
270 struct eth_dma_regs *dma_p = priv->dma_regs_p;
271
272 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
273 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
274
275 phy_shutdown(priv->phydev);
276 }
277
278 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
279 {
280 struct eth_mac_regs *mac_p = priv->mac_regs_p;
281 struct eth_dma_regs *dma_p = priv->dma_regs_p;
282 unsigned int start;
283 int ret;
284
285 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
286
287 /*
288 * When a MII PHY is used, we must set the PS bit for the DMA
289 * reset to succeed.
290 */
291 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
292 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
293 else
294 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
295
296 start = get_timer(0);
297 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
298 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
299 printf("DMA reset timeout\n");
300 return -ETIMEDOUT;
301 }
302
303 mdelay(100);
304 };
305
306 /*
307 * Soft reset above clears HW address registers.
308 * So we have to set it here once again.
309 */
310 _dw_write_hwaddr(priv, enetaddr);
311
312 rx_descs_init(priv);
313 tx_descs_init(priv);
314
315 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
316
317 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
318 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
319 &dma_p->opmode);
320 #else
321 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
322 &dma_p->opmode);
323 #endif
324
325 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
326
327 #ifdef CONFIG_DW_AXI_BURST_LEN
328 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
329 #endif
330
331 /* Start up the PHY */
332 ret = phy_startup(priv->phydev);
333 if (ret) {
334 printf("Could not initialize PHY %s\n",
335 priv->phydev->dev->name);
336 return ret;
337 }
338
339 ret = dw_adjust_link(priv, mac_p, priv->phydev);
340 if (ret)
341 return ret;
342
343 return 0;
344 }
345
346 int designware_eth_enable(struct dw_eth_dev *priv)
347 {
348 struct eth_mac_regs *mac_p = priv->mac_regs_p;
349
350 if (!priv->phydev->link)
351 return -EIO;
352
353 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
354
355 return 0;
356 }
357
358 #define ETH_ZLEN 60
359
360 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
361 {
362 struct eth_dma_regs *dma_p = priv->dma_regs_p;
363 u32 desc_num = priv->tx_currdescnum;
364 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
365 ulong desc_start = (ulong)desc_p;
366 ulong desc_end = desc_start +
367 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
368 ulong data_start = desc_p->dmamac_addr;
369 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
370 /*
371 * Strictly we only need to invalidate the "txrx_status" field
372 * for the following check, but on some platforms we cannot
373 * invalidate only 4 bytes, so we flush the entire descriptor,
374 * which is 16 bytes in total. This is safe because the
375 * individual descriptors in the array are each aligned to
376 * ARCH_DMA_MINALIGN and padded appropriately.
377 */
378 invalidate_dcache_range(desc_start, desc_end);
379
380 /* Check if the descriptor is owned by CPU */
381 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
382 printf("CPU not owner of tx frame\n");
383 return -EPERM;
384 }
385
386 memcpy((void *)data_start, packet, length);
387 if (length < ETH_ZLEN) {
388 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
389 length = ETH_ZLEN;
390 }
391
392 /* Flush data to be sent */
393 flush_dcache_range(data_start, data_end);
394
395 #if defined(CONFIG_DW_ALTDESCRIPTOR)
396 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
397 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
398 ((length << DESC_TXCTRL_SIZE1SHFT) &
399 DESC_TXCTRL_SIZE1MASK);
400
401 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
402 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
403 #else
404 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
405 ((length << DESC_TXCTRL_SIZE1SHFT) &
406 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
407 DESC_TXCTRL_TXFIRST;
408
409 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
410 #endif
411
412 /* Flush modified buffer descriptor */
413 flush_dcache_range(desc_start, desc_end);
414
415 /* Test the wrap-around condition. */
416 if (++desc_num >= CONFIG_TX_DESCR_NUM)
417 desc_num = 0;
418
419 priv->tx_currdescnum = desc_num;
420
421 /* Start the transmission */
422 writel(POLL_DATA, &dma_p->txpolldemand);
423
424 return 0;
425 }
426
427 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
428 {
429 u32 status, desc_num = priv->rx_currdescnum;
430 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
431 int length = -EAGAIN;
432 ulong desc_start = (ulong)desc_p;
433 ulong desc_end = desc_start +
434 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
435 ulong data_start = desc_p->dmamac_addr;
436 ulong data_end;
437
438 /* Invalidate entire buffer descriptor */
439 invalidate_dcache_range(desc_start, desc_end);
440
441 status = desc_p->txrx_status;
442
443 /* Check if the owner is the CPU */
444 if (!(status & DESC_RXSTS_OWNBYDMA)) {
445
446 length = (status & DESC_RXSTS_FRMLENMSK) >>
447 DESC_RXSTS_FRMLENSHFT;
448
449 /* Invalidate received data */
450 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
451 invalidate_dcache_range(data_start, data_end);
452 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
453 }
454
455 return length;
456 }
457
458 static int _dw_free_pkt(struct dw_eth_dev *priv)
459 {
460 u32 desc_num = priv->rx_currdescnum;
461 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
462 ulong desc_start = (ulong)desc_p;
463 ulong desc_end = desc_start +
464 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
465
466 /*
467 * Make the current descriptor valid again and go to
468 * the next one
469 */
470 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
471
472 /* Flush only status field - others weren't changed */
473 flush_dcache_range(desc_start, desc_end);
474
475 /* Test the wrap-around condition. */
476 if (++desc_num >= CONFIG_RX_DESCR_NUM)
477 desc_num = 0;
478 priv->rx_currdescnum = desc_num;
479
480 return 0;
481 }
482
483 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
484 {
485 struct phy_device *phydev;
486 int phy_addr = -1, ret;
487
488 #ifdef CONFIG_PHY_ADDR
489 phy_addr = CONFIG_PHY_ADDR;
490 #endif
491
492 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
493 if (!phydev)
494 return -ENODEV;
495
496 phydev->supported &= PHY_GBIT_FEATURES;
497 if (priv->max_speed) {
498 ret = phy_set_supported(phydev, priv->max_speed);
499 if (ret)
500 return ret;
501 }
502 phydev->advertising = phydev->supported;
503
504 priv->phydev = phydev;
505 phy_config(phydev);
506
507 return 0;
508 }
509
510 #ifndef CONFIG_DM_ETH
511 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
512 {
513 int ret;
514
515 ret = designware_eth_init(dev->priv, dev->enetaddr);
516 if (!ret)
517 ret = designware_eth_enable(dev->priv);
518
519 return ret;
520 }
521
522 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
523 {
524 return _dw_eth_send(dev->priv, packet, length);
525 }
526
527 static int dw_eth_recv(struct eth_device *dev)
528 {
529 uchar *packet;
530 int length;
531
532 length = _dw_eth_recv(dev->priv, &packet);
533 if (length == -EAGAIN)
534 return 0;
535 net_process_received_packet(packet, length);
536
537 _dw_free_pkt(dev->priv);
538
539 return 0;
540 }
541
542 static void dw_eth_halt(struct eth_device *dev)
543 {
544 return _dw_eth_halt(dev->priv);
545 }
546
547 static int dw_write_hwaddr(struct eth_device *dev)
548 {
549 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
550 }
551
552 int designware_initialize(ulong base_addr, u32 interface)
553 {
554 struct eth_device *dev;
555 struct dw_eth_dev *priv;
556
557 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
558 if (!dev)
559 return -ENOMEM;
560
561 /*
562 * Since the priv structure contains the descriptors which need a strict
563 * buswidth alignment, memalign is used to allocate memory
564 */
565 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
566 sizeof(struct dw_eth_dev));
567 if (!priv) {
568 free(dev);
569 return -ENOMEM;
570 }
571
572 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
573 printf("designware: buffers are outside DMA memory\n");
574 return -EINVAL;
575 }
576
577 memset(dev, 0, sizeof(struct eth_device));
578 memset(priv, 0, sizeof(struct dw_eth_dev));
579
580 sprintf(dev->name, "dwmac.%lx", base_addr);
581 dev->iobase = (int)base_addr;
582 dev->priv = priv;
583
584 priv->dev = dev;
585 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
586 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
587 DW_DMA_BASE_OFFSET);
588
589 dev->init = dw_eth_init;
590 dev->send = dw_eth_send;
591 dev->recv = dw_eth_recv;
592 dev->halt = dw_eth_halt;
593 dev->write_hwaddr = dw_write_hwaddr;
594
595 eth_register(dev);
596
597 priv->interface = interface;
598
599 dw_mdio_init(dev->name, priv->mac_regs_p);
600 priv->bus = miiphy_get_dev_by_name(dev->name);
601
602 return dw_phy_init(priv, dev);
603 }
604 #endif
605
606 #ifdef CONFIG_DM_ETH
607 static int designware_eth_start(struct udevice *dev)
608 {
609 struct eth_pdata *pdata = dev_get_platdata(dev);
610 struct dw_eth_dev *priv = dev_get_priv(dev);
611 int ret;
612
613 ret = designware_eth_init(priv, pdata->enetaddr);
614 if (ret)
615 return ret;
616 ret = designware_eth_enable(priv);
617 if (ret)
618 return ret;
619
620 return 0;
621 }
622
623 int designware_eth_send(struct udevice *dev, void *packet, int length)
624 {
625 struct dw_eth_dev *priv = dev_get_priv(dev);
626
627 return _dw_eth_send(priv, packet, length);
628 }
629
630 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
631 {
632 struct dw_eth_dev *priv = dev_get_priv(dev);
633
634 return _dw_eth_recv(priv, packetp);
635 }
636
637 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
638 {
639 struct dw_eth_dev *priv = dev_get_priv(dev);
640
641 return _dw_free_pkt(priv);
642 }
643
644 void designware_eth_stop(struct udevice *dev)
645 {
646 struct dw_eth_dev *priv = dev_get_priv(dev);
647
648 return _dw_eth_halt(priv);
649 }
650
651 int designware_eth_write_hwaddr(struct udevice *dev)
652 {
653 struct eth_pdata *pdata = dev_get_platdata(dev);
654 struct dw_eth_dev *priv = dev_get_priv(dev);
655
656 return _dw_write_hwaddr(priv, pdata->enetaddr);
657 }
658
659 static int designware_eth_bind(struct udevice *dev)
660 {
661 #ifdef CONFIG_DM_PCI
662 static int num_cards;
663 char name[20];
664
665 /* Create a unique device name for PCI type devices */
666 if (device_is_on_pci_bus(dev)) {
667 sprintf(name, "eth_designware#%u", num_cards++);
668 device_set_name(dev, name);
669 }
670 #endif
671
672 return 0;
673 }
674
675 int designware_eth_probe(struct udevice *dev)
676 {
677 struct eth_pdata *pdata = dev_get_platdata(dev);
678 struct dw_eth_dev *priv = dev_get_priv(dev);
679 u32 iobase = pdata->iobase;
680 ulong ioaddr;
681 int ret, err;
682 struct reset_ctl_bulk reset_bulk;
683 #ifdef CONFIG_CLK
684 int i, clock_nb;
685
686 priv->clock_count = 0;
687 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
688 if (clock_nb > 0) {
689 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
690 GFP_KERNEL);
691 if (!priv->clocks)
692 return -ENOMEM;
693
694 for (i = 0; i < clock_nb; i++) {
695 err = clk_get_by_index(dev, i, &priv->clocks[i]);
696 if (err < 0)
697 break;
698
699 err = clk_enable(&priv->clocks[i]);
700 if (err && err != -ENOSYS && err != -ENOTSUPP) {
701 pr_err("failed to enable clock %d\n", i);
702 clk_free(&priv->clocks[i]);
703 goto clk_err;
704 }
705 priv->clock_count++;
706 }
707 } else if (clock_nb != -ENOENT) {
708 pr_err("failed to get clock phandle(%d)\n", clock_nb);
709 return clock_nb;
710 }
711 #endif
712
713 #if defined(CONFIG_DM_REGULATOR)
714 struct udevice *phy_supply;
715
716 ret = device_get_supply_regulator(dev, "phy-supply",
717 &phy_supply);
718 if (ret) {
719 debug("%s: No phy supply\n", dev->name);
720 } else {
721 ret = regulator_set_enable(phy_supply, true);
722 if (ret) {
723 puts("Error enabling phy supply\n");
724 return ret;
725 }
726 }
727 #endif
728
729 ret = reset_get_bulk(dev, &reset_bulk);
730 if (ret)
731 dev_warn(dev, "Can't get reset: %d\n", ret);
732 else
733 reset_deassert_bulk(&reset_bulk);
734
735 #ifdef CONFIG_DM_PCI
736 /*
737 * If we are on PCI bus, either directly attached to a PCI root port,
738 * or via a PCI bridge, fill in platdata before we probe the hardware.
739 */
740 if (device_is_on_pci_bus(dev)) {
741 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
742 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
743 iobase = dm_pci_mem_to_phys(dev, iobase);
744
745 pdata->iobase = iobase;
746 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
747 }
748 #endif
749
750 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
751 ioaddr = iobase;
752 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
753 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
754 priv->interface = pdata->phy_interface;
755 priv->max_speed = pdata->max_speed;
756
757 ret = dw_mdio_init(dev->name, dev);
758 if (ret) {
759 err = ret;
760 goto mdio_err;
761 }
762 priv->bus = miiphy_get_dev_by_name(dev->name);
763
764 ret = dw_phy_init(priv, dev);
765 debug("%s, ret=%d\n", __func__, ret);
766 if (!ret)
767 return 0;
768
769 /* continue here for cleanup if no PHY found */
770 err = ret;
771 mdio_unregister(priv->bus);
772 mdio_free(priv->bus);
773 mdio_err:
774
775 #ifdef CONFIG_CLK
776 clk_err:
777 ret = clk_release_all(priv->clocks, priv->clock_count);
778 if (ret)
779 pr_err("failed to disable all clocks\n");
780
781 #endif
782 return err;
783 }
784
785 static int designware_eth_remove(struct udevice *dev)
786 {
787 struct dw_eth_dev *priv = dev_get_priv(dev);
788
789 free(priv->phydev);
790 mdio_unregister(priv->bus);
791 mdio_free(priv->bus);
792
793 #ifdef CONFIG_CLK
794 return clk_release_all(priv->clocks, priv->clock_count);
795 #else
796 return 0;
797 #endif
798 }
799
800 const struct eth_ops designware_eth_ops = {
801 .start = designware_eth_start,
802 .send = designware_eth_send,
803 .recv = designware_eth_recv,
804 .free_pkt = designware_eth_free_pkt,
805 .stop = designware_eth_stop,
806 .write_hwaddr = designware_eth_write_hwaddr,
807 };
808
809 int designware_eth_ofdata_to_platdata(struct udevice *dev)
810 {
811 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
812 #if CONFIG_IS_ENABLED(DM_GPIO)
813 struct dw_eth_dev *priv = dev_get_priv(dev);
814 #endif
815 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
816 const char *phy_mode;
817 #if CONFIG_IS_ENABLED(DM_GPIO)
818 int reset_flags = GPIOD_IS_OUT;
819 #endif
820 int ret = 0;
821
822 pdata->iobase = dev_read_addr(dev);
823 pdata->phy_interface = -1;
824 phy_mode = dev_read_string(dev, "phy-mode");
825 if (phy_mode)
826 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
827 if (pdata->phy_interface == -1) {
828 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
829 return -EINVAL;
830 }
831
832 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
833
834 #if CONFIG_IS_ENABLED(DM_GPIO)
835 if (dev_read_bool(dev, "snps,reset-active-low"))
836 reset_flags |= GPIOD_ACTIVE_LOW;
837
838 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
839 &priv->reset_gpio, reset_flags);
840 if (ret == 0) {
841 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
842 dw_pdata->reset_delays, 3);
843 } else if (ret == -ENOENT) {
844 ret = 0;
845 }
846 #endif
847
848 return ret;
849 }
850
851 static const struct udevice_id designware_eth_ids[] = {
852 { .compatible = "allwinner,sun7i-a20-gmac" },
853 { .compatible = "amlogic,meson6-dwmac" },
854 { .compatible = "amlogic,meson-gx-dwmac" },
855 { .compatible = "amlogic,meson-gxbb-dwmac" },
856 { .compatible = "amlogic,meson-axg-dwmac" },
857 { .compatible = "st,stm32-dwmac" },
858 { .compatible = "snps,arc-dwmac-3.70a" },
859 { }
860 };
861
862 U_BOOT_DRIVER(eth_designware) = {
863 .name = "eth_designware",
864 .id = UCLASS_ETH,
865 .of_match = designware_eth_ids,
866 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
867 .bind = designware_eth_bind,
868 .probe = designware_eth_probe,
869 .remove = designware_eth_remove,
870 .ops = &designware_eth_ops,
871 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
872 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
873 .flags = DM_FLAG_ALLOC_PRIV_DMA,
874 };
875
876 static struct pci_device_id supported[] = {
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
878 { }
879 };
880
881 U_BOOT_PCI_DEVICE(eth_designware, supported);
882 #endif
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