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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/net/dm9000x.c
2 dm9000.c: Version 1.2 12/15/2003
4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
7 * SPDX-License-Identifier: GPL-2.0+
9 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
11 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
12 06/22/2001 Support DM9801 progrmming
13 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
14 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
15 R17 = (R17 & 0xfff0) | NF + 3
16 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
17 R17 = (R17 & 0xfff0) | NF
19 v1.00 modify by simon 2001.9.5
20 change for kernel 2.4.x
22 v1.1 11/09/2001 fix force mode bug
24 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
26 Added tx/rx 32 bit mode.
27 Cleaned up for kernel merge.
29 --------------------------------------
31 12/15/2003 Initial port to u-boot by
32 Sascha Hauer <saschahauer@web.de>
34 06/03/2008 Remy Bohmer <linux@bohmer.net>
35 - Fixed the driver to work with DM9000A.
36 (check on ISR receive status bit before reading the
37 FIFO as described in DM9000 programming guide and
39 - Added autodetect of databus width.
40 - Made debug code compile again.
41 - Adapt eth_send such that it matches the DM9000*
42 application notes. Needed to make it work properly
44 - Adapted reset procedure to match DM9000 application
45 notes (i.e. double reset)
46 - some minor code cleanups
47 These changes are tested with DM9000{A,EP,E} together
48 with a 200MHz Atmel AT91SAM9261 core
50 TODO: external MII is not functional, only internal at the moment.
61 /* Board/System/Debug information/definition ---------------- */
63 /* #define CONFIG_DM9000_DEBUG */
65 #ifdef CONFIG_DM9000_DEBUG
66 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
67 #define DM9000_DMP_PACKET(func,packet,length) \
70 printf("%s: length: %d\n", func, length); \
71 for (i = 0; i < length; i++) { \
73 printf("\n%s: %02x: ", func, i); \
74 printf("%02x ", ((unsigned char *) packet)[i]); \
78 #define DM9000_DBG(fmt,args...)
79 #define DM9000_DMP_PACKET(func,packet,length)
82 /* Structure/enum declaration ------------------------------- */
83 typedef struct board_info
{
84 u32 runt_length_counter
; /* counter: RX length < 64byte */
85 u32 long_length_counter
; /* counter: RX length > 1514byte */
86 u32 reset_counter
; /* counter: RESET */
87 u32 reset_tx_timeout
; /* RESET caused by TX Timeout */
88 u32 reset_rx_status
; /* RESET caused by RX Statsus wrong */
93 u8 device_wait_reset
; /* device state */
94 unsigned char srom
[128];
95 void (*outblk
)(volatile void *data_ptr
, int count
);
96 void (*inblk
)(void *data_ptr
, int count
);
97 void (*rx_status
)(u16
*RxStatus
, u16
*RxLen
);
98 struct eth_device netdev
;
100 static board_info_t dm9000_info
;
103 /* function declaration ------------------------------------- */
104 static int dm9000_probe(void);
105 static u16
dm9000_phy_read(int);
106 static void dm9000_phy_write(int, u16
);
107 static u8
DM9000_ior(int);
108 static void DM9000_iow(int reg
, u8 value
);
110 /* DM9000 network board routine ---------------------------- */
111 #ifndef CONFIG_DM9000_BYTE_SWAPPED
112 #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
113 #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
114 #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
115 #define DM9000_inb(r) readb((volatile u8 *)(r))
116 #define DM9000_inw(r) readw((volatile u16 *)(r))
117 #define DM9000_inl(r) readl((volatile u32 *)(r))
119 #define DM9000_outb(d, r) __raw_writeb(d, r)
120 #define DM9000_outw(d, r) __raw_writew(d, r)
121 #define DM9000_outl(d, r) __raw_writel(d, r)
122 #define DM9000_inb(r) __raw_readb(r)
123 #define DM9000_inw(r) __raw_readw(r)
124 #define DM9000_inl(r) __raw_readl(r)
127 #ifdef CONFIG_DM9000_DEBUG
132 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
133 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
134 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
135 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
136 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
137 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
138 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
139 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR
));
144 static void dm9000_outblk_8bit(volatile void *data_ptr
, int count
)
147 for (i
= 0; i
< count
; i
++)
148 DM9000_outb((((u8
*) data_ptr
)[i
] & 0xff), DM9000_DATA
);
151 static void dm9000_outblk_16bit(volatile void *data_ptr
, int count
)
154 u32 tmplen
= (count
+ 1) / 2;
156 for (i
= 0; i
< tmplen
; i
++)
157 DM9000_outw(((u16
*) data_ptr
)[i
], DM9000_DATA
);
159 static void dm9000_outblk_32bit(volatile void *data_ptr
, int count
)
162 u32 tmplen
= (count
+ 3) / 4;
164 for (i
= 0; i
< tmplen
; i
++)
165 DM9000_outl(((u32
*) data_ptr
)[i
], DM9000_DATA
);
168 static void dm9000_inblk_8bit(void *data_ptr
, int count
)
171 for (i
= 0; i
< count
; i
++)
172 ((u8
*) data_ptr
)[i
] = DM9000_inb(DM9000_DATA
);
175 static void dm9000_inblk_16bit(void *data_ptr
, int count
)
178 u32 tmplen
= (count
+ 1) / 2;
180 for (i
= 0; i
< tmplen
; i
++)
181 ((u16
*) data_ptr
)[i
] = DM9000_inw(DM9000_DATA
);
183 static void dm9000_inblk_32bit(void *data_ptr
, int count
)
186 u32 tmplen
= (count
+ 3) / 4;
188 for (i
= 0; i
< tmplen
; i
++)
189 ((u32
*) data_ptr
)[i
] = DM9000_inl(DM9000_DATA
);
192 static void dm9000_rx_status_32bit(u16
*RxStatus
, u16
*RxLen
)
196 DM9000_outb(DM9000_MRCMD
, DM9000_IO
);
198 tmpdata
= DM9000_inl(DM9000_DATA
);
199 *RxStatus
= __le16_to_cpu(tmpdata
);
200 *RxLen
= __le16_to_cpu(tmpdata
>> 16);
203 static void dm9000_rx_status_16bit(u16
*RxStatus
, u16
*RxLen
)
205 DM9000_outb(DM9000_MRCMD
, DM9000_IO
);
207 *RxStatus
= __le16_to_cpu(DM9000_inw(DM9000_DATA
));
208 *RxLen
= __le16_to_cpu(DM9000_inw(DM9000_DATA
));
211 static void dm9000_rx_status_8bit(u16
*RxStatus
, u16
*RxLen
)
213 DM9000_outb(DM9000_MRCMD
, DM9000_IO
);
216 __le16_to_cpu(DM9000_inb(DM9000_DATA
) +
217 (DM9000_inb(DM9000_DATA
) << 8));
219 __le16_to_cpu(DM9000_inb(DM9000_DATA
) +
220 (DM9000_inb(DM9000_DATA
) << 8));
224 Search DM9000 board, allocate space and register it
230 id_val
= DM9000_ior(DM9000_VIDL
);
231 id_val
|= DM9000_ior(DM9000_VIDH
) << 8;
232 id_val
|= DM9000_ior(DM9000_PIDL
) << 16;
233 id_val
|= DM9000_ior(DM9000_PIDH
) << 24;
234 if (id_val
== DM9000_ID
) {
235 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE
,
239 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
240 CONFIG_DM9000_BASE
, id_val
);
245 /* General Purpose dm9000 reset routine */
249 DM9000_DBG("resetting DM9000\n");
252 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
254 /* DEBUG: Make all GPIO0 outputs, all others inputs */
255 DM9000_iow(DM9000_GPCR
, GPCR_GPIO0_OUT
);
256 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
257 DM9000_iow(DM9000_GPR
, 0);
258 /* Step 2: Software reset */
259 DM9000_iow(DM9000_NCR
, (NCR_LBK_INT_MAC
| NCR_RST
));
262 DM9000_DBG("resetting the DM9000, 1st reset\n");
263 udelay(25); /* Wait at least 20 us */
264 } while (DM9000_ior(DM9000_NCR
) & 1);
266 DM9000_iow(DM9000_NCR
, 0);
267 DM9000_iow(DM9000_NCR
, (NCR_LBK_INT_MAC
| NCR_RST
)); /* Issue a second reset */
270 DM9000_DBG("resetting the DM9000, 2nd reset\n");
271 udelay(25); /* Wait at least 20 us */
272 } while (DM9000_ior(DM9000_NCR
) & 1);
274 /* Check whether the ethernet controller is present */
275 if ((DM9000_ior(DM9000_PIDL
) != 0x0) ||
276 (DM9000_ior(DM9000_PIDH
) != 0x90))
277 printf("ERROR: resetting DM9000 -> not responding\n");
280 /* Initialize dm9000 board
282 static int dm9000_init(struct eth_device
*dev
, bd_t
*bd
)
286 struct board_info
*db
= &dm9000_info
;
288 DM9000_DBG("%s\n", __func__
);
293 if (dm9000_probe() < 0)
296 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
297 io_mode
= DM9000_ior(DM9000_ISR
) >> 6;
300 case 0x0: /* 16-bit mode */
301 printf("DM9000: running in 16 bit mode\n");
302 db
->outblk
= dm9000_outblk_16bit
;
303 db
->inblk
= dm9000_inblk_16bit
;
304 db
->rx_status
= dm9000_rx_status_16bit
;
306 case 0x01: /* 32-bit mode */
307 printf("DM9000: running in 32 bit mode\n");
308 db
->outblk
= dm9000_outblk_32bit
;
309 db
->inblk
= dm9000_inblk_32bit
;
310 db
->rx_status
= dm9000_rx_status_32bit
;
312 case 0x02: /* 8 bit mode */
313 printf("DM9000: running in 8 bit mode\n");
314 db
->outblk
= dm9000_outblk_8bit
;
315 db
->inblk
= dm9000_inblk_8bit
;
316 db
->rx_status
= dm9000_rx_status_8bit
;
319 /* Assume 8 bit mode, will probably not work anyway */
320 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode
);
321 db
->outblk
= dm9000_outblk_8bit
;
322 db
->inblk
= dm9000_inblk_8bit
;
323 db
->rx_status
= dm9000_rx_status_8bit
;
327 /* Program operating register, only internal phy supported */
328 DM9000_iow(DM9000_NCR
, 0x0);
329 /* TX Polling clear */
330 DM9000_iow(DM9000_TCR
, 0);
331 /* Less 3Kb, 200us */
332 DM9000_iow(DM9000_BPTR
, BPTR_BPHW(3) | BPTR_JPT_600US
);
333 /* Flow Control : High/Low Water */
334 DM9000_iow(DM9000_FCTR
, FCTR_HWOT(3) | FCTR_LWOT(8));
335 /* SH FIXME: This looks strange! Flow Control */
336 DM9000_iow(DM9000_FCR
, 0x0);
338 DM9000_iow(DM9000_SMCR
, 0);
339 /* clear TX status */
340 DM9000_iow(DM9000_NSR
, NSR_WAKEST
| NSR_TX2END
| NSR_TX1END
);
341 /* Clear interrupt status */
342 DM9000_iow(DM9000_ISR
, ISR_ROOS
| ISR_ROS
| ISR_PTS
| ISR_PRS
);
344 printf("MAC: %pM\n", dev
->enetaddr
);
346 /* fill device MAC address registers */
347 for (i
= 0, oft
= DM9000_PAR
; i
< 6; i
++, oft
++)
348 DM9000_iow(oft
, dev
->enetaddr
[i
]);
349 for (i
= 0, oft
= 0x16; i
< 8; i
++, oft
++)
350 DM9000_iow(oft
, 0xff);
352 /* read back mac, just to be sure */
353 for (i
= 0, oft
= 0x10; i
< 6; i
++, oft
++)
354 DM9000_DBG("%02x:", DM9000_ior(oft
));
357 /* Activate DM9000 */
359 DM9000_iow(DM9000_RCR
, RCR_DIS_LONG
| RCR_DIS_CRC
| RCR_RXEN
);
360 /* Enable TX/RX interrupt mask */
361 DM9000_iow(DM9000_IMR
, IMR_PAR
);
364 while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
368 printf("could not establish link\n");
373 /* see what we've got */
374 lnk
= dm9000_phy_read(17) >> 12;
375 printf("operating at ");
378 printf("10M half duplex ");
381 printf("10M full duplex ");
384 printf("100M half duplex ");
387 printf("100M full duplex ");
390 printf("unknown: %d ", lnk
);
398 Hardware start transmission.
399 Send a packet to media from the upper layer.
401 static int dm9000_send(struct eth_device
*netdev
, void *packet
, int length
)
404 struct board_info
*db
= &dm9000_info
;
406 DM9000_DMP_PACKET(__func__
, packet
, length
);
408 DM9000_iow(DM9000_ISR
, IMR_PTM
); /* Clear Tx bit in ISR */
410 /* Move data to DM9000 TX RAM */
411 DM9000_outb(DM9000_MWCMD
, DM9000_IO
); /* Prepare for TX-data */
413 /* push the data to the TX-fifo */
414 (db
->outblk
)(packet
, length
);
416 /* Set TX length to DM9000 */
417 DM9000_iow(DM9000_TXPLL
, length
& 0xff);
418 DM9000_iow(DM9000_TXPLH
, (length
>> 8) & 0xff);
420 /* Issue TX polling command */
421 DM9000_iow(DM9000_TCR
, TCR_TXREQ
); /* Cleared after TX complete */
423 /* wait for end of transmission */
424 tmo
= get_timer(0) + 5 * CONFIG_SYS_HZ
;
425 while ( !(DM9000_ior(DM9000_NSR
) & (NSR_TX1END
| NSR_TX2END
)) ||
426 !(DM9000_ior(DM9000_ISR
) & IMR_PTM
) ) {
427 if (get_timer(0) >= tmo
) {
428 printf("transmission timeout\n");
432 DM9000_iow(DM9000_ISR
, IMR_PTM
); /* Clear Tx bit in ISR */
434 DM9000_DBG("transmit done\n\n");
440 The interface is stopped when it is brought.
442 static void dm9000_halt(struct eth_device
*netdev
)
444 DM9000_DBG("%s\n", __func__
);
447 dm9000_phy_write(0, 0x8000); /* PHY RESET */
448 DM9000_iow(DM9000_GPR
, 0x01); /* Power-Down PHY */
449 DM9000_iow(DM9000_IMR
, 0x80); /* Disable all interrupt */
450 DM9000_iow(DM9000_RCR
, 0x00); /* Disable RX */
454 Received a packet and pass to upper layer
456 static int dm9000_rx(struct eth_device
*netdev
)
458 u8 rxbyte
, *rdptr
= (u8
*) NetRxPackets
[0];
459 u16 RxStatus
, RxLen
= 0;
460 struct board_info
*db
= &dm9000_info
;
462 /* Check packet ready or not, we must check
463 the ISR status first for DM9000A */
464 if (!(DM9000_ior(DM9000_ISR
) & 0x01)) /* Rx-ISR bit must be set. */
467 DM9000_iow(DM9000_ISR
, 0x01); /* clear PR status latched in bit 0 */
469 /* There is _at least_ 1 package in the fifo, read them all */
471 DM9000_ior(DM9000_MRCMDX
); /* Dummy read */
473 /* Get most updated data,
474 only look at bits 0:1, See application notes DM9000 */
475 rxbyte
= DM9000_inb(DM9000_DATA
) & 0x03;
477 /* Status check: this byte must be 0 or 1 */
478 if (rxbyte
> DM9000_PKT_RDY
) {
479 DM9000_iow(DM9000_RCR
, 0x00); /* Stop Device */
480 DM9000_iow(DM9000_ISR
, 0x80); /* Stop INT request */
481 printf("DM9000 error: status check fail: 0x%x\n",
486 if (rxbyte
!= DM9000_PKT_RDY
)
487 return 0; /* No packet received, ignore */
489 DM9000_DBG("receiving packet\n");
491 /* A packet ready now & Get status/length */
492 (db
->rx_status
)(&RxStatus
, &RxLen
);
494 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus
, RxLen
);
496 /* Move data from DM9000 */
497 /* Read received packet from RX SRAM */
498 (db
->inblk
)(rdptr
, RxLen
);
500 if ((RxStatus
& 0xbf00) || (RxLen
< 0x40)
501 || (RxLen
> DM9000_PKT_MAX
)) {
502 if (RxStatus
& 0x100) {
503 printf("rx fifo error\n");
505 if (RxStatus
& 0x200) {
506 printf("rx crc error\n");
508 if (RxStatus
& 0x8000) {
509 printf("rx length error\n");
511 if (RxLen
> DM9000_PKT_MAX
) {
512 printf("rx length too big\n");
516 DM9000_DMP_PACKET(__func__
, rdptr
, RxLen
);
518 DM9000_DBG("passing packet to upper layer\n");
519 NetReceive(NetRxPackets
[0], RxLen
);
526 Read a word data from SROM
528 #if !defined(CONFIG_DM9000_NO_SROM)
529 void dm9000_read_srom_word(int offset
, u8
*to
)
531 DM9000_iow(DM9000_EPAR
, offset
);
532 DM9000_iow(DM9000_EPCR
, 0x4);
534 DM9000_iow(DM9000_EPCR
, 0x0);
535 to
[0] = DM9000_ior(DM9000_EPDRL
);
536 to
[1] = DM9000_ior(DM9000_EPDRH
);
539 void dm9000_write_srom_word(int offset
, u16 val
)
541 DM9000_iow(DM9000_EPAR
, offset
);
542 DM9000_iow(DM9000_EPDRH
, ((val
>> 8) & 0xff));
543 DM9000_iow(DM9000_EPDRL
, (val
& 0xff));
544 DM9000_iow(DM9000_EPCR
, 0x12);
546 DM9000_iow(DM9000_EPCR
, 0);
550 static void dm9000_get_enetaddr(struct eth_device
*dev
)
552 #if !defined(CONFIG_DM9000_NO_SROM)
554 for (i
= 0; i
< 3; i
++)
555 dm9000_read_srom_word(i
, dev
->enetaddr
+ (2 * i
));
560 Read a byte from I/O port
565 DM9000_outb(reg
, DM9000_IO
);
566 return DM9000_inb(DM9000_DATA
);
570 Write a byte to I/O port
573 DM9000_iow(int reg
, u8 value
)
575 DM9000_outb(reg
, DM9000_IO
);
576 DM9000_outb(value
, DM9000_DATA
);
580 Read a word from phyxcer
583 dm9000_phy_read(int reg
)
587 /* Fill the phyxcer register into REG_0C */
588 DM9000_iow(DM9000_EPAR
, DM9000_PHY
| reg
);
589 DM9000_iow(DM9000_EPCR
, 0xc); /* Issue phyxcer read command */
590 udelay(100); /* Wait read complete */
591 DM9000_iow(DM9000_EPCR
, 0x0); /* Clear phyxcer read command */
592 val
= (DM9000_ior(DM9000_EPDRH
) << 8) | DM9000_ior(DM9000_EPDRL
);
594 /* The read data keeps on REG_0D & REG_0E */
595 DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg
, val
);
600 Write a word to phyxcer
603 dm9000_phy_write(int reg
, u16 value
)
606 /* Fill the phyxcer register into REG_0C */
607 DM9000_iow(DM9000_EPAR
, DM9000_PHY
| reg
);
609 /* Fill the written data into REG_0D & REG_0E */
610 DM9000_iow(DM9000_EPDRL
, (value
& 0xff));
611 DM9000_iow(DM9000_EPDRH
, ((value
>> 8) & 0xff));
612 DM9000_iow(DM9000_EPCR
, 0xa); /* Issue phyxcer write command */
613 udelay(500); /* Wait write complete */
614 DM9000_iow(DM9000_EPCR
, 0x0); /* Clear phyxcer write command */
615 DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg
, value
);
618 int dm9000_initialize(bd_t
*bis
)
620 struct eth_device
*dev
= &(dm9000_info
.netdev
);
622 /* Load MAC address from EEPROM */
623 dm9000_get_enetaddr(dev
);
625 dev
->init
= dm9000_init
;
626 dev
->halt
= dm9000_halt
;
627 dev
->send
= dm9000_send
;
628 dev
->recv
= dm9000_rx
;
629 sprintf(dev
->name
, "dm9000");