2 * Dave Ethernet Controller driver
4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #ifndef CONFIG_DNET_AUTONEG_TIMEOUT
14 #define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
19 #include <linux/mii.h>
27 struct dnet_registers
*regs
;
28 const struct device
*dev
;
29 struct eth_device netdev
;
30 unsigned short phy_addr
;
33 /* get struct dnet_device from given struct netdev */
34 #define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
36 /* function for reading internal MAC register */
37 u16
dnet_readw_mac(struct dnet_device
*dnet
, u16 reg
)
42 writel(reg
, &dnet
->regs
->MACREG_ADDR
);
44 /* since a read/write op to the MAC is very slow,
45 * we must wait before reading the data */
48 /* read data read from the MAC register */
49 data_read
= readl(&dnet
->regs
->MACREG_DATA
);
55 /* function for writing internal MAC register */
56 void dnet_writew_mac(struct dnet_device
*dnet
, u16 reg
, u16 val
)
58 /* load data to write */
59 writel(val
, &dnet
->regs
->MACREG_DATA
);
62 writel(reg
| DNET_INTERNAL_WRITE
, &dnet
->regs
->MACREG_ADDR
);
64 /* since a read/write op to the MAC is very slow,
65 * we must wait before exiting */
69 static void dnet_mdio_write(struct dnet_device
*dnet
, u8 reg
, u16 value
)
73 debug(DRIVERNAME
"dnet_mdio_write %02x:%02x <- %04x\n",
74 dnet
->phy_addr
, reg
, value
);
76 while (!(dnet_readw_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
) &
77 DNET_INTERNAL_GMII_MNG_CMD_FIN
))
80 /* prepare for a write operation */
83 /* only 5 bits allowed for register offset */
86 /* prepare reg_value for a write */
87 tmp
|= (dnet
->phy_addr
<< 8);
90 /* write data to write first */
91 dnet_writew_mac(dnet
, DNET_INTERNAL_GMII_MNG_DAT_REG
, value
);
93 /* write control word */
94 dnet_writew_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
, tmp
);
96 while (!(dnet_readw_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
) &
97 DNET_INTERNAL_GMII_MNG_CMD_FIN
))
101 static u16
dnet_mdio_read(struct dnet_device
*dnet
, u8 reg
)
105 while (!(dnet_readw_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
) &
106 DNET_INTERNAL_GMII_MNG_CMD_FIN
))
109 /* only 5 bits allowed for register offset*/
112 /* prepare reg_value for a read */
113 value
= (dnet
->phy_addr
<< 8);
116 /* write control word */
117 dnet_writew_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
, value
);
119 /* wait for end of transfer */
120 while (!(dnet_readw_mac(dnet
, DNET_INTERNAL_GMII_MNG_CTL_REG
) &
121 DNET_INTERNAL_GMII_MNG_CMD_FIN
))
124 value
= dnet_readw_mac(dnet
, DNET_INTERNAL_GMII_MNG_DAT_REG
);
126 debug(DRIVERNAME
"dnet_mdio_read %02x:%02x <- %04x\n",
127 dnet
->phy_addr
, reg
, value
);
132 static int dnet_send(struct eth_device
*netdev
, volatile void *packet
,
135 struct dnet_device
*dnet
= to_dnet(netdev
);
140 debug(DRIVERNAME
"[%s] Sending %u bytes\n", __func__
, length
);
142 /* frame size (words) */
143 len
= (length
+ 3) >> 2;
145 bufp
= (unsigned int *) (((u32
)packet
) & 0xFFFFFFFC);
146 wrsz
= (u32
)length
+ 3;
147 wrsz
+= ((u32
)packet
) & 0x3;
149 tx_cmd
= ((((unsigned int)(packet
)) & 0x03) << 16) | (u32
)length
;
151 /* check if there is enough room for the current frame */
152 if (wrsz
< (DNET_FIFO_SIZE
- readl(&dnet
->regs
->TX_FIFO_WCNT
))) {
153 for (i
= 0; i
< wrsz
; i
++)
154 writel(*bufp
++, &dnet
->regs
->TX_DATA_FIFO
);
156 * inform MAC that a packet's written and ready
159 writel(tx_cmd
, &dnet
->regs
->TX_LEN_FIFO
);
161 printf(DRIVERNAME
"No free space (actual %d, required %d "
162 "(words))\n", DNET_FIFO_SIZE
-
163 readl(&dnet
->regs
->TX_FIFO_WCNT
), wrsz
);
166 /* No one cares anyway */
171 static int dnet_recv(struct eth_device
*netdev
)
173 struct dnet_device
*dnet
= to_dnet(netdev
);
174 unsigned int *data_ptr
;
175 int pkt_len
, poll
, i
;
178 debug("Waiting for pkt (polling)\n");
180 while ((readl(&dnet
->regs
->RX_FIFO_WCNT
) >> 16) == 0) {
181 udelay(10); /* wait 10 usec */
183 return 0; /* no pkt available */
186 cmd_word
= readl(&dnet
->regs
->RX_LEN_FIFO
);
187 pkt_len
= cmd_word
& 0xFFFF;
189 debug("Got pkt with size %d bytes\n", pkt_len
);
191 if (cmd_word
& 0xDF180000)
192 printf("%s packet receive error %x\n", __func__
, cmd_word
);
194 data_ptr
= (unsigned int *) NetRxPackets
[0];
196 for (i
= 0; i
< (pkt_len
+ 3) >> 2; i
++)
197 *data_ptr
++ = readl(&dnet
->regs
->RX_DATA_FIFO
);
199 NetReceive(NetRxPackets
[0], pkt_len
+ 5); /* ok + 5 ?? */
204 static void dnet_set_hwaddr(struct eth_device
*netdev
)
206 struct dnet_device
*dnet
= to_dnet(netdev
);
209 tmp
= cpu_to_be16(*((u16
*)netdev
->enetaddr
));
210 dnet_writew_mac(dnet
, DNET_INTERNAL_MAC_ADDR_0_REG
, tmp
);
211 tmp
= cpu_to_be16(*((u16
*)(netdev
->enetaddr
+ 2)));
212 dnet_writew_mac(dnet
, DNET_INTERNAL_MAC_ADDR_1_REG
, tmp
);
213 tmp
= cpu_to_be16(*((u16
*)(netdev
->enetaddr
+ 4)));
214 dnet_writew_mac(dnet
, DNET_INTERNAL_MAC_ADDR_2_REG
, tmp
);
217 static void dnet_phy_reset(struct dnet_device
*dnet
)
219 struct eth_device
*netdev
= &dnet
->netdev
;
223 adv
= ADVERTISE_CSMA
| ADVERTISE_ALL
;
224 dnet_mdio_write(dnet
, MII_ADVERTISE
, adv
);
225 printf("%s: Starting autonegotiation...\n", netdev
->name
);
226 dnet_mdio_write(dnet
, MII_BMCR
, (BMCR_ANENABLE
229 for (i
= 0; i
< CONFIG_DNET_AUTONEG_TIMEOUT
/ 100; i
++) {
230 status
= dnet_mdio_read(dnet
, MII_BMSR
);
231 if (status
& BMSR_ANEGCOMPLETE
)
236 if (status
& BMSR_ANEGCOMPLETE
)
237 printf("%s: Autonegotiation complete\n", netdev
->name
);
239 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
240 netdev
->name
, status
);
243 static int dnet_phy_init(struct dnet_device
*dnet
)
245 struct eth_device
*netdev
= &dnet
->netdev
;
246 u16 phy_id
, status
, adv
, lpa
;
247 int media
, speed
, duplex
;
252 for (i
= 0; i
< 32; i
++) {
254 phy_id
= dnet_mdio_read(dnet
, MII_PHYSID1
);
255 if (phy_id
!= 0xffff) {
257 printf("Found PHY at address %d PHYID (%04x:%04x)\n",
259 dnet_mdio_read(dnet
, MII_PHYSID2
));
264 /* Check if the PHY is up to snuff... */
265 phy_id
= dnet_mdio_read(dnet
, MII_PHYSID1
);
266 if (phy_id
== 0xffff) {
267 printf("%s: No PHY present\n", netdev
->name
);
271 status
= dnet_mdio_read(dnet
, MII_BMSR
);
272 if (!(status
& BMSR_LSTATUS
)) {
273 /* Try to re-negotiate if we don't have link already. */
274 dnet_phy_reset(dnet
);
276 for (i
= 0; i
< CONFIG_DNET_AUTONEG_TIMEOUT
/ 100; i
++) {
277 status
= dnet_mdio_read(dnet
, MII_BMSR
);
278 if (status
& BMSR_LSTATUS
)
284 if (!(status
& BMSR_LSTATUS
)) {
285 printf("%s: link down (status: 0x%04x)\n",
286 netdev
->name
, status
);
289 adv
= dnet_mdio_read(dnet
, MII_ADVERTISE
);
290 lpa
= dnet_mdio_read(dnet
, MII_LPA
);
291 media
= mii_nway_result(lpa
& adv
);
292 speed
= (media
& (ADVERTISE_100FULL
| ADVERTISE_100HALF
)
294 duplex
= (media
& ADVERTISE_FULL
) ? 1 : 0;
295 /* 1000BaseT ethernet is not supported */
296 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
298 speed
? "100" : "10",
299 duplex
? "full" : "half",
302 ctl_reg
= dnet_readw_mac(dnet
, DNET_INTERNAL_RXTX_CONTROL_REG
);
305 ctl_reg
&= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP
);
307 ctl_reg
|= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP
;
309 dnet_writew_mac(dnet
, DNET_INTERNAL_RXTX_CONTROL_REG
, ctl_reg
);
315 static int dnet_init(struct eth_device
*netdev
, bd_t
*bd
)
317 struct dnet_device
*dnet
= to_dnet(netdev
);
321 * dnet_halt should have been called at some point before now,
322 * so we'll assume the controller is idle.
325 /* set hardware address */
326 dnet_set_hwaddr(netdev
);
328 if (dnet_phy_init(dnet
) < 0)
331 /* flush rx/tx fifos */
332 writel(DNET_SYS_CTL_RXFIFOFLUSH
| DNET_SYS_CTL_TXFIFOFLUSH
,
333 &dnet
->regs
->SYS_CTL
);
335 writel(0, &dnet
->regs
->SYS_CTL
);
337 config
= dnet_readw_mac(dnet
, DNET_INTERNAL_RXTX_CONTROL_REG
);
339 config
|= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE
|
340 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST
|
341 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL
|
342 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS
;
344 dnet_writew_mac(dnet
, DNET_INTERNAL_RXTX_CONTROL_REG
, config
);
346 /* Enable TX and RX */
347 dnet_writew_mac(dnet
, DNET_INTERNAL_MODE_REG
,
348 DNET_INTERNAL_MODE_RXEN
| DNET_INTERNAL_MODE_TXEN
);
353 static void dnet_halt(struct eth_device
*netdev
)
355 struct dnet_device
*dnet
= to_dnet(netdev
);
357 /* Disable TX and RX */
358 dnet_writew_mac(dnet
, DNET_INTERNAL_MODE_REG
, 0);
361 int dnet_eth_initialize(int id
, void *regs
, unsigned int phy_addr
)
363 struct dnet_device
*dnet
;
364 struct eth_device
*netdev
;
365 unsigned int dev_capa
;
367 dnet
= malloc(sizeof(struct dnet_device
));
369 printf("Error: Failed to allocate memory for DNET%d\n", id
);
372 memset(dnet
, 0, sizeof(struct dnet_device
));
374 netdev
= &dnet
->netdev
;
376 dnet
->regs
= (struct dnet_registers
*)regs
;
377 dnet
->phy_addr
= phy_addr
;
379 sprintf(netdev
->name
, "dnet%d", id
);
380 netdev
->init
= dnet_init
;
381 netdev
->halt
= dnet_halt
;
382 netdev
->send
= dnet_send
;
383 netdev
->recv
= dnet_recv
;
385 dev_capa
= readl(&dnet
->regs
->VERCAPS
) & 0xFFFF;
386 debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev
->name
,
387 (dev_capa
& DNET_HAS_MDIO
) ? "" : "no ",
388 (dev_capa
& DNET_HAS_IRQ
) ? "" : "no ",
389 (dev_capa
& DNET_HAS_GIGABIT
) ? "" : "no ",
390 (dev_capa
& DNET_HAS_DMA
) ? "" : "no ");
392 eth_register(netdev
);