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[thirdparty/linux.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
32 #include <net/dsa.h>
33
34 #include "chip.h"
35 #include "global1.h"
36 #include "global2.h"
37 #include "hwtstamp.h"
38 #include "phy.h"
39 #include "port.h"
40 #include "ptp.h"
41 #include "serdes.h"
42 #include "smi.h"
43
44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
45 {
46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
47 dev_err(chip->dev, "Switch registers lock not held!\n");
48 dump_stack();
49 }
50 }
51
52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
53 {
54 int err;
55
56 assert_reg_lock(chip);
57
58 err = mv88e6xxx_smi_read(chip, addr, reg, val);
59 if (err)
60 return err;
61
62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
63 addr, reg, *val);
64
65 return 0;
66 }
67
68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
69 {
70 int err;
71
72 assert_reg_lock(chip);
73
74 err = mv88e6xxx_smi_write(chip, addr, reg, val);
75 if (err)
76 return err;
77
78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
79 addr, reg, val);
80
81 return 0;
82 }
83
84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
85 u16 mask, u16 val)
86 {
87 u16 data;
88 int err;
89 int i;
90
91 /* There's no bus specific operation to wait for a mask */
92 for (i = 0; i < 16; i++) {
93 err = mv88e6xxx_read(chip, addr, reg, &data);
94 if (err)
95 return err;
96
97 if ((data & mask) == val)
98 return 0;
99
100 usleep_range(1000, 2000);
101 }
102
103 dev_err(chip->dev, "Timeout while waiting for switch\n");
104 return -ETIMEDOUT;
105 }
106
107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
108 int bit, int val)
109 {
110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
111 val ? BIT(bit) : 0x0000);
112 }
113
114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
115 {
116 struct mv88e6xxx_mdio_bus *mdio_bus;
117
118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
119 list);
120 if (!mdio_bus)
121 return NULL;
122
123 return mdio_bus->bus;
124 }
125
126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
127 {
128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
129 unsigned int n = d->hwirq;
130
131 chip->g1_irq.masked |= (1 << n);
132 }
133
134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
135 {
136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
137 unsigned int n = d->hwirq;
138
139 chip->g1_irq.masked &= ~(1 << n);
140 }
141
142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
143 {
144 unsigned int nhandled = 0;
145 unsigned int sub_irq;
146 unsigned int n;
147 u16 reg;
148 u16 ctl1;
149 int err;
150
151 mv88e6xxx_reg_lock(chip);
152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
153 mv88e6xxx_reg_unlock(chip);
154
155 if (err)
156 goto out;
157
158 do {
159 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
160 if (reg & (1 << n)) {
161 sub_irq = irq_find_mapping(chip->g1_irq.domain,
162 n);
163 handle_nested_irq(sub_irq);
164 ++nhandled;
165 }
166 }
167
168 mv88e6xxx_reg_lock(chip);
169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
170 if (err)
171 goto unlock;
172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
173 unlock:
174 mv88e6xxx_reg_unlock(chip);
175 if (err)
176 goto out;
177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
178 } while (reg & ctl1);
179
180 out:
181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
182 }
183
184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
185 {
186 struct mv88e6xxx_chip *chip = dev_id;
187
188 return mv88e6xxx_g1_irq_thread_work(chip);
189 }
190
191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
192 {
193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
194
195 mv88e6xxx_reg_lock(chip);
196 }
197
198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
199 {
200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
202 u16 reg;
203 int err;
204
205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
206 if (err)
207 goto out;
208
209 reg &= ~mask;
210 reg |= (~chip->g1_irq.masked & mask);
211
212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
213 if (err)
214 goto out;
215
216 out:
217 mv88e6xxx_reg_unlock(chip);
218 }
219
220 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
221 .name = "mv88e6xxx-g1",
222 .irq_mask = mv88e6xxx_g1_irq_mask,
223 .irq_unmask = mv88e6xxx_g1_irq_unmask,
224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
226 };
227
228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
229 unsigned int irq,
230 irq_hw_number_t hwirq)
231 {
232 struct mv88e6xxx_chip *chip = d->host_data;
233
234 irq_set_chip_data(irq, d->host_data);
235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
236 irq_set_noprobe(irq);
237
238 return 0;
239 }
240
241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
242 .map = mv88e6xxx_g1_irq_domain_map,
243 .xlate = irq_domain_xlate_twocell,
244 };
245
246 /* To be called with reg_lock held */
247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
248 {
249 int irq, virq;
250 u16 mask;
251
252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
255
256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
257 virq = irq_find_mapping(chip->g1_irq.domain, irq);
258 irq_dispose_mapping(virq);
259 }
260
261 irq_domain_remove(chip->g1_irq.domain);
262 }
263
264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
265 {
266 /*
267 * free_irq must be called without reg_lock taken because the irq
268 * handler takes this lock, too.
269 */
270 free_irq(chip->irq, chip);
271
272 mv88e6xxx_reg_lock(chip);
273 mv88e6xxx_g1_irq_free_common(chip);
274 mv88e6xxx_reg_unlock(chip);
275 }
276
277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
278 {
279 int err, irq, virq;
280 u16 reg, mask;
281
282 chip->g1_irq.nirqs = chip->info->g1_irqs;
283 chip->g1_irq.domain = irq_domain_add_simple(
284 NULL, chip->g1_irq.nirqs, 0,
285 &mv88e6xxx_g1_irq_domain_ops, chip);
286 if (!chip->g1_irq.domain)
287 return -ENOMEM;
288
289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
290 irq_create_mapping(chip->g1_irq.domain, irq);
291
292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
293 chip->g1_irq.masked = ~0;
294
295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
296 if (err)
297 goto out_mapping;
298
299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
300
301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
302 if (err)
303 goto out_disable;
304
305 /* Reading the interrupt status clears (most of) them */
306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
307 if (err)
308 goto out_disable;
309
310 return 0;
311
312 out_disable:
313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
315
316 out_mapping:
317 for (irq = 0; irq < 16; irq++) {
318 virq = irq_find_mapping(chip->g1_irq.domain, irq);
319 irq_dispose_mapping(virq);
320 }
321
322 irq_domain_remove(chip->g1_irq.domain);
323
324 return err;
325 }
326
327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
328 {
329 static struct lock_class_key lock_key;
330 static struct lock_class_key request_key;
331 int err;
332
333 err = mv88e6xxx_g1_irq_setup_common(chip);
334 if (err)
335 return err;
336
337 /* These lock classes tells lockdep that global 1 irqs are in
338 * a different category than their parent GPIO, so it won't
339 * report false recursion.
340 */
341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
342
343 snprintf(chip->irq_name, sizeof(chip->irq_name),
344 "mv88e6xxx-%s", dev_name(chip->dev));
345
346 mv88e6xxx_reg_unlock(chip);
347 err = request_threaded_irq(chip->irq, NULL,
348 mv88e6xxx_g1_irq_thread_fn,
349 IRQF_ONESHOT | IRQF_SHARED,
350 chip->irq_name, chip);
351 mv88e6xxx_reg_lock(chip);
352 if (err)
353 mv88e6xxx_g1_irq_free_common(chip);
354
355 return err;
356 }
357
358 static void mv88e6xxx_irq_poll(struct kthread_work *work)
359 {
360 struct mv88e6xxx_chip *chip = container_of(work,
361 struct mv88e6xxx_chip,
362 irq_poll_work.work);
363 mv88e6xxx_g1_irq_thread_work(chip);
364
365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
366 msecs_to_jiffies(100));
367 }
368
369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
370 {
371 int err;
372
373 err = mv88e6xxx_g1_irq_setup_common(chip);
374 if (err)
375 return err;
376
377 kthread_init_delayed_work(&chip->irq_poll_work,
378 mv88e6xxx_irq_poll);
379
380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
381 if (IS_ERR(chip->kworker))
382 return PTR_ERR(chip->kworker);
383
384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
385 msecs_to_jiffies(100));
386
387 return 0;
388 }
389
390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
391 {
392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
393 kthread_destroy_worker(chip->kworker);
394
395 mv88e6xxx_reg_lock(chip);
396 mv88e6xxx_g1_irq_free_common(chip);
397 mv88e6xxx_reg_unlock(chip);
398 }
399
400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
401 int port, phy_interface_t interface)
402 {
403 int err;
404
405 if (chip->info->ops->port_set_rgmii_delay) {
406 err = chip->info->ops->port_set_rgmii_delay(chip, port,
407 interface);
408 if (err && err != -EOPNOTSUPP)
409 return err;
410 }
411
412 if (chip->info->ops->port_set_cmode) {
413 err = chip->info->ops->port_set_cmode(chip, port,
414 interface);
415 if (err && err != -EOPNOTSUPP)
416 return err;
417 }
418
419 return 0;
420 }
421
422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
423 int link, int speed, int duplex, int pause,
424 phy_interface_t mode)
425 {
426 int err;
427
428 if (!chip->info->ops->port_set_link)
429 return 0;
430
431 /* Port's MAC control must not be changed unless the link is down */
432 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
433 if (err)
434 return err;
435
436 if (chip->info->ops->port_set_speed_duplex) {
437 err = chip->info->ops->port_set_speed_duplex(chip, port,
438 speed, duplex);
439 if (err && err != -EOPNOTSUPP)
440 goto restore_link;
441 }
442
443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
444 mode = chip->info->ops->port_max_speed_mode(port);
445
446 if (chip->info->ops->port_set_pause) {
447 err = chip->info->ops->port_set_pause(chip, port, pause);
448 if (err)
449 goto restore_link;
450 }
451
452 err = mv88e6xxx_port_config_interface(chip, port, mode);
453 restore_link:
454 if (chip->info->ops->port_set_link(chip, port, link))
455 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
456
457 return err;
458 }
459
460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
461 {
462 struct mv88e6xxx_chip *chip = ds->priv;
463
464 return port < chip->info->num_internal_phys;
465 }
466
467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
468 {
469 u16 reg;
470 int err;
471
472 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
473 if (err) {
474 dev_err(chip->dev,
475 "p%d: %s: failed to read port status\n",
476 port, __func__);
477 return err;
478 }
479
480 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
481 }
482
483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
484 struct phylink_link_state *state)
485 {
486 struct mv88e6xxx_chip *chip = ds->priv;
487 u8 lane;
488 int err;
489
490 mv88e6xxx_reg_lock(chip);
491 lane = mv88e6xxx_serdes_get_lane(chip, port);
492 if (lane && chip->info->ops->serdes_pcs_get_state)
493 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
494 state);
495 else
496 err = -EOPNOTSUPP;
497 mv88e6xxx_reg_unlock(chip);
498
499 return err;
500 }
501
502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
503 unsigned int mode,
504 phy_interface_t interface,
505 const unsigned long *advertise)
506 {
507 const struct mv88e6xxx_ops *ops = chip->info->ops;
508 u8 lane;
509
510 if (ops->serdes_pcs_config) {
511 lane = mv88e6xxx_serdes_get_lane(chip, port);
512 if (lane)
513 return ops->serdes_pcs_config(chip, port, lane, mode,
514 interface, advertise);
515 }
516
517 return 0;
518 }
519
520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
521 {
522 struct mv88e6xxx_chip *chip = ds->priv;
523 const struct mv88e6xxx_ops *ops;
524 int err = 0;
525 u8 lane;
526
527 ops = chip->info->ops;
528
529 if (ops->serdes_pcs_an_restart) {
530 mv88e6xxx_reg_lock(chip);
531 lane = mv88e6xxx_serdes_get_lane(chip, port);
532 if (lane)
533 err = ops->serdes_pcs_an_restart(chip, port, lane);
534 mv88e6xxx_reg_unlock(chip);
535
536 if (err)
537 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
538 }
539 }
540
541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
542 unsigned int mode,
543 int speed, int duplex)
544 {
545 const struct mv88e6xxx_ops *ops = chip->info->ops;
546 u8 lane;
547
548 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
549 lane = mv88e6xxx_serdes_get_lane(chip, port);
550 if (lane)
551 return ops->serdes_pcs_link_up(chip, port, lane,
552 speed, duplex);
553 }
554
555 return 0;
556 }
557
558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
559 unsigned long *mask,
560 struct phylink_link_state *state)
561 {
562 if (!phy_interface_mode_is_8023z(state->interface)) {
563 /* 10M and 100M are only supported in non-802.3z mode */
564 phylink_set(mask, 10baseT_Half);
565 phylink_set(mask, 10baseT_Full);
566 phylink_set(mask, 100baseT_Half);
567 phylink_set(mask, 100baseT_Full);
568 }
569 }
570
571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
572 unsigned long *mask,
573 struct phylink_link_state *state)
574 {
575 /* FIXME: if the port is in 1000Base-X mode, then it only supports
576 * 1000M FD speeds. In this case, CMODE will indicate 5.
577 */
578 phylink_set(mask, 1000baseT_Full);
579 phylink_set(mask, 1000baseX_Full);
580
581 mv88e6065_phylink_validate(chip, port, mask, state);
582 }
583
584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
585 unsigned long *mask,
586 struct phylink_link_state *state)
587 {
588 if (port >= 5)
589 phylink_set(mask, 2500baseX_Full);
590
591 /* No ethtool bits for 200Mbps */
592 phylink_set(mask, 1000baseT_Full);
593 phylink_set(mask, 1000baseX_Full);
594
595 mv88e6065_phylink_validate(chip, port, mask, state);
596 }
597
598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
599 unsigned long *mask,
600 struct phylink_link_state *state)
601 {
602 /* No ethtool bits for 200Mbps */
603 phylink_set(mask, 1000baseT_Full);
604 phylink_set(mask, 1000baseX_Full);
605
606 mv88e6065_phylink_validate(chip, port, mask, state);
607 }
608
609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
610 unsigned long *mask,
611 struct phylink_link_state *state)
612 {
613 if (port >= 9) {
614 phylink_set(mask, 2500baseX_Full);
615 phylink_set(mask, 2500baseT_Full);
616 }
617
618 /* No ethtool bits for 200Mbps */
619 phylink_set(mask, 1000baseT_Full);
620 phylink_set(mask, 1000baseX_Full);
621
622 mv88e6065_phylink_validate(chip, port, mask, state);
623 }
624
625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
626 unsigned long *mask,
627 struct phylink_link_state *state)
628 {
629 if (port >= 9) {
630 phylink_set(mask, 10000baseT_Full);
631 phylink_set(mask, 10000baseKR_Full);
632 }
633
634 mv88e6390_phylink_validate(chip, port, mask, state);
635 }
636
637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
638 unsigned long *supported,
639 struct phylink_link_state *state)
640 {
641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
642 struct mv88e6xxx_chip *chip = ds->priv;
643
644 /* Allow all the expected bits */
645 phylink_set(mask, Autoneg);
646 phylink_set(mask, Pause);
647 phylink_set_port_modes(mask);
648
649 if (chip->info->ops->phylink_validate)
650 chip->info->ops->phylink_validate(chip, port, mask, state);
651
652 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
653 bitmap_and(state->advertising, state->advertising, mask,
654 __ETHTOOL_LINK_MODE_MASK_NBITS);
655
656 /* We can only operate at 2500BaseX or 1000BaseX. If requested
657 * to advertise both, only report advertising at 2500BaseX.
658 */
659 phylink_helper_basex_speed(state);
660 }
661
662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
663 unsigned int mode,
664 const struct phylink_link_state *state)
665 {
666 struct mv88e6xxx_chip *chip = ds->priv;
667 int err;
668
669 /* FIXME: is this the correct test? If we're in fixed mode on an
670 * internal port, why should we process this any different from
671 * PHY mode? On the other hand, the port may be automedia between
672 * an internal PHY and the serdes...
673 */
674 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
675 return;
676
677 mv88e6xxx_reg_lock(chip);
678 /* FIXME: should we force the link down here - but if we do, how
679 * do we restore the link force/unforce state? The driver layering
680 * gets in the way.
681 */
682 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
683 if (err && err != -EOPNOTSUPP)
684 goto err_unlock;
685
686 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
687 state->advertising);
688 /* FIXME: we should restart negotiation if something changed - which
689 * is something we get if we convert to using phylinks PCS operations.
690 */
691 if (err > 0)
692 err = 0;
693
694 err_unlock:
695 mv88e6xxx_reg_unlock(chip);
696
697 if (err && err != -EOPNOTSUPP)
698 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
699 }
700
701 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
702 unsigned int mode,
703 phy_interface_t interface)
704 {
705 struct mv88e6xxx_chip *chip = ds->priv;
706 const struct mv88e6xxx_ops *ops;
707 int err = 0;
708
709 ops = chip->info->ops;
710
711 mv88e6xxx_reg_lock(chip);
712 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
713 mode == MLO_AN_FIXED) && ops->port_set_link)
714 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
715 mv88e6xxx_reg_unlock(chip);
716
717 if (err)
718 dev_err(chip->dev,
719 "p%d: failed to force MAC link down\n", port);
720 }
721
722 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
723 unsigned int mode, phy_interface_t interface,
724 struct phy_device *phydev,
725 int speed, int duplex,
726 bool tx_pause, bool rx_pause)
727 {
728 struct mv88e6xxx_chip *chip = ds->priv;
729 const struct mv88e6xxx_ops *ops;
730 int err = 0;
731
732 ops = chip->info->ops;
733
734 mv88e6xxx_reg_lock(chip);
735 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
736 /* FIXME: for an automedia port, should we force the link
737 * down here - what if the link comes up due to "other" media
738 * while we're bringing the port up, how is the exclusivity
739 * handled in the Marvell hardware? E.g. port 2 on 88E6390
740 * shared between internal PHY and Serdes.
741 */
742 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
743 duplex);
744 if (err)
745 goto error;
746
747 if (ops->port_set_speed_duplex) {
748 err = ops->port_set_speed_duplex(chip, port,
749 speed, duplex);
750 if (err && err != -EOPNOTSUPP)
751 goto error;
752 }
753
754 if (ops->port_set_link)
755 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
756 }
757 error:
758 mv88e6xxx_reg_unlock(chip);
759
760 if (err && err != -EOPNOTSUPP)
761 dev_err(ds->dev,
762 "p%d: failed to configure MAC link up\n", port);
763 }
764
765 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
766 {
767 if (!chip->info->ops->stats_snapshot)
768 return -EOPNOTSUPP;
769
770 return chip->info->ops->stats_snapshot(chip, port);
771 }
772
773 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
774 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
775 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
776 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
777 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
778 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
779 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
780 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
781 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
782 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
783 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
784 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
785 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
786 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
787 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
788 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
789 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
790 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
791 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
792 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
793 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
794 { "single", 4, 0x14, STATS_TYPE_BANK0, },
795 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
796 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
797 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
798 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
799 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
800 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
801 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
802 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
803 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
804 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
805 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
806 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
807 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
808 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
809 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
810 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
811 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
812 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
813 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
814 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
815 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
816 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
817 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
818 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
819 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
820 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
821 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
822 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
823 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
824 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
825 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
826 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
827 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
828 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
829 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
830 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
831 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
832 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
833 };
834
835 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
836 struct mv88e6xxx_hw_stat *s,
837 int port, u16 bank1_select,
838 u16 histogram)
839 {
840 u32 low;
841 u32 high = 0;
842 u16 reg = 0;
843 int err;
844 u64 value;
845
846 switch (s->type) {
847 case STATS_TYPE_PORT:
848 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
849 if (err)
850 return U64_MAX;
851
852 low = reg;
853 if (s->size == 4) {
854 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
855 if (err)
856 return U64_MAX;
857 low |= ((u32)reg) << 16;
858 }
859 break;
860 case STATS_TYPE_BANK1:
861 reg = bank1_select;
862 /* fall through */
863 case STATS_TYPE_BANK0:
864 reg |= s->reg | histogram;
865 mv88e6xxx_g1_stats_read(chip, reg, &low);
866 if (s->size == 8)
867 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
868 break;
869 default:
870 return U64_MAX;
871 }
872 value = (((u64)high) << 32) | low;
873 return value;
874 }
875
876 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
877 uint8_t *data, int types)
878 {
879 struct mv88e6xxx_hw_stat *stat;
880 int i, j;
881
882 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
883 stat = &mv88e6xxx_hw_stats[i];
884 if (stat->type & types) {
885 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
886 ETH_GSTRING_LEN);
887 j++;
888 }
889 }
890
891 return j;
892 }
893
894 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
895 uint8_t *data)
896 {
897 return mv88e6xxx_stats_get_strings(chip, data,
898 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
899 }
900
901 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
902 uint8_t *data)
903 {
904 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
905 }
906
907 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
908 uint8_t *data)
909 {
910 return mv88e6xxx_stats_get_strings(chip, data,
911 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
912 }
913
914 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
915 "atu_member_violation",
916 "atu_miss_violation",
917 "atu_full_violation",
918 "vtu_member_violation",
919 "vtu_miss_violation",
920 };
921
922 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
923 {
924 unsigned int i;
925
926 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
927 strlcpy(data + i * ETH_GSTRING_LEN,
928 mv88e6xxx_atu_vtu_stats_strings[i],
929 ETH_GSTRING_LEN);
930 }
931
932 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
933 u32 stringset, uint8_t *data)
934 {
935 struct mv88e6xxx_chip *chip = ds->priv;
936 int count = 0;
937
938 if (stringset != ETH_SS_STATS)
939 return;
940
941 mv88e6xxx_reg_lock(chip);
942
943 if (chip->info->ops->stats_get_strings)
944 count = chip->info->ops->stats_get_strings(chip, data);
945
946 if (chip->info->ops->serdes_get_strings) {
947 data += count * ETH_GSTRING_LEN;
948 count = chip->info->ops->serdes_get_strings(chip, port, data);
949 }
950
951 data += count * ETH_GSTRING_LEN;
952 mv88e6xxx_atu_vtu_get_strings(data);
953
954 mv88e6xxx_reg_unlock(chip);
955 }
956
957 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
958 int types)
959 {
960 struct mv88e6xxx_hw_stat *stat;
961 int i, j;
962
963 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
964 stat = &mv88e6xxx_hw_stats[i];
965 if (stat->type & types)
966 j++;
967 }
968 return j;
969 }
970
971 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
972 {
973 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
974 STATS_TYPE_PORT);
975 }
976
977 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
978 {
979 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
980 }
981
982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
983 {
984 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
985 STATS_TYPE_BANK1);
986 }
987
988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
989 {
990 struct mv88e6xxx_chip *chip = ds->priv;
991 int serdes_count = 0;
992 int count = 0;
993
994 if (sset != ETH_SS_STATS)
995 return 0;
996
997 mv88e6xxx_reg_lock(chip);
998 if (chip->info->ops->stats_get_sset_count)
999 count = chip->info->ops->stats_get_sset_count(chip);
1000 if (count < 0)
1001 goto out;
1002
1003 if (chip->info->ops->serdes_get_sset_count)
1004 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1005 port);
1006 if (serdes_count < 0) {
1007 count = serdes_count;
1008 goto out;
1009 }
1010 count += serdes_count;
1011 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1012
1013 out:
1014 mv88e6xxx_reg_unlock(chip);
1015
1016 return count;
1017 }
1018
1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1020 uint64_t *data, int types,
1021 u16 bank1_select, u16 histogram)
1022 {
1023 struct mv88e6xxx_hw_stat *stat;
1024 int i, j;
1025
1026 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1027 stat = &mv88e6xxx_hw_stats[i];
1028 if (stat->type & types) {
1029 mv88e6xxx_reg_lock(chip);
1030 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1031 bank1_select,
1032 histogram);
1033 mv88e6xxx_reg_unlock(chip);
1034
1035 j++;
1036 }
1037 }
1038 return j;
1039 }
1040
1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1042 uint64_t *data)
1043 {
1044 return mv88e6xxx_stats_get_stats(chip, port, data,
1045 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1046 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1047 }
1048
1049 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1050 uint64_t *data)
1051 {
1052 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1053 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1054 }
1055
1056 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1057 uint64_t *data)
1058 {
1059 return mv88e6xxx_stats_get_stats(chip, port, data,
1060 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1061 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1062 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1063 }
1064
1065 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1066 uint64_t *data)
1067 {
1068 return mv88e6xxx_stats_get_stats(chip, port, data,
1069 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1070 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1071 0);
1072 }
1073
1074 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1075 uint64_t *data)
1076 {
1077 *data++ = chip->ports[port].atu_member_violation;
1078 *data++ = chip->ports[port].atu_miss_violation;
1079 *data++ = chip->ports[port].atu_full_violation;
1080 *data++ = chip->ports[port].vtu_member_violation;
1081 *data++ = chip->ports[port].vtu_miss_violation;
1082 }
1083
1084 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1085 uint64_t *data)
1086 {
1087 int count = 0;
1088
1089 if (chip->info->ops->stats_get_stats)
1090 count = chip->info->ops->stats_get_stats(chip, port, data);
1091
1092 mv88e6xxx_reg_lock(chip);
1093 if (chip->info->ops->serdes_get_stats) {
1094 data += count;
1095 count = chip->info->ops->serdes_get_stats(chip, port, data);
1096 }
1097 data += count;
1098 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1099 mv88e6xxx_reg_unlock(chip);
1100 }
1101
1102 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1103 uint64_t *data)
1104 {
1105 struct mv88e6xxx_chip *chip = ds->priv;
1106 int ret;
1107
1108 mv88e6xxx_reg_lock(chip);
1109
1110 ret = mv88e6xxx_stats_snapshot(chip, port);
1111 mv88e6xxx_reg_unlock(chip);
1112
1113 if (ret < 0)
1114 return;
1115
1116 mv88e6xxx_get_stats(chip, port, data);
1117
1118 }
1119
1120 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1121 {
1122 struct mv88e6xxx_chip *chip = ds->priv;
1123 int len;
1124
1125 len = 32 * sizeof(u16);
1126 if (chip->info->ops->serdes_get_regs_len)
1127 len += chip->info->ops->serdes_get_regs_len(chip, port);
1128
1129 return len;
1130 }
1131
1132 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1133 struct ethtool_regs *regs, void *_p)
1134 {
1135 struct mv88e6xxx_chip *chip = ds->priv;
1136 int err;
1137 u16 reg;
1138 u16 *p = _p;
1139 int i;
1140
1141 regs->version = chip->info->prod_num;
1142
1143 memset(p, 0xff, 32 * sizeof(u16));
1144
1145 mv88e6xxx_reg_lock(chip);
1146
1147 for (i = 0; i < 32; i++) {
1148
1149 err = mv88e6xxx_port_read(chip, port, i, &reg);
1150 if (!err)
1151 p[i] = reg;
1152 }
1153
1154 if (chip->info->ops->serdes_get_regs)
1155 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1156
1157 mv88e6xxx_reg_unlock(chip);
1158 }
1159
1160 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1161 struct ethtool_eee *e)
1162 {
1163 /* Nothing to do on the port's MAC */
1164 return 0;
1165 }
1166
1167 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1168 struct ethtool_eee *e)
1169 {
1170 /* Nothing to do on the port's MAC */
1171 return 0;
1172 }
1173
1174 /* Mask of the local ports allowed to receive frames from a given fabric port */
1175 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1176 {
1177 struct dsa_switch *ds = chip->ds;
1178 struct dsa_switch_tree *dst = ds->dst;
1179 struct net_device *br;
1180 struct dsa_port *dp;
1181 bool found = false;
1182 u16 pvlan;
1183
1184 list_for_each_entry(dp, &dst->ports, list) {
1185 if (dp->ds->index == dev && dp->index == port) {
1186 found = true;
1187 break;
1188 }
1189 }
1190
1191 /* Prevent frames from unknown switch or port */
1192 if (!found)
1193 return 0;
1194
1195 /* Frames from DSA links and CPU ports can egress any local port */
1196 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1197 return mv88e6xxx_port_mask(chip);
1198
1199 br = dp->bridge_dev;
1200 pvlan = 0;
1201
1202 /* Frames from user ports can egress any local DSA links and CPU ports,
1203 * as well as any local member of their bridge group.
1204 */
1205 list_for_each_entry(dp, &dst->ports, list)
1206 if (dp->ds == ds &&
1207 (dp->type == DSA_PORT_TYPE_CPU ||
1208 dp->type == DSA_PORT_TYPE_DSA ||
1209 (br && dp->bridge_dev == br)))
1210 pvlan |= BIT(dp->index);
1211
1212 return pvlan;
1213 }
1214
1215 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1216 {
1217 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1218
1219 /* prevent frames from going back out of the port they came in on */
1220 output_ports &= ~BIT(port);
1221
1222 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1223 }
1224
1225 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1226 u8 state)
1227 {
1228 struct mv88e6xxx_chip *chip = ds->priv;
1229 int err;
1230
1231 mv88e6xxx_reg_lock(chip);
1232 err = mv88e6xxx_port_set_state(chip, port, state);
1233 mv88e6xxx_reg_unlock(chip);
1234
1235 if (err)
1236 dev_err(ds->dev, "p%d: failed to update state\n", port);
1237 }
1238
1239 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1240 {
1241 int err;
1242
1243 if (chip->info->ops->ieee_pri_map) {
1244 err = chip->info->ops->ieee_pri_map(chip);
1245 if (err)
1246 return err;
1247 }
1248
1249 if (chip->info->ops->ip_pri_map) {
1250 err = chip->info->ops->ip_pri_map(chip);
1251 if (err)
1252 return err;
1253 }
1254
1255 return 0;
1256 }
1257
1258 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1259 {
1260 struct dsa_switch *ds = chip->ds;
1261 int target, port;
1262 int err;
1263
1264 if (!chip->info->global2_addr)
1265 return 0;
1266
1267 /* Initialize the routing port to the 32 possible target devices */
1268 for (target = 0; target < 32; target++) {
1269 port = dsa_routing_port(ds, target);
1270 if (port == ds->num_ports)
1271 port = 0x1f;
1272
1273 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1274 if (err)
1275 return err;
1276 }
1277
1278 if (chip->info->ops->set_cascade_port) {
1279 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1280 err = chip->info->ops->set_cascade_port(chip, port);
1281 if (err)
1282 return err;
1283 }
1284
1285 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1286 if (err)
1287 return err;
1288
1289 return 0;
1290 }
1291
1292 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1293 {
1294 /* Clear all trunk masks and mapping */
1295 if (chip->info->global2_addr)
1296 return mv88e6xxx_g2_trunk_clear(chip);
1297
1298 return 0;
1299 }
1300
1301 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1302 {
1303 if (chip->info->ops->rmu_disable)
1304 return chip->info->ops->rmu_disable(chip);
1305
1306 return 0;
1307 }
1308
1309 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1310 {
1311 if (chip->info->ops->pot_clear)
1312 return chip->info->ops->pot_clear(chip);
1313
1314 return 0;
1315 }
1316
1317 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1318 {
1319 if (chip->info->ops->mgmt_rsvd2cpu)
1320 return chip->info->ops->mgmt_rsvd2cpu(chip);
1321
1322 return 0;
1323 }
1324
1325 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1326 {
1327 int err;
1328
1329 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1330 if (err)
1331 return err;
1332
1333 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1334 if (err)
1335 return err;
1336
1337 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1338 }
1339
1340 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1341 {
1342 int port;
1343 int err;
1344
1345 if (!chip->info->ops->irl_init_all)
1346 return 0;
1347
1348 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1349 /* Disable ingress rate limiting by resetting all per port
1350 * ingress rate limit resources to their initial state.
1351 */
1352 err = chip->info->ops->irl_init_all(chip, port);
1353 if (err)
1354 return err;
1355 }
1356
1357 return 0;
1358 }
1359
1360 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1361 {
1362 if (chip->info->ops->set_switch_mac) {
1363 u8 addr[ETH_ALEN];
1364
1365 eth_random_addr(addr);
1366
1367 return chip->info->ops->set_switch_mac(chip, addr);
1368 }
1369
1370 return 0;
1371 }
1372
1373 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1374 {
1375 u16 pvlan = 0;
1376
1377 if (!mv88e6xxx_has_pvt(chip))
1378 return 0;
1379
1380 /* Skip the local source device, which uses in-chip port VLAN */
1381 if (dev != chip->ds->index)
1382 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1383
1384 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1385 }
1386
1387 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1388 {
1389 int dev, port;
1390 int err;
1391
1392 if (!mv88e6xxx_has_pvt(chip))
1393 return 0;
1394
1395 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1396 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1397 */
1398 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1399 if (err)
1400 return err;
1401
1402 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1403 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1404 err = mv88e6xxx_pvt_map(chip, dev, port);
1405 if (err)
1406 return err;
1407 }
1408 }
1409
1410 return 0;
1411 }
1412
1413 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1414 {
1415 struct mv88e6xxx_chip *chip = ds->priv;
1416 int err;
1417
1418 mv88e6xxx_reg_lock(chip);
1419 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1420 mv88e6xxx_reg_unlock(chip);
1421
1422 if (err)
1423 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1424 }
1425
1426 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1427 {
1428 if (!chip->info->max_vid)
1429 return 0;
1430
1431 return mv88e6xxx_g1_vtu_flush(chip);
1432 }
1433
1434 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1435 struct mv88e6xxx_vtu_entry *entry)
1436 {
1437 if (!chip->info->ops->vtu_getnext)
1438 return -EOPNOTSUPP;
1439
1440 return chip->info->ops->vtu_getnext(chip, entry);
1441 }
1442
1443 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1444 struct mv88e6xxx_vtu_entry *entry)
1445 {
1446 if (!chip->info->ops->vtu_loadpurge)
1447 return -EOPNOTSUPP;
1448
1449 return chip->info->ops->vtu_loadpurge(chip, entry);
1450 }
1451
1452 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1453 {
1454 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1455 struct mv88e6xxx_vtu_entry vlan;
1456 int i, err;
1457
1458 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1459
1460 /* Set every FID bit used by the (un)bridged ports */
1461 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1462 err = mv88e6xxx_port_get_fid(chip, i, fid);
1463 if (err)
1464 return err;
1465
1466 set_bit(*fid, fid_bitmap);
1467 }
1468
1469 /* Set every FID bit used by the VLAN entries */
1470 vlan.vid = chip->info->max_vid;
1471 vlan.valid = false;
1472
1473 do {
1474 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1475 if (err)
1476 return err;
1477
1478 if (!vlan.valid)
1479 break;
1480
1481 set_bit(vlan.fid, fid_bitmap);
1482 } while (vlan.vid < chip->info->max_vid);
1483
1484 /* The reset value 0x000 is used to indicate that multiple address
1485 * databases are not needed. Return the next positive available.
1486 */
1487 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1488 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1489 return -ENOSPC;
1490
1491 /* Clear the database */
1492 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1493 }
1494
1495 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
1496 {
1497 if (chip->info->ops->atu_get_hash)
1498 return chip->info->ops->atu_get_hash(chip, hash);
1499
1500 return -EOPNOTSUPP;
1501 }
1502
1503 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
1504 {
1505 if (chip->info->ops->atu_set_hash)
1506 return chip->info->ops->atu_set_hash(chip, hash);
1507
1508 return -EOPNOTSUPP;
1509 }
1510
1511 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1512 u16 vid_begin, u16 vid_end)
1513 {
1514 struct mv88e6xxx_chip *chip = ds->priv;
1515 struct mv88e6xxx_vtu_entry vlan;
1516 int i, err;
1517
1518 /* DSA and CPU ports have to be members of multiple vlans */
1519 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1520 return 0;
1521
1522 if (!vid_begin)
1523 return -EOPNOTSUPP;
1524
1525 vlan.vid = vid_begin - 1;
1526 vlan.valid = false;
1527
1528 do {
1529 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1530 if (err)
1531 return err;
1532
1533 if (!vlan.valid)
1534 break;
1535
1536 if (vlan.vid > vid_end)
1537 break;
1538
1539 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1540 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1541 continue;
1542
1543 if (!dsa_to_port(ds, i)->slave)
1544 continue;
1545
1546 if (vlan.member[i] ==
1547 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1548 continue;
1549
1550 if (dsa_to_port(ds, i)->bridge_dev ==
1551 dsa_to_port(ds, port)->bridge_dev)
1552 break; /* same bridge, check next VLAN */
1553
1554 if (!dsa_to_port(ds, i)->bridge_dev)
1555 continue;
1556
1557 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1558 port, vlan.vid, i,
1559 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1560 return -EOPNOTSUPP;
1561 }
1562 } while (vlan.vid < vid_end);
1563
1564 return 0;
1565 }
1566
1567 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1568 bool vlan_filtering)
1569 {
1570 struct mv88e6xxx_chip *chip = ds->priv;
1571 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1572 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1573 int err;
1574
1575 if (!chip->info->max_vid)
1576 return -EOPNOTSUPP;
1577
1578 mv88e6xxx_reg_lock(chip);
1579 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1580 mv88e6xxx_reg_unlock(chip);
1581
1582 return err;
1583 }
1584
1585 static int
1586 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1587 const struct switchdev_obj_port_vlan *vlan)
1588 {
1589 struct mv88e6xxx_chip *chip = ds->priv;
1590 int err;
1591
1592 if (!chip->info->max_vid)
1593 return -EOPNOTSUPP;
1594
1595 /* If the requested port doesn't belong to the same bridge as the VLAN
1596 * members, do not support it (yet) and fallback to software VLAN.
1597 */
1598 mv88e6xxx_reg_lock(chip);
1599 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1600 vlan->vid_end);
1601 mv88e6xxx_reg_unlock(chip);
1602
1603 /* We don't need any dynamic resource from the kernel (yet),
1604 * so skip the prepare phase.
1605 */
1606 return err;
1607 }
1608
1609 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1610 const unsigned char *addr, u16 vid,
1611 u8 state)
1612 {
1613 struct mv88e6xxx_atu_entry entry;
1614 struct mv88e6xxx_vtu_entry vlan;
1615 u16 fid;
1616 int err;
1617
1618 /* Null VLAN ID corresponds to the port private database */
1619 if (vid == 0) {
1620 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1621 if (err)
1622 return err;
1623 } else {
1624 vlan.vid = vid - 1;
1625 vlan.valid = false;
1626
1627 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1628 if (err)
1629 return err;
1630
1631 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1632 if (vlan.vid != vid || !vlan.valid)
1633 return -EOPNOTSUPP;
1634
1635 fid = vlan.fid;
1636 }
1637
1638 entry.state = 0;
1639 ether_addr_copy(entry.mac, addr);
1640 eth_addr_dec(entry.mac);
1641
1642 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1643 if (err)
1644 return err;
1645
1646 /* Initialize a fresh ATU entry if it isn't found */
1647 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1648 memset(&entry, 0, sizeof(entry));
1649 ether_addr_copy(entry.mac, addr);
1650 }
1651
1652 /* Purge the ATU entry only if no port is using it anymore */
1653 if (!state) {
1654 entry.portvec &= ~BIT(port);
1655 if (!entry.portvec)
1656 entry.state = 0;
1657 } else {
1658 entry.portvec |= BIT(port);
1659 entry.state = state;
1660 }
1661
1662 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1663 }
1664
1665 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1666 const struct mv88e6xxx_policy *policy)
1667 {
1668 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1669 enum mv88e6xxx_policy_action action = policy->action;
1670 const u8 *addr = policy->addr;
1671 u16 vid = policy->vid;
1672 u8 state;
1673 int err;
1674 int id;
1675
1676 if (!chip->info->ops->port_set_policy)
1677 return -EOPNOTSUPP;
1678
1679 switch (mapping) {
1680 case MV88E6XXX_POLICY_MAPPING_DA:
1681 case MV88E6XXX_POLICY_MAPPING_SA:
1682 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1683 state = 0; /* Dissociate the port and address */
1684 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1685 is_multicast_ether_addr(addr))
1686 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1687 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1688 is_unicast_ether_addr(addr))
1689 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1690 else
1691 return -EOPNOTSUPP;
1692
1693 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1694 state);
1695 if (err)
1696 return err;
1697 break;
1698 default:
1699 return -EOPNOTSUPP;
1700 }
1701
1702 /* Skip the port's policy clearing if the mapping is still in use */
1703 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1704 idr_for_each_entry(&chip->policies, policy, id)
1705 if (policy->port == port &&
1706 policy->mapping == mapping &&
1707 policy->action != action)
1708 return 0;
1709
1710 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1711 }
1712
1713 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1714 struct ethtool_rx_flow_spec *fs)
1715 {
1716 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1717 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1718 enum mv88e6xxx_policy_mapping mapping;
1719 enum mv88e6xxx_policy_action action;
1720 struct mv88e6xxx_policy *policy;
1721 u16 vid = 0;
1722 u8 *addr;
1723 int err;
1724 int id;
1725
1726 if (fs->location != RX_CLS_LOC_ANY)
1727 return -EINVAL;
1728
1729 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1730 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1731 else
1732 return -EOPNOTSUPP;
1733
1734 switch (fs->flow_type & ~FLOW_EXT) {
1735 case ETHER_FLOW:
1736 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1737 is_zero_ether_addr(mac_mask->h_source)) {
1738 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1739 addr = mac_entry->h_dest;
1740 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1741 !is_zero_ether_addr(mac_mask->h_source)) {
1742 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1743 addr = mac_entry->h_source;
1744 } else {
1745 /* Cannot support DA and SA mapping in the same rule */
1746 return -EOPNOTSUPP;
1747 }
1748 break;
1749 default:
1750 return -EOPNOTSUPP;
1751 }
1752
1753 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1754 if (fs->m_ext.vlan_tci != 0xffff)
1755 return -EOPNOTSUPP;
1756 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1757 }
1758
1759 idr_for_each_entry(&chip->policies, policy, id) {
1760 if (policy->port == port && policy->mapping == mapping &&
1761 policy->action == action && policy->vid == vid &&
1762 ether_addr_equal(policy->addr, addr))
1763 return -EEXIST;
1764 }
1765
1766 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1767 if (!policy)
1768 return -ENOMEM;
1769
1770 fs->location = 0;
1771 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1772 GFP_KERNEL);
1773 if (err) {
1774 devm_kfree(chip->dev, policy);
1775 return err;
1776 }
1777
1778 memcpy(&policy->fs, fs, sizeof(*fs));
1779 ether_addr_copy(policy->addr, addr);
1780 policy->mapping = mapping;
1781 policy->action = action;
1782 policy->port = port;
1783 policy->vid = vid;
1784
1785 err = mv88e6xxx_policy_apply(chip, port, policy);
1786 if (err) {
1787 idr_remove(&chip->policies, fs->location);
1788 devm_kfree(chip->dev, policy);
1789 return err;
1790 }
1791
1792 return 0;
1793 }
1794
1795 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1796 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1797 {
1798 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1799 struct mv88e6xxx_chip *chip = ds->priv;
1800 struct mv88e6xxx_policy *policy;
1801 int err;
1802 int id;
1803
1804 mv88e6xxx_reg_lock(chip);
1805
1806 switch (rxnfc->cmd) {
1807 case ETHTOOL_GRXCLSRLCNT:
1808 rxnfc->data = 0;
1809 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1810 rxnfc->rule_cnt = 0;
1811 idr_for_each_entry(&chip->policies, policy, id)
1812 if (policy->port == port)
1813 rxnfc->rule_cnt++;
1814 err = 0;
1815 break;
1816 case ETHTOOL_GRXCLSRULE:
1817 err = -ENOENT;
1818 policy = idr_find(&chip->policies, fs->location);
1819 if (policy) {
1820 memcpy(fs, &policy->fs, sizeof(*fs));
1821 err = 0;
1822 }
1823 break;
1824 case ETHTOOL_GRXCLSRLALL:
1825 rxnfc->data = 0;
1826 rxnfc->rule_cnt = 0;
1827 idr_for_each_entry(&chip->policies, policy, id)
1828 if (policy->port == port)
1829 rule_locs[rxnfc->rule_cnt++] = id;
1830 err = 0;
1831 break;
1832 default:
1833 err = -EOPNOTSUPP;
1834 break;
1835 }
1836
1837 mv88e6xxx_reg_unlock(chip);
1838
1839 return err;
1840 }
1841
1842 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1843 struct ethtool_rxnfc *rxnfc)
1844 {
1845 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1846 struct mv88e6xxx_chip *chip = ds->priv;
1847 struct mv88e6xxx_policy *policy;
1848 int err;
1849
1850 mv88e6xxx_reg_lock(chip);
1851
1852 switch (rxnfc->cmd) {
1853 case ETHTOOL_SRXCLSRLINS:
1854 err = mv88e6xxx_policy_insert(chip, port, fs);
1855 break;
1856 case ETHTOOL_SRXCLSRLDEL:
1857 err = -ENOENT;
1858 policy = idr_remove(&chip->policies, fs->location);
1859 if (policy) {
1860 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1861 err = mv88e6xxx_policy_apply(chip, port, policy);
1862 devm_kfree(chip->dev, policy);
1863 }
1864 break;
1865 default:
1866 err = -EOPNOTSUPP;
1867 break;
1868 }
1869
1870 mv88e6xxx_reg_unlock(chip);
1871
1872 return err;
1873 }
1874
1875 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1876 u16 vid)
1877 {
1878 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1879 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1880
1881 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1882 }
1883
1884 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1885 {
1886 int port;
1887 int err;
1888
1889 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1890 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1891 if (err)
1892 return err;
1893 }
1894
1895 return 0;
1896 }
1897
1898 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1899 u16 vid, u8 member, bool warn)
1900 {
1901 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1902 struct mv88e6xxx_vtu_entry vlan;
1903 int i, err;
1904
1905 if (!vid)
1906 return -EOPNOTSUPP;
1907
1908 vlan.vid = vid - 1;
1909 vlan.valid = false;
1910
1911 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1912 if (err)
1913 return err;
1914
1915 if (vlan.vid != vid || !vlan.valid) {
1916 memset(&vlan, 0, sizeof(vlan));
1917
1918 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1919 if (err)
1920 return err;
1921
1922 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1923 if (i == port)
1924 vlan.member[i] = member;
1925 else
1926 vlan.member[i] = non_member;
1927
1928 vlan.vid = vid;
1929 vlan.valid = true;
1930
1931 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1932 if (err)
1933 return err;
1934
1935 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1936 if (err)
1937 return err;
1938 } else if (vlan.member[port] != member) {
1939 vlan.member[port] = member;
1940
1941 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1942 if (err)
1943 return err;
1944 } else if (warn) {
1945 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1946 port, vid);
1947 }
1948
1949 return 0;
1950 }
1951
1952 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1953 const struct switchdev_obj_port_vlan *vlan)
1954 {
1955 struct mv88e6xxx_chip *chip = ds->priv;
1956 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1957 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1958 bool warn;
1959 u8 member;
1960 u16 vid;
1961
1962 if (!chip->info->max_vid)
1963 return;
1964
1965 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1966 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1967 else if (untagged)
1968 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1969 else
1970 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1971
1972 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
1973 * and then the CPU port. Do not warn for duplicates for the CPU port.
1974 */
1975 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
1976
1977 mv88e6xxx_reg_lock(chip);
1978
1979 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1980 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
1981 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1982 vid, untagged ? 'u' : 't');
1983
1984 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1985 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1986 vlan->vid_end);
1987
1988 mv88e6xxx_reg_unlock(chip);
1989 }
1990
1991 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
1992 int port, u16 vid)
1993 {
1994 struct mv88e6xxx_vtu_entry vlan;
1995 int i, err;
1996
1997 if (!vid)
1998 return -EOPNOTSUPP;
1999
2000 vlan.vid = vid - 1;
2001 vlan.valid = false;
2002
2003 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2004 if (err)
2005 return err;
2006
2007 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2008 * tell switchdev that this VLAN is likely handled in software.
2009 */
2010 if (vlan.vid != vid || !vlan.valid ||
2011 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2012 return -EOPNOTSUPP;
2013
2014 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2015
2016 /* keep the VLAN unless all ports are excluded */
2017 vlan.valid = false;
2018 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2019 if (vlan.member[i] !=
2020 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2021 vlan.valid = true;
2022 break;
2023 }
2024 }
2025
2026 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2027 if (err)
2028 return err;
2029
2030 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2031 }
2032
2033 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2034 const struct switchdev_obj_port_vlan *vlan)
2035 {
2036 struct mv88e6xxx_chip *chip = ds->priv;
2037 u16 pvid, vid;
2038 int err = 0;
2039
2040 if (!chip->info->max_vid)
2041 return -EOPNOTSUPP;
2042
2043 mv88e6xxx_reg_lock(chip);
2044
2045 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2046 if (err)
2047 goto unlock;
2048
2049 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2050 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2051 if (err)
2052 goto unlock;
2053
2054 if (vid == pvid) {
2055 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2056 if (err)
2057 goto unlock;
2058 }
2059 }
2060
2061 unlock:
2062 mv88e6xxx_reg_unlock(chip);
2063
2064 return err;
2065 }
2066
2067 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2068 const unsigned char *addr, u16 vid)
2069 {
2070 struct mv88e6xxx_chip *chip = ds->priv;
2071 int err;
2072
2073 mv88e6xxx_reg_lock(chip);
2074 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2075 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2076 mv88e6xxx_reg_unlock(chip);
2077
2078 return err;
2079 }
2080
2081 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2082 const unsigned char *addr, u16 vid)
2083 {
2084 struct mv88e6xxx_chip *chip = ds->priv;
2085 int err;
2086
2087 mv88e6xxx_reg_lock(chip);
2088 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2089 mv88e6xxx_reg_unlock(chip);
2090
2091 return err;
2092 }
2093
2094 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2095 u16 fid, u16 vid, int port,
2096 dsa_fdb_dump_cb_t *cb, void *data)
2097 {
2098 struct mv88e6xxx_atu_entry addr;
2099 bool is_static;
2100 int err;
2101
2102 addr.state = 0;
2103 eth_broadcast_addr(addr.mac);
2104
2105 do {
2106 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2107 if (err)
2108 return err;
2109
2110 if (!addr.state)
2111 break;
2112
2113 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2114 continue;
2115
2116 if (!is_unicast_ether_addr(addr.mac))
2117 continue;
2118
2119 is_static = (addr.state ==
2120 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2121 err = cb(addr.mac, vid, is_static, data);
2122 if (err)
2123 return err;
2124 } while (!is_broadcast_ether_addr(addr.mac));
2125
2126 return err;
2127 }
2128
2129 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2130 dsa_fdb_dump_cb_t *cb, void *data)
2131 {
2132 struct mv88e6xxx_vtu_entry vlan;
2133 u16 fid;
2134 int err;
2135
2136 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2137 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2138 if (err)
2139 return err;
2140
2141 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2142 if (err)
2143 return err;
2144
2145 /* Dump VLANs' Filtering Information Databases */
2146 vlan.vid = chip->info->max_vid;
2147 vlan.valid = false;
2148
2149 do {
2150 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2151 if (err)
2152 return err;
2153
2154 if (!vlan.valid)
2155 break;
2156
2157 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2158 cb, data);
2159 if (err)
2160 return err;
2161 } while (vlan.vid < chip->info->max_vid);
2162
2163 return err;
2164 }
2165
2166 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2167 dsa_fdb_dump_cb_t *cb, void *data)
2168 {
2169 struct mv88e6xxx_chip *chip = ds->priv;
2170 int err;
2171
2172 mv88e6xxx_reg_lock(chip);
2173 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2174 mv88e6xxx_reg_unlock(chip);
2175
2176 return err;
2177 }
2178
2179 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2180 struct net_device *br)
2181 {
2182 struct dsa_switch *ds = chip->ds;
2183 struct dsa_switch_tree *dst = ds->dst;
2184 struct dsa_port *dp;
2185 int err;
2186
2187 list_for_each_entry(dp, &dst->ports, list) {
2188 if (dp->bridge_dev == br) {
2189 if (dp->ds == ds) {
2190 /* This is a local bridge group member,
2191 * remap its Port VLAN Map.
2192 */
2193 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2194 if (err)
2195 return err;
2196 } else {
2197 /* This is an external bridge group member,
2198 * remap its cross-chip Port VLAN Table entry.
2199 */
2200 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2201 dp->index);
2202 if (err)
2203 return err;
2204 }
2205 }
2206 }
2207
2208 return 0;
2209 }
2210
2211 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2212 struct net_device *br)
2213 {
2214 struct mv88e6xxx_chip *chip = ds->priv;
2215 int err;
2216
2217 mv88e6xxx_reg_lock(chip);
2218 err = mv88e6xxx_bridge_map(chip, br);
2219 mv88e6xxx_reg_unlock(chip);
2220
2221 return err;
2222 }
2223
2224 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2225 struct net_device *br)
2226 {
2227 struct mv88e6xxx_chip *chip = ds->priv;
2228
2229 mv88e6xxx_reg_lock(chip);
2230 if (mv88e6xxx_bridge_map(chip, br) ||
2231 mv88e6xxx_port_vlan_map(chip, port))
2232 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2233 mv88e6xxx_reg_unlock(chip);
2234 }
2235
2236 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2237 int port, struct net_device *br)
2238 {
2239 struct mv88e6xxx_chip *chip = ds->priv;
2240 int err;
2241
2242 mv88e6xxx_reg_lock(chip);
2243 err = mv88e6xxx_pvt_map(chip, dev, port);
2244 mv88e6xxx_reg_unlock(chip);
2245
2246 return err;
2247 }
2248
2249 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2250 int port, struct net_device *br)
2251 {
2252 struct mv88e6xxx_chip *chip = ds->priv;
2253
2254 mv88e6xxx_reg_lock(chip);
2255 if (mv88e6xxx_pvt_map(chip, dev, port))
2256 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2257 mv88e6xxx_reg_unlock(chip);
2258 }
2259
2260 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2261 {
2262 if (chip->info->ops->reset)
2263 return chip->info->ops->reset(chip);
2264
2265 return 0;
2266 }
2267
2268 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2269 {
2270 struct gpio_desc *gpiod = chip->reset;
2271
2272 /* If there is a GPIO connected to the reset pin, toggle it */
2273 if (gpiod) {
2274 gpiod_set_value_cansleep(gpiod, 1);
2275 usleep_range(10000, 20000);
2276 gpiod_set_value_cansleep(gpiod, 0);
2277 usleep_range(10000, 20000);
2278 }
2279 }
2280
2281 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2282 {
2283 int i, err;
2284
2285 /* Set all ports to the Disabled state */
2286 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2287 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2288 if (err)
2289 return err;
2290 }
2291
2292 /* Wait for transmit queues to drain,
2293 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2294 */
2295 usleep_range(2000, 4000);
2296
2297 return 0;
2298 }
2299
2300 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2301 {
2302 int err;
2303
2304 err = mv88e6xxx_disable_ports(chip);
2305 if (err)
2306 return err;
2307
2308 mv88e6xxx_hardware_reset(chip);
2309
2310 return mv88e6xxx_software_reset(chip);
2311 }
2312
2313 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2314 enum mv88e6xxx_frame_mode frame,
2315 enum mv88e6xxx_egress_mode egress, u16 etype)
2316 {
2317 int err;
2318
2319 if (!chip->info->ops->port_set_frame_mode)
2320 return -EOPNOTSUPP;
2321
2322 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2323 if (err)
2324 return err;
2325
2326 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2327 if (err)
2328 return err;
2329
2330 if (chip->info->ops->port_set_ether_type)
2331 return chip->info->ops->port_set_ether_type(chip, port, etype);
2332
2333 return 0;
2334 }
2335
2336 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2337 {
2338 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2339 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2340 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2341 }
2342
2343 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2344 {
2345 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2346 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2347 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2348 }
2349
2350 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2351 {
2352 return mv88e6xxx_set_port_mode(chip, port,
2353 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2354 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2355 ETH_P_EDSA);
2356 }
2357
2358 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2359 {
2360 if (dsa_is_dsa_port(chip->ds, port))
2361 return mv88e6xxx_set_port_mode_dsa(chip, port);
2362
2363 if (dsa_is_user_port(chip->ds, port))
2364 return mv88e6xxx_set_port_mode_normal(chip, port);
2365
2366 /* Setup CPU port mode depending on its supported tag format */
2367 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2368 return mv88e6xxx_set_port_mode_dsa(chip, port);
2369
2370 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2371 return mv88e6xxx_set_port_mode_edsa(chip, port);
2372
2373 return -EINVAL;
2374 }
2375
2376 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2377 {
2378 bool message = dsa_is_dsa_port(chip->ds, port);
2379
2380 return mv88e6xxx_port_set_message_port(chip, port, message);
2381 }
2382
2383 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2384 {
2385 struct dsa_switch *ds = chip->ds;
2386 bool flood;
2387
2388 /* Upstream ports flood frames with unknown unicast or multicast DA */
2389 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2390 if (chip->info->ops->port_set_egress_floods)
2391 return chip->info->ops->port_set_egress_floods(chip, port,
2392 flood, flood);
2393
2394 return 0;
2395 }
2396
2397 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2398 {
2399 struct mv88e6xxx_port *mvp = dev_id;
2400 struct mv88e6xxx_chip *chip = mvp->chip;
2401 irqreturn_t ret = IRQ_NONE;
2402 int port = mvp->port;
2403 u8 lane;
2404
2405 mv88e6xxx_reg_lock(chip);
2406 lane = mv88e6xxx_serdes_get_lane(chip, port);
2407 if (lane)
2408 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2409 mv88e6xxx_reg_unlock(chip);
2410
2411 return ret;
2412 }
2413
2414 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2415 u8 lane)
2416 {
2417 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2418 unsigned int irq;
2419 int err;
2420
2421 /* Nothing to request if this SERDES port has no IRQ */
2422 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2423 if (!irq)
2424 return 0;
2425
2426 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2427 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2428
2429 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2430 mv88e6xxx_reg_unlock(chip);
2431 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2432 IRQF_ONESHOT, dev_id->serdes_irq_name,
2433 dev_id);
2434 mv88e6xxx_reg_lock(chip);
2435 if (err)
2436 return err;
2437
2438 dev_id->serdes_irq = irq;
2439
2440 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2441 }
2442
2443 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2444 u8 lane)
2445 {
2446 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2447 unsigned int irq = dev_id->serdes_irq;
2448 int err;
2449
2450 /* Nothing to free if no IRQ has been requested */
2451 if (!irq)
2452 return 0;
2453
2454 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2455
2456 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2457 mv88e6xxx_reg_unlock(chip);
2458 free_irq(irq, dev_id);
2459 mv88e6xxx_reg_lock(chip);
2460
2461 dev_id->serdes_irq = 0;
2462
2463 return err;
2464 }
2465
2466 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2467 bool on)
2468 {
2469 u8 lane;
2470 int err;
2471
2472 lane = mv88e6xxx_serdes_get_lane(chip, port);
2473 if (!lane)
2474 return 0;
2475
2476 if (on) {
2477 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2478 if (err)
2479 return err;
2480
2481 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2482 } else {
2483 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2484 if (err)
2485 return err;
2486
2487 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2488 }
2489
2490 return err;
2491 }
2492
2493 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2494 {
2495 struct dsa_switch *ds = chip->ds;
2496 int upstream_port;
2497 int err;
2498
2499 upstream_port = dsa_upstream_port(ds, port);
2500 if (chip->info->ops->port_set_upstream_port) {
2501 err = chip->info->ops->port_set_upstream_port(chip, port,
2502 upstream_port);
2503 if (err)
2504 return err;
2505 }
2506
2507 if (port == upstream_port) {
2508 if (chip->info->ops->set_cpu_port) {
2509 err = chip->info->ops->set_cpu_port(chip,
2510 upstream_port);
2511 if (err)
2512 return err;
2513 }
2514
2515 if (chip->info->ops->set_egress_port) {
2516 err = chip->info->ops->set_egress_port(chip,
2517 MV88E6XXX_EGRESS_DIR_INGRESS,
2518 upstream_port);
2519 if (err)
2520 return err;
2521
2522 err = chip->info->ops->set_egress_port(chip,
2523 MV88E6XXX_EGRESS_DIR_EGRESS,
2524 upstream_port);
2525 if (err)
2526 return err;
2527 }
2528 }
2529
2530 return 0;
2531 }
2532
2533 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2534 {
2535 struct dsa_switch *ds = chip->ds;
2536 int err;
2537 u16 reg;
2538
2539 chip->ports[port].chip = chip;
2540 chip->ports[port].port = port;
2541
2542 /* MAC Forcing register: don't force link, speed, duplex or flow control
2543 * state to any particular values on physical ports, but force the CPU
2544 * port and all DSA ports to their maximum bandwidth and full duplex.
2545 */
2546 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2547 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2548 SPEED_MAX, DUPLEX_FULL,
2549 PAUSE_OFF,
2550 PHY_INTERFACE_MODE_NA);
2551 else
2552 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2553 SPEED_UNFORCED, DUPLEX_UNFORCED,
2554 PAUSE_ON,
2555 PHY_INTERFACE_MODE_NA);
2556 if (err)
2557 return err;
2558
2559 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2560 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2561 * tunneling, determine priority by looking at 802.1p and IP
2562 * priority fields (IP prio has precedence), and set STP state
2563 * to Forwarding.
2564 *
2565 * If this is the CPU link, use DSA or EDSA tagging depending
2566 * on which tagging mode was configured.
2567 *
2568 * If this is a link to another switch, use DSA tagging mode.
2569 *
2570 * If this is the upstream port for this switch, enable
2571 * forwarding of unknown unicasts and multicasts.
2572 */
2573 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2574 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2575 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2576 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2577 if (err)
2578 return err;
2579
2580 err = mv88e6xxx_setup_port_mode(chip, port);
2581 if (err)
2582 return err;
2583
2584 err = mv88e6xxx_setup_egress_floods(chip, port);
2585 if (err)
2586 return err;
2587
2588 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2589 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2590 * untagged frames on this port, do a destination address lookup on all
2591 * received packets as usual, disable ARP mirroring and don't send a
2592 * copy of all transmitted/received frames on this port to the CPU.
2593 */
2594 err = mv88e6xxx_port_set_map_da(chip, port);
2595 if (err)
2596 return err;
2597
2598 err = mv88e6xxx_setup_upstream_port(chip, port);
2599 if (err)
2600 return err;
2601
2602 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2603 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2604 if (err)
2605 return err;
2606
2607 if (chip->info->ops->port_set_jumbo_size) {
2608 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2609 if (err)
2610 return err;
2611 }
2612
2613 /* Port Association Vector: when learning source addresses
2614 * of packets, add the address to the address database using
2615 * a port bitmap that has only the bit for this port set and
2616 * the other bits clear.
2617 */
2618 reg = 1 << port;
2619 /* Disable learning for CPU port */
2620 if (dsa_is_cpu_port(ds, port))
2621 reg = 0;
2622
2623 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2624 reg);
2625 if (err)
2626 return err;
2627
2628 /* Egress rate control 2: disable egress rate control. */
2629 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2630 0x0000);
2631 if (err)
2632 return err;
2633
2634 if (chip->info->ops->port_pause_limit) {
2635 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2636 if (err)
2637 return err;
2638 }
2639
2640 if (chip->info->ops->port_disable_learn_limit) {
2641 err = chip->info->ops->port_disable_learn_limit(chip, port);
2642 if (err)
2643 return err;
2644 }
2645
2646 if (chip->info->ops->port_disable_pri_override) {
2647 err = chip->info->ops->port_disable_pri_override(chip, port);
2648 if (err)
2649 return err;
2650 }
2651
2652 if (chip->info->ops->port_tag_remap) {
2653 err = chip->info->ops->port_tag_remap(chip, port);
2654 if (err)
2655 return err;
2656 }
2657
2658 if (chip->info->ops->port_egress_rate_limiting) {
2659 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2660 if (err)
2661 return err;
2662 }
2663
2664 if (chip->info->ops->port_setup_message_port) {
2665 err = chip->info->ops->port_setup_message_port(chip, port);
2666 if (err)
2667 return err;
2668 }
2669
2670 /* Port based VLAN map: give each port the same default address
2671 * database, and allow bidirectional communication between the
2672 * CPU and DSA port(s), and the other ports.
2673 */
2674 err = mv88e6xxx_port_set_fid(chip, port, 0);
2675 if (err)
2676 return err;
2677
2678 err = mv88e6xxx_port_vlan_map(chip, port);
2679 if (err)
2680 return err;
2681
2682 /* Default VLAN ID and priority: don't set a default VLAN
2683 * ID, and set the default packet priority to zero.
2684 */
2685 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2686 }
2687
2688 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2689 struct phy_device *phydev)
2690 {
2691 struct mv88e6xxx_chip *chip = ds->priv;
2692 int err;
2693
2694 mv88e6xxx_reg_lock(chip);
2695 err = mv88e6xxx_serdes_power(chip, port, true);
2696 mv88e6xxx_reg_unlock(chip);
2697
2698 return err;
2699 }
2700
2701 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2702 {
2703 struct mv88e6xxx_chip *chip = ds->priv;
2704
2705 mv88e6xxx_reg_lock(chip);
2706 if (mv88e6xxx_serdes_power(chip, port, false))
2707 dev_err(chip->dev, "failed to power off SERDES\n");
2708 mv88e6xxx_reg_unlock(chip);
2709 }
2710
2711 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2712 unsigned int ageing_time)
2713 {
2714 struct mv88e6xxx_chip *chip = ds->priv;
2715 int err;
2716
2717 mv88e6xxx_reg_lock(chip);
2718 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2719 mv88e6xxx_reg_unlock(chip);
2720
2721 return err;
2722 }
2723
2724 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2725 {
2726 int err;
2727
2728 /* Initialize the statistics unit */
2729 if (chip->info->ops->stats_set_histogram) {
2730 err = chip->info->ops->stats_set_histogram(chip);
2731 if (err)
2732 return err;
2733 }
2734
2735 return mv88e6xxx_g1_stats_clear(chip);
2736 }
2737
2738 /* Check if the errata has already been applied. */
2739 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2740 {
2741 int port;
2742 int err;
2743 u16 val;
2744
2745 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2746 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2747 if (err) {
2748 dev_err(chip->dev,
2749 "Error reading hidden register: %d\n", err);
2750 return false;
2751 }
2752 if (val != 0x01c0)
2753 return false;
2754 }
2755
2756 return true;
2757 }
2758
2759 /* The 6390 copper ports have an errata which require poking magic
2760 * values into undocumented hidden registers and then performing a
2761 * software reset.
2762 */
2763 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2764 {
2765 int port;
2766 int err;
2767
2768 if (mv88e6390_setup_errata_applied(chip))
2769 return 0;
2770
2771 /* Set the ports into blocking mode */
2772 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2773 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2774 if (err)
2775 return err;
2776 }
2777
2778 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2779 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2780 if (err)
2781 return err;
2782 }
2783
2784 return mv88e6xxx_software_reset(chip);
2785 }
2786
2787 enum mv88e6xxx_devlink_param_id {
2788 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
2789 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2790 };
2791
2792 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
2793 struct devlink_param_gset_ctx *ctx)
2794 {
2795 struct mv88e6xxx_chip *chip = ds->priv;
2796 int err;
2797
2798 mv88e6xxx_reg_lock(chip);
2799
2800 switch (id) {
2801 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2802 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
2803 break;
2804 default:
2805 err = -EOPNOTSUPP;
2806 break;
2807 }
2808
2809 mv88e6xxx_reg_unlock(chip);
2810
2811 return err;
2812 }
2813
2814 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
2815 struct devlink_param_gset_ctx *ctx)
2816 {
2817 struct mv88e6xxx_chip *chip = ds->priv;
2818 int err;
2819
2820 mv88e6xxx_reg_lock(chip);
2821
2822 switch (id) {
2823 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2824 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
2825 break;
2826 default:
2827 err = -EOPNOTSUPP;
2828 break;
2829 }
2830
2831 mv88e6xxx_reg_unlock(chip);
2832
2833 return err;
2834 }
2835
2836 static const struct devlink_param mv88e6xxx_devlink_params[] = {
2837 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2838 "ATU_hash", DEVLINK_PARAM_TYPE_U8,
2839 BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
2840 };
2841
2842 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
2843 {
2844 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
2845 ARRAY_SIZE(mv88e6xxx_devlink_params));
2846 }
2847
2848 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
2849 {
2850 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
2851 ARRAY_SIZE(mv88e6xxx_devlink_params));
2852 }
2853
2854 enum mv88e6xxx_devlink_resource_id {
2855 MV88E6XXX_RESOURCE_ID_ATU,
2856 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2857 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2858 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2859 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2860 };
2861
2862 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip,
2863 u16 bin)
2864 {
2865 u16 occupancy = 0;
2866 int err;
2867
2868 mv88e6xxx_reg_lock(chip);
2869
2870 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL,
2871 bin);
2872 if (err) {
2873 dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
2874 goto unlock;
2875 }
2876
2877 err = mv88e6xxx_g1_atu_get_next(chip, 0);
2878 if (err) {
2879 dev_err(chip->dev, "failed to perform ATU get next\n");
2880 goto unlock;
2881 }
2882
2883 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy);
2884 if (err) {
2885 dev_err(chip->dev, "failed to get ATU stats\n");
2886 goto unlock;
2887 }
2888
2889 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK;
2890
2891 unlock:
2892 mv88e6xxx_reg_unlock(chip);
2893
2894 return occupancy;
2895 }
2896
2897 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv)
2898 {
2899 struct mv88e6xxx_chip *chip = priv;
2900
2901 return mv88e6xxx_devlink_atu_bin_get(chip,
2902 MV88E6XXX_G2_ATU_STATS_BIN_0);
2903 }
2904
2905 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv)
2906 {
2907 struct mv88e6xxx_chip *chip = priv;
2908
2909 return mv88e6xxx_devlink_atu_bin_get(chip,
2910 MV88E6XXX_G2_ATU_STATS_BIN_1);
2911 }
2912
2913 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv)
2914 {
2915 struct mv88e6xxx_chip *chip = priv;
2916
2917 return mv88e6xxx_devlink_atu_bin_get(chip,
2918 MV88E6XXX_G2_ATU_STATS_BIN_2);
2919 }
2920
2921 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv)
2922 {
2923 struct mv88e6xxx_chip *chip = priv;
2924
2925 return mv88e6xxx_devlink_atu_bin_get(chip,
2926 MV88E6XXX_G2_ATU_STATS_BIN_3);
2927 }
2928
2929 static u64 mv88e6xxx_devlink_atu_get(void *priv)
2930 {
2931 return mv88e6xxx_devlink_atu_bin_0_get(priv) +
2932 mv88e6xxx_devlink_atu_bin_1_get(priv) +
2933 mv88e6xxx_devlink_atu_bin_2_get(priv) +
2934 mv88e6xxx_devlink_atu_bin_3_get(priv);
2935 }
2936
2937 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds)
2938 {
2939 struct devlink_resource_size_params size_params;
2940 struct mv88e6xxx_chip *chip = ds->priv;
2941 int err;
2942
2943 devlink_resource_size_params_init(&size_params,
2944 mv88e6xxx_num_macs(chip),
2945 mv88e6xxx_num_macs(chip),
2946 1, DEVLINK_RESOURCE_UNIT_ENTRY);
2947
2948 err = dsa_devlink_resource_register(ds, "ATU",
2949 mv88e6xxx_num_macs(chip),
2950 MV88E6XXX_RESOURCE_ID_ATU,
2951 DEVLINK_RESOURCE_ID_PARENT_TOP,
2952 &size_params);
2953 if (err)
2954 goto out;
2955
2956 devlink_resource_size_params_init(&size_params,
2957 mv88e6xxx_num_macs(chip) / 4,
2958 mv88e6xxx_num_macs(chip) / 4,
2959 1, DEVLINK_RESOURCE_UNIT_ENTRY);
2960
2961 err = dsa_devlink_resource_register(ds, "ATU_bin_0",
2962 mv88e6xxx_num_macs(chip) / 4,
2963 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2964 MV88E6XXX_RESOURCE_ID_ATU,
2965 &size_params);
2966 if (err)
2967 goto out;
2968
2969 err = dsa_devlink_resource_register(ds, "ATU_bin_1",
2970 mv88e6xxx_num_macs(chip) / 4,
2971 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2972 MV88E6XXX_RESOURCE_ID_ATU,
2973 &size_params);
2974 if (err)
2975 goto out;
2976
2977 err = dsa_devlink_resource_register(ds, "ATU_bin_2",
2978 mv88e6xxx_num_macs(chip) / 4,
2979 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2980 MV88E6XXX_RESOURCE_ID_ATU,
2981 &size_params);
2982 if (err)
2983 goto out;
2984
2985 err = dsa_devlink_resource_register(ds, "ATU_bin_3",
2986 mv88e6xxx_num_macs(chip) / 4,
2987 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2988 MV88E6XXX_RESOURCE_ID_ATU,
2989 &size_params);
2990 if (err)
2991 goto out;
2992
2993 dsa_devlink_resource_occ_get_register(ds,
2994 MV88E6XXX_RESOURCE_ID_ATU,
2995 mv88e6xxx_devlink_atu_get,
2996 chip);
2997
2998 dsa_devlink_resource_occ_get_register(ds,
2999 MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
3000 mv88e6xxx_devlink_atu_bin_0_get,
3001 chip);
3002
3003 dsa_devlink_resource_occ_get_register(ds,
3004 MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
3005 mv88e6xxx_devlink_atu_bin_1_get,
3006 chip);
3007
3008 dsa_devlink_resource_occ_get_register(ds,
3009 MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
3010 mv88e6xxx_devlink_atu_bin_2_get,
3011 chip);
3012
3013 dsa_devlink_resource_occ_get_register(ds,
3014 MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
3015 mv88e6xxx_devlink_atu_bin_3_get,
3016 chip);
3017
3018 return 0;
3019
3020 out:
3021 dsa_devlink_resources_unregister(ds);
3022 return err;
3023 }
3024
3025 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3026 {
3027 mv88e6xxx_teardown_devlink_params(ds);
3028 dsa_devlink_resources_unregister(ds);
3029 }
3030
3031 static int mv88e6xxx_setup(struct dsa_switch *ds)
3032 {
3033 struct mv88e6xxx_chip *chip = ds->priv;
3034 u8 cmode;
3035 int err;
3036 int i;
3037
3038 chip->ds = ds;
3039 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3040
3041 mv88e6xxx_reg_lock(chip);
3042
3043 if (chip->info->ops->setup_errata) {
3044 err = chip->info->ops->setup_errata(chip);
3045 if (err)
3046 goto unlock;
3047 }
3048
3049 /* Cache the cmode of each port. */
3050 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3051 if (chip->info->ops->port_get_cmode) {
3052 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3053 if (err)
3054 goto unlock;
3055
3056 chip->ports[i].cmode = cmode;
3057 }
3058 }
3059
3060 /* Setup Switch Port Registers */
3061 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3062 if (dsa_is_unused_port(ds, i))
3063 continue;
3064
3065 /* Prevent the use of an invalid port. */
3066 if (mv88e6xxx_is_invalid_port(chip, i)) {
3067 dev_err(chip->dev, "port %d is invalid\n", i);
3068 err = -EINVAL;
3069 goto unlock;
3070 }
3071
3072 err = mv88e6xxx_setup_port(chip, i);
3073 if (err)
3074 goto unlock;
3075 }
3076
3077 err = mv88e6xxx_irl_setup(chip);
3078 if (err)
3079 goto unlock;
3080
3081 err = mv88e6xxx_mac_setup(chip);
3082 if (err)
3083 goto unlock;
3084
3085 err = mv88e6xxx_phy_setup(chip);
3086 if (err)
3087 goto unlock;
3088
3089 err = mv88e6xxx_vtu_setup(chip);
3090 if (err)
3091 goto unlock;
3092
3093 err = mv88e6xxx_pvt_setup(chip);
3094 if (err)
3095 goto unlock;
3096
3097 err = mv88e6xxx_atu_setup(chip);
3098 if (err)
3099 goto unlock;
3100
3101 err = mv88e6xxx_broadcast_setup(chip, 0);
3102 if (err)
3103 goto unlock;
3104
3105 err = mv88e6xxx_pot_setup(chip);
3106 if (err)
3107 goto unlock;
3108
3109 err = mv88e6xxx_rmu_setup(chip);
3110 if (err)
3111 goto unlock;
3112
3113 err = mv88e6xxx_rsvd2cpu_setup(chip);
3114 if (err)
3115 goto unlock;
3116
3117 err = mv88e6xxx_trunk_setup(chip);
3118 if (err)
3119 goto unlock;
3120
3121 err = mv88e6xxx_devmap_setup(chip);
3122 if (err)
3123 goto unlock;
3124
3125 err = mv88e6xxx_pri_setup(chip);
3126 if (err)
3127 goto unlock;
3128
3129 /* Setup PTP Hardware Clock and timestamping */
3130 if (chip->info->ptp_support) {
3131 err = mv88e6xxx_ptp_setup(chip);
3132 if (err)
3133 goto unlock;
3134
3135 err = mv88e6xxx_hwtstamp_setup(chip);
3136 if (err)
3137 goto unlock;
3138 }
3139
3140 err = mv88e6xxx_stats_setup(chip);
3141 if (err)
3142 goto unlock;
3143
3144 unlock:
3145 mv88e6xxx_reg_unlock(chip);
3146
3147 if (err)
3148 return err;
3149
3150 /* Have to be called without holding the register lock, since
3151 * they take the devlink lock, and we later take the locks in
3152 * the reverse order when getting/setting parameters or
3153 * resource occupancy.
3154 */
3155 err = mv88e6xxx_setup_devlink_resources(ds);
3156 if (err)
3157 return err;
3158
3159 err = mv88e6xxx_setup_devlink_params(ds);
3160 if (err)
3161 dsa_devlink_resources_unregister(ds);
3162
3163 return err;
3164 }
3165
3166 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3167 {
3168 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3169 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3170 u16 val;
3171 int err;
3172
3173 if (!chip->info->ops->phy_read)
3174 return -EOPNOTSUPP;
3175
3176 mv88e6xxx_reg_lock(chip);
3177 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3178 mv88e6xxx_reg_unlock(chip);
3179
3180 if (reg == MII_PHYSID2) {
3181 /* Some internal PHYs don't have a model number. */
3182 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3183 /* Then there is the 6165 family. It gets is
3184 * PHYs correct. But it can also have two
3185 * SERDES interfaces in the PHY address
3186 * space. And these don't have a model
3187 * number. But they are not PHYs, so we don't
3188 * want to give them something a PHY driver
3189 * will recognise.
3190 *
3191 * Use the mv88e6390 family model number
3192 * instead, for anything which really could be
3193 * a PHY,
3194 */
3195 if (!(val & 0x3f0))
3196 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3197 }
3198
3199 return err ? err : val;
3200 }
3201
3202 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3203 {
3204 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3205 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3206 int err;
3207
3208 if (!chip->info->ops->phy_write)
3209 return -EOPNOTSUPP;
3210
3211 mv88e6xxx_reg_lock(chip);
3212 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3213 mv88e6xxx_reg_unlock(chip);
3214
3215 return err;
3216 }
3217
3218 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3219 struct device_node *np,
3220 bool external)
3221 {
3222 static int index;
3223 struct mv88e6xxx_mdio_bus *mdio_bus;
3224 struct mii_bus *bus;
3225 int err;
3226
3227 if (external) {
3228 mv88e6xxx_reg_lock(chip);
3229 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3230 mv88e6xxx_reg_unlock(chip);
3231
3232 if (err)
3233 return err;
3234 }
3235
3236 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3237 if (!bus)
3238 return -ENOMEM;
3239
3240 mdio_bus = bus->priv;
3241 mdio_bus->bus = bus;
3242 mdio_bus->chip = chip;
3243 INIT_LIST_HEAD(&mdio_bus->list);
3244 mdio_bus->external = external;
3245
3246 if (np) {
3247 bus->name = np->full_name;
3248 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3249 } else {
3250 bus->name = "mv88e6xxx SMI";
3251 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3252 }
3253
3254 bus->read = mv88e6xxx_mdio_read;
3255 bus->write = mv88e6xxx_mdio_write;
3256 bus->parent = chip->dev;
3257
3258 if (!external) {
3259 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3260 if (err)
3261 return err;
3262 }
3263
3264 err = of_mdiobus_register(bus, np);
3265 if (err) {
3266 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3267 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3268 return err;
3269 }
3270
3271 if (external)
3272 list_add_tail(&mdio_bus->list, &chip->mdios);
3273 else
3274 list_add(&mdio_bus->list, &chip->mdios);
3275
3276 return 0;
3277 }
3278
3279 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3280 { .compatible = "marvell,mv88e6xxx-mdio-external",
3281 .data = (void *)true },
3282 { },
3283 };
3284
3285 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3286
3287 {
3288 struct mv88e6xxx_mdio_bus *mdio_bus;
3289 struct mii_bus *bus;
3290
3291 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3292 bus = mdio_bus->bus;
3293
3294 if (!mdio_bus->external)
3295 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3296
3297 mdiobus_unregister(bus);
3298 }
3299 }
3300
3301 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3302 struct device_node *np)
3303 {
3304 const struct of_device_id *match;
3305 struct device_node *child;
3306 int err;
3307
3308 /* Always register one mdio bus for the internal/default mdio
3309 * bus. This maybe represented in the device tree, but is
3310 * optional.
3311 */
3312 child = of_get_child_by_name(np, "mdio");
3313 err = mv88e6xxx_mdio_register(chip, child, false);
3314 if (err)
3315 return err;
3316
3317 /* Walk the device tree, and see if there are any other nodes
3318 * which say they are compatible with the external mdio
3319 * bus.
3320 */
3321 for_each_available_child_of_node(np, child) {
3322 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3323 if (match) {
3324 err = mv88e6xxx_mdio_register(chip, child, true);
3325 if (err) {
3326 mv88e6xxx_mdios_unregister(chip);
3327 of_node_put(child);
3328 return err;
3329 }
3330 }
3331 }
3332
3333 return 0;
3334 }
3335
3336 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3337 {
3338 struct mv88e6xxx_chip *chip = ds->priv;
3339
3340 return chip->eeprom_len;
3341 }
3342
3343 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3344 struct ethtool_eeprom *eeprom, u8 *data)
3345 {
3346 struct mv88e6xxx_chip *chip = ds->priv;
3347 int err;
3348
3349 if (!chip->info->ops->get_eeprom)
3350 return -EOPNOTSUPP;
3351
3352 mv88e6xxx_reg_lock(chip);
3353 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3354 mv88e6xxx_reg_unlock(chip);
3355
3356 if (err)
3357 return err;
3358
3359 eeprom->magic = 0xc3ec4951;
3360
3361 return 0;
3362 }
3363
3364 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3365 struct ethtool_eeprom *eeprom, u8 *data)
3366 {
3367 struct mv88e6xxx_chip *chip = ds->priv;
3368 int err;
3369
3370 if (!chip->info->ops->set_eeprom)
3371 return -EOPNOTSUPP;
3372
3373 if (eeprom->magic != 0xc3ec4951)
3374 return -EINVAL;
3375
3376 mv88e6xxx_reg_lock(chip);
3377 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3378 mv88e6xxx_reg_unlock(chip);
3379
3380 return err;
3381 }
3382
3383 static const struct mv88e6xxx_ops mv88e6085_ops = {
3384 /* MV88E6XXX_FAMILY_6097 */
3385 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3386 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3387 .irl_init_all = mv88e6352_g2_irl_init_all,
3388 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3389 .phy_read = mv88e6185_phy_ppu_read,
3390 .phy_write = mv88e6185_phy_ppu_write,
3391 .port_set_link = mv88e6xxx_port_set_link,
3392 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3393 .port_tag_remap = mv88e6095_port_tag_remap,
3394 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3395 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3396 .port_set_ether_type = mv88e6351_port_set_ether_type,
3397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3398 .port_pause_limit = mv88e6097_port_pause_limit,
3399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3401 .port_get_cmode = mv88e6185_port_get_cmode,
3402 .port_setup_message_port = mv88e6xxx_setup_message_port,
3403 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3405 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3406 .stats_get_strings = mv88e6095_stats_get_strings,
3407 .stats_get_stats = mv88e6095_stats_get_stats,
3408 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3409 .set_egress_port = mv88e6095_g1_set_egress_port,
3410 .watchdog_ops = &mv88e6097_watchdog_ops,
3411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3412 .pot_clear = mv88e6xxx_g2_pot_clear,
3413 .ppu_enable = mv88e6185_g1_ppu_enable,
3414 .ppu_disable = mv88e6185_g1_ppu_disable,
3415 .reset = mv88e6185_g1_reset,
3416 .rmu_disable = mv88e6085_g1_rmu_disable,
3417 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3418 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3419 .phylink_validate = mv88e6185_phylink_validate,
3420 };
3421
3422 static const struct mv88e6xxx_ops mv88e6095_ops = {
3423 /* MV88E6XXX_FAMILY_6095 */
3424 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3425 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3426 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3427 .phy_read = mv88e6185_phy_ppu_read,
3428 .phy_write = mv88e6185_phy_ppu_write,
3429 .port_set_link = mv88e6xxx_port_set_link,
3430 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3431 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3432 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3433 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3434 .port_get_cmode = mv88e6185_port_get_cmode,
3435 .port_setup_message_port = mv88e6xxx_setup_message_port,
3436 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3437 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3438 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3439 .stats_get_strings = mv88e6095_stats_get_strings,
3440 .stats_get_stats = mv88e6095_stats_get_stats,
3441 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3442 .ppu_enable = mv88e6185_g1_ppu_enable,
3443 .ppu_disable = mv88e6185_g1_ppu_disable,
3444 .reset = mv88e6185_g1_reset,
3445 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3446 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3447 .phylink_validate = mv88e6185_phylink_validate,
3448 };
3449
3450 static const struct mv88e6xxx_ops mv88e6097_ops = {
3451 /* MV88E6XXX_FAMILY_6097 */
3452 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3453 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3454 .irl_init_all = mv88e6352_g2_irl_init_all,
3455 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3456 .phy_read = mv88e6xxx_g2_smi_phy_read,
3457 .phy_write = mv88e6xxx_g2_smi_phy_write,
3458 .port_set_link = mv88e6xxx_port_set_link,
3459 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3460 .port_tag_remap = mv88e6095_port_tag_remap,
3461 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3462 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3463 .port_set_ether_type = mv88e6351_port_set_ether_type,
3464 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3465 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3466 .port_pause_limit = mv88e6097_port_pause_limit,
3467 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3468 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3469 .port_get_cmode = mv88e6185_port_get_cmode,
3470 .port_setup_message_port = mv88e6xxx_setup_message_port,
3471 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3472 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3473 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3474 .stats_get_strings = mv88e6095_stats_get_strings,
3475 .stats_get_stats = mv88e6095_stats_get_stats,
3476 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3477 .set_egress_port = mv88e6095_g1_set_egress_port,
3478 .watchdog_ops = &mv88e6097_watchdog_ops,
3479 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3480 .pot_clear = mv88e6xxx_g2_pot_clear,
3481 .reset = mv88e6352_g1_reset,
3482 .rmu_disable = mv88e6085_g1_rmu_disable,
3483 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3484 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3485 .phylink_validate = mv88e6185_phylink_validate,
3486 };
3487
3488 static const struct mv88e6xxx_ops mv88e6123_ops = {
3489 /* MV88E6XXX_FAMILY_6165 */
3490 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3491 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3492 .irl_init_all = mv88e6352_g2_irl_init_all,
3493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3494 .phy_read = mv88e6xxx_g2_smi_phy_read,
3495 .phy_write = mv88e6xxx_g2_smi_phy_write,
3496 .port_set_link = mv88e6xxx_port_set_link,
3497 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3498 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3499 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3500 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3501 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3502 .port_get_cmode = mv88e6185_port_get_cmode,
3503 .port_setup_message_port = mv88e6xxx_setup_message_port,
3504 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3505 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3506 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3507 .stats_get_strings = mv88e6095_stats_get_strings,
3508 .stats_get_stats = mv88e6095_stats_get_stats,
3509 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3510 .set_egress_port = mv88e6095_g1_set_egress_port,
3511 .watchdog_ops = &mv88e6097_watchdog_ops,
3512 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3513 .pot_clear = mv88e6xxx_g2_pot_clear,
3514 .reset = mv88e6352_g1_reset,
3515 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3516 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3517 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3518 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3519 .phylink_validate = mv88e6185_phylink_validate,
3520 };
3521
3522 static const struct mv88e6xxx_ops mv88e6131_ops = {
3523 /* MV88E6XXX_FAMILY_6185 */
3524 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3525 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3526 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3527 .phy_read = mv88e6185_phy_ppu_read,
3528 .phy_write = mv88e6185_phy_ppu_write,
3529 .port_set_link = mv88e6xxx_port_set_link,
3530 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3531 .port_tag_remap = mv88e6095_port_tag_remap,
3532 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3533 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3534 .port_set_ether_type = mv88e6351_port_set_ether_type,
3535 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3536 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3537 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3538 .port_pause_limit = mv88e6097_port_pause_limit,
3539 .port_set_pause = mv88e6185_port_set_pause,
3540 .port_get_cmode = mv88e6185_port_get_cmode,
3541 .port_setup_message_port = mv88e6xxx_setup_message_port,
3542 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3543 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3544 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3545 .stats_get_strings = mv88e6095_stats_get_strings,
3546 .stats_get_stats = mv88e6095_stats_get_stats,
3547 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3548 .set_egress_port = mv88e6095_g1_set_egress_port,
3549 .watchdog_ops = &mv88e6097_watchdog_ops,
3550 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3551 .ppu_enable = mv88e6185_g1_ppu_enable,
3552 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3553 .ppu_disable = mv88e6185_g1_ppu_disable,
3554 .reset = mv88e6185_g1_reset,
3555 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3556 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3557 .phylink_validate = mv88e6185_phylink_validate,
3558 };
3559
3560 static const struct mv88e6xxx_ops mv88e6141_ops = {
3561 /* MV88E6XXX_FAMILY_6341 */
3562 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3563 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3564 .irl_init_all = mv88e6352_g2_irl_init_all,
3565 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3566 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3567 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3568 .phy_read = mv88e6xxx_g2_smi_phy_read,
3569 .phy_write = mv88e6xxx_g2_smi_phy_write,
3570 .port_set_link = mv88e6xxx_port_set_link,
3571 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3572 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3573 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3574 .port_tag_remap = mv88e6095_port_tag_remap,
3575 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3576 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3577 .port_set_ether_type = mv88e6351_port_set_ether_type,
3578 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3579 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3580 .port_pause_limit = mv88e6097_port_pause_limit,
3581 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3582 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3583 .port_get_cmode = mv88e6352_port_get_cmode,
3584 .port_set_cmode = mv88e6341_port_set_cmode,
3585 .port_setup_message_port = mv88e6xxx_setup_message_port,
3586 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3587 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3588 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3589 .stats_get_strings = mv88e6320_stats_get_strings,
3590 .stats_get_stats = mv88e6390_stats_get_stats,
3591 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3592 .set_egress_port = mv88e6390_g1_set_egress_port,
3593 .watchdog_ops = &mv88e6390_watchdog_ops,
3594 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3595 .pot_clear = mv88e6xxx_g2_pot_clear,
3596 .reset = mv88e6352_g1_reset,
3597 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3598 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3599 .serdes_power = mv88e6390_serdes_power,
3600 .serdes_get_lane = mv88e6341_serdes_get_lane,
3601 /* Check status register pause & lpa register */
3602 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3603 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3604 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3605 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3606 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3607 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3608 .serdes_irq_status = mv88e6390_serdes_irq_status,
3609 .gpio_ops = &mv88e6352_gpio_ops,
3610 .phylink_validate = mv88e6341_phylink_validate,
3611 };
3612
3613 static const struct mv88e6xxx_ops mv88e6161_ops = {
3614 /* MV88E6XXX_FAMILY_6165 */
3615 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3616 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3617 .irl_init_all = mv88e6352_g2_irl_init_all,
3618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3619 .phy_read = mv88e6xxx_g2_smi_phy_read,
3620 .phy_write = mv88e6xxx_g2_smi_phy_write,
3621 .port_set_link = mv88e6xxx_port_set_link,
3622 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3623 .port_tag_remap = mv88e6095_port_tag_remap,
3624 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3625 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3626 .port_set_ether_type = mv88e6351_port_set_ether_type,
3627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3629 .port_pause_limit = mv88e6097_port_pause_limit,
3630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3632 .port_get_cmode = mv88e6185_port_get_cmode,
3633 .port_setup_message_port = mv88e6xxx_setup_message_port,
3634 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3635 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3636 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3637 .stats_get_strings = mv88e6095_stats_get_strings,
3638 .stats_get_stats = mv88e6095_stats_get_stats,
3639 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3640 .set_egress_port = mv88e6095_g1_set_egress_port,
3641 .watchdog_ops = &mv88e6097_watchdog_ops,
3642 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3643 .pot_clear = mv88e6xxx_g2_pot_clear,
3644 .reset = mv88e6352_g1_reset,
3645 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3646 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3647 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3648 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3649 .avb_ops = &mv88e6165_avb_ops,
3650 .ptp_ops = &mv88e6165_ptp_ops,
3651 .phylink_validate = mv88e6185_phylink_validate,
3652 };
3653
3654 static const struct mv88e6xxx_ops mv88e6165_ops = {
3655 /* MV88E6XXX_FAMILY_6165 */
3656 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3657 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3658 .irl_init_all = mv88e6352_g2_irl_init_all,
3659 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3660 .phy_read = mv88e6165_phy_read,
3661 .phy_write = mv88e6165_phy_write,
3662 .port_set_link = mv88e6xxx_port_set_link,
3663 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3666 .port_get_cmode = mv88e6185_port_get_cmode,
3667 .port_setup_message_port = mv88e6xxx_setup_message_port,
3668 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3669 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3670 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3671 .stats_get_strings = mv88e6095_stats_get_strings,
3672 .stats_get_stats = mv88e6095_stats_get_stats,
3673 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3674 .set_egress_port = mv88e6095_g1_set_egress_port,
3675 .watchdog_ops = &mv88e6097_watchdog_ops,
3676 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3677 .pot_clear = mv88e6xxx_g2_pot_clear,
3678 .reset = mv88e6352_g1_reset,
3679 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3680 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3681 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3682 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3683 .avb_ops = &mv88e6165_avb_ops,
3684 .ptp_ops = &mv88e6165_ptp_ops,
3685 .phylink_validate = mv88e6185_phylink_validate,
3686 };
3687
3688 static const struct mv88e6xxx_ops mv88e6171_ops = {
3689 /* MV88E6XXX_FAMILY_6351 */
3690 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3691 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3692 .irl_init_all = mv88e6352_g2_irl_init_all,
3693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3694 .phy_read = mv88e6xxx_g2_smi_phy_read,
3695 .phy_write = mv88e6xxx_g2_smi_phy_write,
3696 .port_set_link = mv88e6xxx_port_set_link,
3697 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3698 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3699 .port_tag_remap = mv88e6095_port_tag_remap,
3700 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3701 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3702 .port_set_ether_type = mv88e6351_port_set_ether_type,
3703 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3704 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3705 .port_pause_limit = mv88e6097_port_pause_limit,
3706 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3707 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3708 .port_get_cmode = mv88e6352_port_get_cmode,
3709 .port_setup_message_port = mv88e6xxx_setup_message_port,
3710 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3711 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3712 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3713 .stats_get_strings = mv88e6095_stats_get_strings,
3714 .stats_get_stats = mv88e6095_stats_get_stats,
3715 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3716 .set_egress_port = mv88e6095_g1_set_egress_port,
3717 .watchdog_ops = &mv88e6097_watchdog_ops,
3718 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3719 .pot_clear = mv88e6xxx_g2_pot_clear,
3720 .reset = mv88e6352_g1_reset,
3721 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3722 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3723 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3724 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3725 .phylink_validate = mv88e6185_phylink_validate,
3726 };
3727
3728 static const struct mv88e6xxx_ops mv88e6172_ops = {
3729 /* MV88E6XXX_FAMILY_6352 */
3730 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3731 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3732 .irl_init_all = mv88e6352_g2_irl_init_all,
3733 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3734 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3735 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3736 .phy_read = mv88e6xxx_g2_smi_phy_read,
3737 .phy_write = mv88e6xxx_g2_smi_phy_write,
3738 .port_set_link = mv88e6xxx_port_set_link,
3739 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3740 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3741 .port_tag_remap = mv88e6095_port_tag_remap,
3742 .port_set_policy = mv88e6352_port_set_policy,
3743 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3744 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3745 .port_set_ether_type = mv88e6351_port_set_ether_type,
3746 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3747 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3748 .port_pause_limit = mv88e6097_port_pause_limit,
3749 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3750 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3751 .port_get_cmode = mv88e6352_port_get_cmode,
3752 .port_setup_message_port = mv88e6xxx_setup_message_port,
3753 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3754 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3755 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3756 .stats_get_strings = mv88e6095_stats_get_strings,
3757 .stats_get_stats = mv88e6095_stats_get_stats,
3758 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3759 .set_egress_port = mv88e6095_g1_set_egress_port,
3760 .watchdog_ops = &mv88e6097_watchdog_ops,
3761 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3762 .pot_clear = mv88e6xxx_g2_pot_clear,
3763 .reset = mv88e6352_g1_reset,
3764 .rmu_disable = mv88e6352_g1_rmu_disable,
3765 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3766 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3767 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3768 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3769 .serdes_get_lane = mv88e6352_serdes_get_lane,
3770 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3771 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3772 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3773 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3774 .serdes_power = mv88e6352_serdes_power,
3775 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3776 .serdes_get_regs = mv88e6352_serdes_get_regs,
3777 .gpio_ops = &mv88e6352_gpio_ops,
3778 .phylink_validate = mv88e6352_phylink_validate,
3779 };
3780
3781 static const struct mv88e6xxx_ops mv88e6175_ops = {
3782 /* MV88E6XXX_FAMILY_6351 */
3783 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3784 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3785 .irl_init_all = mv88e6352_g2_irl_init_all,
3786 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3787 .phy_read = mv88e6xxx_g2_smi_phy_read,
3788 .phy_write = mv88e6xxx_g2_smi_phy_write,
3789 .port_set_link = mv88e6xxx_port_set_link,
3790 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3791 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3792 .port_tag_remap = mv88e6095_port_tag_remap,
3793 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3794 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3795 .port_set_ether_type = mv88e6351_port_set_ether_type,
3796 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3797 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3798 .port_pause_limit = mv88e6097_port_pause_limit,
3799 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3800 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3801 .port_get_cmode = mv88e6352_port_get_cmode,
3802 .port_setup_message_port = mv88e6xxx_setup_message_port,
3803 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3804 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3805 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3806 .stats_get_strings = mv88e6095_stats_get_strings,
3807 .stats_get_stats = mv88e6095_stats_get_stats,
3808 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3809 .set_egress_port = mv88e6095_g1_set_egress_port,
3810 .watchdog_ops = &mv88e6097_watchdog_ops,
3811 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3812 .pot_clear = mv88e6xxx_g2_pot_clear,
3813 .reset = mv88e6352_g1_reset,
3814 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3815 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3816 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3817 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3818 .phylink_validate = mv88e6185_phylink_validate,
3819 };
3820
3821 static const struct mv88e6xxx_ops mv88e6176_ops = {
3822 /* MV88E6XXX_FAMILY_6352 */
3823 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3824 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3825 .irl_init_all = mv88e6352_g2_irl_init_all,
3826 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3827 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3828 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3829 .phy_read = mv88e6xxx_g2_smi_phy_read,
3830 .phy_write = mv88e6xxx_g2_smi_phy_write,
3831 .port_set_link = mv88e6xxx_port_set_link,
3832 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3833 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3834 .port_tag_remap = mv88e6095_port_tag_remap,
3835 .port_set_policy = mv88e6352_port_set_policy,
3836 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3837 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3838 .port_set_ether_type = mv88e6351_port_set_ether_type,
3839 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3840 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3841 .port_pause_limit = mv88e6097_port_pause_limit,
3842 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3843 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3844 .port_get_cmode = mv88e6352_port_get_cmode,
3845 .port_setup_message_port = mv88e6xxx_setup_message_port,
3846 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3847 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3848 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3849 .stats_get_strings = mv88e6095_stats_get_strings,
3850 .stats_get_stats = mv88e6095_stats_get_stats,
3851 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3852 .set_egress_port = mv88e6095_g1_set_egress_port,
3853 .watchdog_ops = &mv88e6097_watchdog_ops,
3854 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3855 .pot_clear = mv88e6xxx_g2_pot_clear,
3856 .reset = mv88e6352_g1_reset,
3857 .rmu_disable = mv88e6352_g1_rmu_disable,
3858 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3859 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3860 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3861 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3862 .serdes_get_lane = mv88e6352_serdes_get_lane,
3863 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3864 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3865 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3866 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3867 .serdes_power = mv88e6352_serdes_power,
3868 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3869 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3870 .serdes_irq_status = mv88e6352_serdes_irq_status,
3871 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3872 .serdes_get_regs = mv88e6352_serdes_get_regs,
3873 .gpio_ops = &mv88e6352_gpio_ops,
3874 .phylink_validate = mv88e6352_phylink_validate,
3875 };
3876
3877 static const struct mv88e6xxx_ops mv88e6185_ops = {
3878 /* MV88E6XXX_FAMILY_6185 */
3879 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3880 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3881 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3882 .phy_read = mv88e6185_phy_ppu_read,
3883 .phy_write = mv88e6185_phy_ppu_write,
3884 .port_set_link = mv88e6xxx_port_set_link,
3885 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3886 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3887 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3888 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3889 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3890 .port_set_pause = mv88e6185_port_set_pause,
3891 .port_get_cmode = mv88e6185_port_get_cmode,
3892 .port_setup_message_port = mv88e6xxx_setup_message_port,
3893 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3894 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3895 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3896 .stats_get_strings = mv88e6095_stats_get_strings,
3897 .stats_get_stats = mv88e6095_stats_get_stats,
3898 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3899 .set_egress_port = mv88e6095_g1_set_egress_port,
3900 .watchdog_ops = &mv88e6097_watchdog_ops,
3901 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3902 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3903 .ppu_enable = mv88e6185_g1_ppu_enable,
3904 .ppu_disable = mv88e6185_g1_ppu_disable,
3905 .reset = mv88e6185_g1_reset,
3906 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3907 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3908 .phylink_validate = mv88e6185_phylink_validate,
3909 };
3910
3911 static const struct mv88e6xxx_ops mv88e6190_ops = {
3912 /* MV88E6XXX_FAMILY_6390 */
3913 .setup_errata = mv88e6390_setup_errata,
3914 .irl_init_all = mv88e6390_g2_irl_init_all,
3915 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3916 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3917 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3918 .phy_read = mv88e6xxx_g2_smi_phy_read,
3919 .phy_write = mv88e6xxx_g2_smi_phy_write,
3920 .port_set_link = mv88e6xxx_port_set_link,
3921 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3922 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3923 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3924 .port_tag_remap = mv88e6390_port_tag_remap,
3925 .port_set_policy = mv88e6352_port_set_policy,
3926 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3927 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3928 .port_set_ether_type = mv88e6351_port_set_ether_type,
3929 .port_pause_limit = mv88e6390_port_pause_limit,
3930 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3931 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3932 .port_get_cmode = mv88e6352_port_get_cmode,
3933 .port_set_cmode = mv88e6390_port_set_cmode,
3934 .port_setup_message_port = mv88e6xxx_setup_message_port,
3935 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3936 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3937 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3938 .stats_get_strings = mv88e6320_stats_get_strings,
3939 .stats_get_stats = mv88e6390_stats_get_stats,
3940 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3941 .set_egress_port = mv88e6390_g1_set_egress_port,
3942 .watchdog_ops = &mv88e6390_watchdog_ops,
3943 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3944 .pot_clear = mv88e6xxx_g2_pot_clear,
3945 .reset = mv88e6352_g1_reset,
3946 .rmu_disable = mv88e6390_g1_rmu_disable,
3947 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3948 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3949 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3950 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3951 .serdes_power = mv88e6390_serdes_power,
3952 .serdes_get_lane = mv88e6390_serdes_get_lane,
3953 /* Check status register pause & lpa register */
3954 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3955 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3956 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3957 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3958 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3959 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3960 .serdes_irq_status = mv88e6390_serdes_irq_status,
3961 .serdes_get_strings = mv88e6390_serdes_get_strings,
3962 .serdes_get_stats = mv88e6390_serdes_get_stats,
3963 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3964 .serdes_get_regs = mv88e6390_serdes_get_regs,
3965 .phylink_validate = mv88e6390_phylink_validate,
3966 .gpio_ops = &mv88e6352_gpio_ops,
3967 .phylink_validate = mv88e6390_phylink_validate,
3968 };
3969
3970 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3971 /* MV88E6XXX_FAMILY_6390 */
3972 .setup_errata = mv88e6390_setup_errata,
3973 .irl_init_all = mv88e6390_g2_irl_init_all,
3974 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3975 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3976 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3977 .phy_read = mv88e6xxx_g2_smi_phy_read,
3978 .phy_write = mv88e6xxx_g2_smi_phy_write,
3979 .port_set_link = mv88e6xxx_port_set_link,
3980 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3981 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3982 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3983 .port_tag_remap = mv88e6390_port_tag_remap,
3984 .port_set_policy = mv88e6352_port_set_policy,
3985 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3986 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3987 .port_set_ether_type = mv88e6351_port_set_ether_type,
3988 .port_pause_limit = mv88e6390_port_pause_limit,
3989 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3990 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3991 .port_get_cmode = mv88e6352_port_get_cmode,
3992 .port_set_cmode = mv88e6390x_port_set_cmode,
3993 .port_setup_message_port = mv88e6xxx_setup_message_port,
3994 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3995 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3996 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3997 .stats_get_strings = mv88e6320_stats_get_strings,
3998 .stats_get_stats = mv88e6390_stats_get_stats,
3999 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4000 .set_egress_port = mv88e6390_g1_set_egress_port,
4001 .watchdog_ops = &mv88e6390_watchdog_ops,
4002 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4003 .pot_clear = mv88e6xxx_g2_pot_clear,
4004 .reset = mv88e6352_g1_reset,
4005 .rmu_disable = mv88e6390_g1_rmu_disable,
4006 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4007 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4008 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4009 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4010 .serdes_power = mv88e6390_serdes_power,
4011 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4012 /* Check status register pause & lpa register */
4013 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4014 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4015 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4016 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4017 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4018 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4019 .serdes_irq_status = mv88e6390_serdes_irq_status,
4020 .serdes_get_strings = mv88e6390_serdes_get_strings,
4021 .serdes_get_stats = mv88e6390_serdes_get_stats,
4022 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4023 .serdes_get_regs = mv88e6390_serdes_get_regs,
4024 .phylink_validate = mv88e6390_phylink_validate,
4025 .gpio_ops = &mv88e6352_gpio_ops,
4026 .phylink_validate = mv88e6390x_phylink_validate,
4027 };
4028
4029 static const struct mv88e6xxx_ops mv88e6191_ops = {
4030 /* MV88E6XXX_FAMILY_6390 */
4031 .setup_errata = mv88e6390_setup_errata,
4032 .irl_init_all = mv88e6390_g2_irl_init_all,
4033 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4034 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4035 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4036 .phy_read = mv88e6xxx_g2_smi_phy_read,
4037 .phy_write = mv88e6xxx_g2_smi_phy_write,
4038 .port_set_link = mv88e6xxx_port_set_link,
4039 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4040 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4041 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4042 .port_tag_remap = mv88e6390_port_tag_remap,
4043 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4044 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4045 .port_set_ether_type = mv88e6351_port_set_ether_type,
4046 .port_pause_limit = mv88e6390_port_pause_limit,
4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4049 .port_get_cmode = mv88e6352_port_get_cmode,
4050 .port_set_cmode = mv88e6390_port_set_cmode,
4051 .port_setup_message_port = mv88e6xxx_setup_message_port,
4052 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4053 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4054 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4055 .stats_get_strings = mv88e6320_stats_get_strings,
4056 .stats_get_stats = mv88e6390_stats_get_stats,
4057 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4058 .set_egress_port = mv88e6390_g1_set_egress_port,
4059 .watchdog_ops = &mv88e6390_watchdog_ops,
4060 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4061 .pot_clear = mv88e6xxx_g2_pot_clear,
4062 .reset = mv88e6352_g1_reset,
4063 .rmu_disable = mv88e6390_g1_rmu_disable,
4064 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4065 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4066 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4067 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4068 .serdes_power = mv88e6390_serdes_power,
4069 .serdes_get_lane = mv88e6390_serdes_get_lane,
4070 /* Check status register pause & lpa register */
4071 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4072 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4073 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4074 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4075 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4076 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4077 .serdes_irq_status = mv88e6390_serdes_irq_status,
4078 .serdes_get_strings = mv88e6390_serdes_get_strings,
4079 .serdes_get_stats = mv88e6390_serdes_get_stats,
4080 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4081 .serdes_get_regs = mv88e6390_serdes_get_regs,
4082 .phylink_validate = mv88e6390_phylink_validate,
4083 .avb_ops = &mv88e6390_avb_ops,
4084 .ptp_ops = &mv88e6352_ptp_ops,
4085 .phylink_validate = mv88e6390_phylink_validate,
4086 };
4087
4088 static const struct mv88e6xxx_ops mv88e6240_ops = {
4089 /* MV88E6XXX_FAMILY_6352 */
4090 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4091 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4092 .irl_init_all = mv88e6352_g2_irl_init_all,
4093 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4094 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4095 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4096 .phy_read = mv88e6xxx_g2_smi_phy_read,
4097 .phy_write = mv88e6xxx_g2_smi_phy_write,
4098 .port_set_link = mv88e6xxx_port_set_link,
4099 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4100 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4101 .port_tag_remap = mv88e6095_port_tag_remap,
4102 .port_set_policy = mv88e6352_port_set_policy,
4103 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4104 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4105 .port_set_ether_type = mv88e6351_port_set_ether_type,
4106 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4107 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4108 .port_pause_limit = mv88e6097_port_pause_limit,
4109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4111 .port_get_cmode = mv88e6352_port_get_cmode,
4112 .port_setup_message_port = mv88e6xxx_setup_message_port,
4113 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4114 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4115 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4116 .stats_get_strings = mv88e6095_stats_get_strings,
4117 .stats_get_stats = mv88e6095_stats_get_stats,
4118 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4119 .set_egress_port = mv88e6095_g1_set_egress_port,
4120 .watchdog_ops = &mv88e6097_watchdog_ops,
4121 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4122 .pot_clear = mv88e6xxx_g2_pot_clear,
4123 .reset = mv88e6352_g1_reset,
4124 .rmu_disable = mv88e6352_g1_rmu_disable,
4125 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4126 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4127 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4128 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4129 .serdes_get_lane = mv88e6352_serdes_get_lane,
4130 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4131 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4132 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4133 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4134 .serdes_power = mv88e6352_serdes_power,
4135 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4136 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4137 .serdes_irq_status = mv88e6352_serdes_irq_status,
4138 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4139 .serdes_get_regs = mv88e6352_serdes_get_regs,
4140 .gpio_ops = &mv88e6352_gpio_ops,
4141 .avb_ops = &mv88e6352_avb_ops,
4142 .ptp_ops = &mv88e6352_ptp_ops,
4143 .phylink_validate = mv88e6352_phylink_validate,
4144 };
4145
4146 static const struct mv88e6xxx_ops mv88e6250_ops = {
4147 /* MV88E6XXX_FAMILY_6250 */
4148 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4149 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4150 .irl_init_all = mv88e6352_g2_irl_init_all,
4151 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4152 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4153 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4154 .phy_read = mv88e6xxx_g2_smi_phy_read,
4155 .phy_write = mv88e6xxx_g2_smi_phy_write,
4156 .port_set_link = mv88e6xxx_port_set_link,
4157 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4158 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4159 .port_tag_remap = mv88e6095_port_tag_remap,
4160 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4161 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4162 .port_set_ether_type = mv88e6351_port_set_ether_type,
4163 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4164 .port_pause_limit = mv88e6097_port_pause_limit,
4165 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4166 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4167 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4168 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4169 .stats_get_strings = mv88e6250_stats_get_strings,
4170 .stats_get_stats = mv88e6250_stats_get_stats,
4171 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4172 .set_egress_port = mv88e6095_g1_set_egress_port,
4173 .watchdog_ops = &mv88e6250_watchdog_ops,
4174 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4175 .pot_clear = mv88e6xxx_g2_pot_clear,
4176 .reset = mv88e6250_g1_reset,
4177 .vtu_getnext = mv88e6250_g1_vtu_getnext,
4178 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4179 .avb_ops = &mv88e6352_avb_ops,
4180 .ptp_ops = &mv88e6250_ptp_ops,
4181 .phylink_validate = mv88e6065_phylink_validate,
4182 };
4183
4184 static const struct mv88e6xxx_ops mv88e6290_ops = {
4185 /* MV88E6XXX_FAMILY_6390 */
4186 .setup_errata = mv88e6390_setup_errata,
4187 .irl_init_all = mv88e6390_g2_irl_init_all,
4188 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4189 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4190 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4191 .phy_read = mv88e6xxx_g2_smi_phy_read,
4192 .phy_write = mv88e6xxx_g2_smi_phy_write,
4193 .port_set_link = mv88e6xxx_port_set_link,
4194 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4195 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4196 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4197 .port_tag_remap = mv88e6390_port_tag_remap,
4198 .port_set_policy = mv88e6352_port_set_policy,
4199 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4200 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4201 .port_set_ether_type = mv88e6351_port_set_ether_type,
4202 .port_pause_limit = mv88e6390_port_pause_limit,
4203 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4204 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4205 .port_get_cmode = mv88e6352_port_get_cmode,
4206 .port_set_cmode = mv88e6390_port_set_cmode,
4207 .port_setup_message_port = mv88e6xxx_setup_message_port,
4208 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4209 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4210 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4211 .stats_get_strings = mv88e6320_stats_get_strings,
4212 .stats_get_stats = mv88e6390_stats_get_stats,
4213 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4214 .set_egress_port = mv88e6390_g1_set_egress_port,
4215 .watchdog_ops = &mv88e6390_watchdog_ops,
4216 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4217 .pot_clear = mv88e6xxx_g2_pot_clear,
4218 .reset = mv88e6352_g1_reset,
4219 .rmu_disable = mv88e6390_g1_rmu_disable,
4220 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4221 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4222 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4223 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4224 .serdes_power = mv88e6390_serdes_power,
4225 .serdes_get_lane = mv88e6390_serdes_get_lane,
4226 /* Check status register pause & lpa register */
4227 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4228 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4229 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4230 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4231 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4232 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4233 .serdes_irq_status = mv88e6390_serdes_irq_status,
4234 .serdes_get_strings = mv88e6390_serdes_get_strings,
4235 .serdes_get_stats = mv88e6390_serdes_get_stats,
4236 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4237 .serdes_get_regs = mv88e6390_serdes_get_regs,
4238 .phylink_validate = mv88e6390_phylink_validate,
4239 .gpio_ops = &mv88e6352_gpio_ops,
4240 .avb_ops = &mv88e6390_avb_ops,
4241 .ptp_ops = &mv88e6352_ptp_ops,
4242 .phylink_validate = mv88e6390_phylink_validate,
4243 };
4244
4245 static const struct mv88e6xxx_ops mv88e6320_ops = {
4246 /* MV88E6XXX_FAMILY_6320 */
4247 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4248 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4249 .irl_init_all = mv88e6352_g2_irl_init_all,
4250 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4251 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4252 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4253 .phy_read = mv88e6xxx_g2_smi_phy_read,
4254 .phy_write = mv88e6xxx_g2_smi_phy_write,
4255 .port_set_link = mv88e6xxx_port_set_link,
4256 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4257 .port_tag_remap = mv88e6095_port_tag_remap,
4258 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4259 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4260 .port_set_ether_type = mv88e6351_port_set_ether_type,
4261 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4262 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4263 .port_pause_limit = mv88e6097_port_pause_limit,
4264 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4265 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4266 .port_get_cmode = mv88e6352_port_get_cmode,
4267 .port_setup_message_port = mv88e6xxx_setup_message_port,
4268 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4269 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4270 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4271 .stats_get_strings = mv88e6320_stats_get_strings,
4272 .stats_get_stats = mv88e6320_stats_get_stats,
4273 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4274 .set_egress_port = mv88e6095_g1_set_egress_port,
4275 .watchdog_ops = &mv88e6390_watchdog_ops,
4276 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4277 .pot_clear = mv88e6xxx_g2_pot_clear,
4278 .reset = mv88e6352_g1_reset,
4279 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4280 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4281 .gpio_ops = &mv88e6352_gpio_ops,
4282 .avb_ops = &mv88e6352_avb_ops,
4283 .ptp_ops = &mv88e6352_ptp_ops,
4284 .phylink_validate = mv88e6185_phylink_validate,
4285 };
4286
4287 static const struct mv88e6xxx_ops mv88e6321_ops = {
4288 /* MV88E6XXX_FAMILY_6320 */
4289 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4290 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4291 .irl_init_all = mv88e6352_g2_irl_init_all,
4292 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4293 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4295 .phy_read = mv88e6xxx_g2_smi_phy_read,
4296 .phy_write = mv88e6xxx_g2_smi_phy_write,
4297 .port_set_link = mv88e6xxx_port_set_link,
4298 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4299 .port_tag_remap = mv88e6095_port_tag_remap,
4300 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4301 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4302 .port_set_ether_type = mv88e6351_port_set_ether_type,
4303 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4304 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4305 .port_pause_limit = mv88e6097_port_pause_limit,
4306 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4307 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4308 .port_get_cmode = mv88e6352_port_get_cmode,
4309 .port_setup_message_port = mv88e6xxx_setup_message_port,
4310 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4311 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4312 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4313 .stats_get_strings = mv88e6320_stats_get_strings,
4314 .stats_get_stats = mv88e6320_stats_get_stats,
4315 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4316 .set_egress_port = mv88e6095_g1_set_egress_port,
4317 .watchdog_ops = &mv88e6390_watchdog_ops,
4318 .reset = mv88e6352_g1_reset,
4319 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4320 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4321 .gpio_ops = &mv88e6352_gpio_ops,
4322 .avb_ops = &mv88e6352_avb_ops,
4323 .ptp_ops = &mv88e6352_ptp_ops,
4324 .phylink_validate = mv88e6185_phylink_validate,
4325 };
4326
4327 static const struct mv88e6xxx_ops mv88e6341_ops = {
4328 /* MV88E6XXX_FAMILY_6341 */
4329 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4330 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4331 .irl_init_all = mv88e6352_g2_irl_init_all,
4332 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4333 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4334 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4335 .phy_read = mv88e6xxx_g2_smi_phy_read,
4336 .phy_write = mv88e6xxx_g2_smi_phy_write,
4337 .port_set_link = mv88e6xxx_port_set_link,
4338 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4339 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4340 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4341 .port_tag_remap = mv88e6095_port_tag_remap,
4342 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4343 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4344 .port_set_ether_type = mv88e6351_port_set_ether_type,
4345 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4346 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4347 .port_pause_limit = mv88e6097_port_pause_limit,
4348 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4349 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4350 .port_get_cmode = mv88e6352_port_get_cmode,
4351 .port_set_cmode = mv88e6341_port_set_cmode,
4352 .port_setup_message_port = mv88e6xxx_setup_message_port,
4353 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4354 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4355 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4356 .stats_get_strings = mv88e6320_stats_get_strings,
4357 .stats_get_stats = mv88e6390_stats_get_stats,
4358 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4359 .set_egress_port = mv88e6390_g1_set_egress_port,
4360 .watchdog_ops = &mv88e6390_watchdog_ops,
4361 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4362 .pot_clear = mv88e6xxx_g2_pot_clear,
4363 .reset = mv88e6352_g1_reset,
4364 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4365 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4366 .serdes_power = mv88e6390_serdes_power,
4367 .serdes_get_lane = mv88e6341_serdes_get_lane,
4368 /* Check status register pause & lpa register */
4369 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4370 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4371 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4372 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4373 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4374 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4375 .serdes_irq_status = mv88e6390_serdes_irq_status,
4376 .gpio_ops = &mv88e6352_gpio_ops,
4377 .avb_ops = &mv88e6390_avb_ops,
4378 .ptp_ops = &mv88e6352_ptp_ops,
4379 .phylink_validate = mv88e6341_phylink_validate,
4380 };
4381
4382 static const struct mv88e6xxx_ops mv88e6350_ops = {
4383 /* MV88E6XXX_FAMILY_6351 */
4384 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4385 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4386 .irl_init_all = mv88e6352_g2_irl_init_all,
4387 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4388 .phy_read = mv88e6xxx_g2_smi_phy_read,
4389 .phy_write = mv88e6xxx_g2_smi_phy_write,
4390 .port_set_link = mv88e6xxx_port_set_link,
4391 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4392 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4393 .port_tag_remap = mv88e6095_port_tag_remap,
4394 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4395 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4396 .port_set_ether_type = mv88e6351_port_set_ether_type,
4397 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4398 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4399 .port_pause_limit = mv88e6097_port_pause_limit,
4400 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4401 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4402 .port_get_cmode = mv88e6352_port_get_cmode,
4403 .port_setup_message_port = mv88e6xxx_setup_message_port,
4404 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4405 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4406 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4407 .stats_get_strings = mv88e6095_stats_get_strings,
4408 .stats_get_stats = mv88e6095_stats_get_stats,
4409 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4410 .set_egress_port = mv88e6095_g1_set_egress_port,
4411 .watchdog_ops = &mv88e6097_watchdog_ops,
4412 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4413 .pot_clear = mv88e6xxx_g2_pot_clear,
4414 .reset = mv88e6352_g1_reset,
4415 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4416 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4417 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4418 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4419 .phylink_validate = mv88e6185_phylink_validate,
4420 };
4421
4422 static const struct mv88e6xxx_ops mv88e6351_ops = {
4423 /* MV88E6XXX_FAMILY_6351 */
4424 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4425 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4426 .irl_init_all = mv88e6352_g2_irl_init_all,
4427 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4428 .phy_read = mv88e6xxx_g2_smi_phy_read,
4429 .phy_write = mv88e6xxx_g2_smi_phy_write,
4430 .port_set_link = mv88e6xxx_port_set_link,
4431 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4432 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4433 .port_tag_remap = mv88e6095_port_tag_remap,
4434 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4435 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4436 .port_set_ether_type = mv88e6351_port_set_ether_type,
4437 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4438 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4439 .port_pause_limit = mv88e6097_port_pause_limit,
4440 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4441 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4442 .port_get_cmode = mv88e6352_port_get_cmode,
4443 .port_setup_message_port = mv88e6xxx_setup_message_port,
4444 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4446 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4447 .stats_get_strings = mv88e6095_stats_get_strings,
4448 .stats_get_stats = mv88e6095_stats_get_stats,
4449 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4450 .set_egress_port = mv88e6095_g1_set_egress_port,
4451 .watchdog_ops = &mv88e6097_watchdog_ops,
4452 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4453 .pot_clear = mv88e6xxx_g2_pot_clear,
4454 .reset = mv88e6352_g1_reset,
4455 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4456 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4457 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4458 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4459 .avb_ops = &mv88e6352_avb_ops,
4460 .ptp_ops = &mv88e6352_ptp_ops,
4461 .phylink_validate = mv88e6185_phylink_validate,
4462 };
4463
4464 static const struct mv88e6xxx_ops mv88e6352_ops = {
4465 /* MV88E6XXX_FAMILY_6352 */
4466 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4467 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4468 .irl_init_all = mv88e6352_g2_irl_init_all,
4469 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4470 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4471 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4472 .phy_read = mv88e6xxx_g2_smi_phy_read,
4473 .phy_write = mv88e6xxx_g2_smi_phy_write,
4474 .port_set_link = mv88e6xxx_port_set_link,
4475 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4476 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4477 .port_tag_remap = mv88e6095_port_tag_remap,
4478 .port_set_policy = mv88e6352_port_set_policy,
4479 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4480 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4481 .port_set_ether_type = mv88e6351_port_set_ether_type,
4482 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4483 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4484 .port_pause_limit = mv88e6097_port_pause_limit,
4485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4487 .port_get_cmode = mv88e6352_port_get_cmode,
4488 .port_setup_message_port = mv88e6xxx_setup_message_port,
4489 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4491 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4492 .stats_get_strings = mv88e6095_stats_get_strings,
4493 .stats_get_stats = mv88e6095_stats_get_stats,
4494 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4495 .set_egress_port = mv88e6095_g1_set_egress_port,
4496 .watchdog_ops = &mv88e6097_watchdog_ops,
4497 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4498 .pot_clear = mv88e6xxx_g2_pot_clear,
4499 .reset = mv88e6352_g1_reset,
4500 .rmu_disable = mv88e6352_g1_rmu_disable,
4501 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4502 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4503 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4504 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4505 .serdes_get_lane = mv88e6352_serdes_get_lane,
4506 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4507 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4508 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4509 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4510 .serdes_power = mv88e6352_serdes_power,
4511 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4512 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4513 .serdes_irq_status = mv88e6352_serdes_irq_status,
4514 .gpio_ops = &mv88e6352_gpio_ops,
4515 .avb_ops = &mv88e6352_avb_ops,
4516 .ptp_ops = &mv88e6352_ptp_ops,
4517 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4518 .serdes_get_strings = mv88e6352_serdes_get_strings,
4519 .serdes_get_stats = mv88e6352_serdes_get_stats,
4520 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4521 .serdes_get_regs = mv88e6352_serdes_get_regs,
4522 .phylink_validate = mv88e6352_phylink_validate,
4523 };
4524
4525 static const struct mv88e6xxx_ops mv88e6390_ops = {
4526 /* MV88E6XXX_FAMILY_6390 */
4527 .setup_errata = mv88e6390_setup_errata,
4528 .irl_init_all = mv88e6390_g2_irl_init_all,
4529 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4530 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4531 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4532 .phy_read = mv88e6xxx_g2_smi_phy_read,
4533 .phy_write = mv88e6xxx_g2_smi_phy_write,
4534 .port_set_link = mv88e6xxx_port_set_link,
4535 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4536 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4537 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4538 .port_tag_remap = mv88e6390_port_tag_remap,
4539 .port_set_policy = mv88e6352_port_set_policy,
4540 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4541 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4542 .port_set_ether_type = mv88e6351_port_set_ether_type,
4543 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4544 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4545 .port_pause_limit = mv88e6390_port_pause_limit,
4546 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4547 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4548 .port_get_cmode = mv88e6352_port_get_cmode,
4549 .port_set_cmode = mv88e6390_port_set_cmode,
4550 .port_setup_message_port = mv88e6xxx_setup_message_port,
4551 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4552 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4553 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4554 .stats_get_strings = mv88e6320_stats_get_strings,
4555 .stats_get_stats = mv88e6390_stats_get_stats,
4556 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4557 .set_egress_port = mv88e6390_g1_set_egress_port,
4558 .watchdog_ops = &mv88e6390_watchdog_ops,
4559 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4560 .pot_clear = mv88e6xxx_g2_pot_clear,
4561 .reset = mv88e6352_g1_reset,
4562 .rmu_disable = mv88e6390_g1_rmu_disable,
4563 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4564 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4565 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4566 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4567 .serdes_power = mv88e6390_serdes_power,
4568 .serdes_get_lane = mv88e6390_serdes_get_lane,
4569 /* Check status register pause & lpa register */
4570 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4571 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4572 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4573 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4574 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4575 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4576 .serdes_irq_status = mv88e6390_serdes_irq_status,
4577 .gpio_ops = &mv88e6352_gpio_ops,
4578 .avb_ops = &mv88e6390_avb_ops,
4579 .ptp_ops = &mv88e6352_ptp_ops,
4580 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4581 .serdes_get_strings = mv88e6390_serdes_get_strings,
4582 .serdes_get_stats = mv88e6390_serdes_get_stats,
4583 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4584 .serdes_get_regs = mv88e6390_serdes_get_regs,
4585 .phylink_validate = mv88e6390_phylink_validate,
4586 };
4587
4588 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4589 /* MV88E6XXX_FAMILY_6390 */
4590 .setup_errata = mv88e6390_setup_errata,
4591 .irl_init_all = mv88e6390_g2_irl_init_all,
4592 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4593 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4594 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4595 .phy_read = mv88e6xxx_g2_smi_phy_read,
4596 .phy_write = mv88e6xxx_g2_smi_phy_write,
4597 .port_set_link = mv88e6xxx_port_set_link,
4598 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4599 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4600 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4601 .port_tag_remap = mv88e6390_port_tag_remap,
4602 .port_set_policy = mv88e6352_port_set_policy,
4603 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4604 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4605 .port_set_ether_type = mv88e6351_port_set_ether_type,
4606 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4607 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4608 .port_pause_limit = mv88e6390_port_pause_limit,
4609 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4610 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4611 .port_get_cmode = mv88e6352_port_get_cmode,
4612 .port_set_cmode = mv88e6390x_port_set_cmode,
4613 .port_setup_message_port = mv88e6xxx_setup_message_port,
4614 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4615 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4616 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4617 .stats_get_strings = mv88e6320_stats_get_strings,
4618 .stats_get_stats = mv88e6390_stats_get_stats,
4619 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4620 .set_egress_port = mv88e6390_g1_set_egress_port,
4621 .watchdog_ops = &mv88e6390_watchdog_ops,
4622 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4623 .pot_clear = mv88e6xxx_g2_pot_clear,
4624 .reset = mv88e6352_g1_reset,
4625 .rmu_disable = mv88e6390_g1_rmu_disable,
4626 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4627 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4628 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4629 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4630 .serdes_power = mv88e6390_serdes_power,
4631 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4632 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4633 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4634 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4635 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4636 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4637 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4638 .serdes_irq_status = mv88e6390_serdes_irq_status,
4639 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4640 .serdes_get_strings = mv88e6390_serdes_get_strings,
4641 .serdes_get_stats = mv88e6390_serdes_get_stats,
4642 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4643 .serdes_get_regs = mv88e6390_serdes_get_regs,
4644 .gpio_ops = &mv88e6352_gpio_ops,
4645 .avb_ops = &mv88e6390_avb_ops,
4646 .ptp_ops = &mv88e6352_ptp_ops,
4647 .phylink_validate = mv88e6390x_phylink_validate,
4648 };
4649
4650 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4651 [MV88E6085] = {
4652 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4653 .family = MV88E6XXX_FAMILY_6097,
4654 .name = "Marvell 88E6085",
4655 .num_databases = 4096,
4656 .num_macs = 8192,
4657 .num_ports = 10,
4658 .num_internal_phys = 5,
4659 .max_vid = 4095,
4660 .port_base_addr = 0x10,
4661 .phy_base_addr = 0x0,
4662 .global1_addr = 0x1b,
4663 .global2_addr = 0x1c,
4664 .age_time_coeff = 15000,
4665 .g1_irqs = 8,
4666 .g2_irqs = 10,
4667 .atu_move_port_mask = 0xf,
4668 .pvt = true,
4669 .multi_chip = true,
4670 .tag_protocol = DSA_TAG_PROTO_DSA,
4671 .ops = &mv88e6085_ops,
4672 },
4673
4674 [MV88E6095] = {
4675 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4676 .family = MV88E6XXX_FAMILY_6095,
4677 .name = "Marvell 88E6095/88E6095F",
4678 .num_databases = 256,
4679 .num_macs = 8192,
4680 .num_ports = 11,
4681 .num_internal_phys = 0,
4682 .max_vid = 4095,
4683 .port_base_addr = 0x10,
4684 .phy_base_addr = 0x0,
4685 .global1_addr = 0x1b,
4686 .global2_addr = 0x1c,
4687 .age_time_coeff = 15000,
4688 .g1_irqs = 8,
4689 .atu_move_port_mask = 0xf,
4690 .multi_chip = true,
4691 .tag_protocol = DSA_TAG_PROTO_DSA,
4692 .ops = &mv88e6095_ops,
4693 },
4694
4695 [MV88E6097] = {
4696 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4697 .family = MV88E6XXX_FAMILY_6097,
4698 .name = "Marvell 88E6097/88E6097F",
4699 .num_databases = 4096,
4700 .num_macs = 8192,
4701 .num_ports = 11,
4702 .num_internal_phys = 8,
4703 .max_vid = 4095,
4704 .port_base_addr = 0x10,
4705 .phy_base_addr = 0x0,
4706 .global1_addr = 0x1b,
4707 .global2_addr = 0x1c,
4708 .age_time_coeff = 15000,
4709 .g1_irqs = 8,
4710 .g2_irqs = 10,
4711 .atu_move_port_mask = 0xf,
4712 .pvt = true,
4713 .multi_chip = true,
4714 .tag_protocol = DSA_TAG_PROTO_EDSA,
4715 .ops = &mv88e6097_ops,
4716 },
4717
4718 [MV88E6123] = {
4719 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4720 .family = MV88E6XXX_FAMILY_6165,
4721 .name = "Marvell 88E6123",
4722 .num_databases = 4096,
4723 .num_macs = 1024,
4724 .num_ports = 3,
4725 .num_internal_phys = 5,
4726 .max_vid = 4095,
4727 .port_base_addr = 0x10,
4728 .phy_base_addr = 0x0,
4729 .global1_addr = 0x1b,
4730 .global2_addr = 0x1c,
4731 .age_time_coeff = 15000,
4732 .g1_irqs = 9,
4733 .g2_irqs = 10,
4734 .atu_move_port_mask = 0xf,
4735 .pvt = true,
4736 .multi_chip = true,
4737 .tag_protocol = DSA_TAG_PROTO_EDSA,
4738 .ops = &mv88e6123_ops,
4739 },
4740
4741 [MV88E6131] = {
4742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4743 .family = MV88E6XXX_FAMILY_6185,
4744 .name = "Marvell 88E6131",
4745 .num_databases = 256,
4746 .num_macs = 8192,
4747 .num_ports = 8,
4748 .num_internal_phys = 0,
4749 .max_vid = 4095,
4750 .port_base_addr = 0x10,
4751 .phy_base_addr = 0x0,
4752 .global1_addr = 0x1b,
4753 .global2_addr = 0x1c,
4754 .age_time_coeff = 15000,
4755 .g1_irqs = 9,
4756 .atu_move_port_mask = 0xf,
4757 .multi_chip = true,
4758 .tag_protocol = DSA_TAG_PROTO_DSA,
4759 .ops = &mv88e6131_ops,
4760 },
4761
4762 [MV88E6141] = {
4763 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4764 .family = MV88E6XXX_FAMILY_6341,
4765 .name = "Marvell 88E6141",
4766 .num_databases = 4096,
4767 .num_macs = 2048,
4768 .num_ports = 6,
4769 .num_internal_phys = 5,
4770 .num_gpio = 11,
4771 .max_vid = 4095,
4772 .port_base_addr = 0x10,
4773 .phy_base_addr = 0x10,
4774 .global1_addr = 0x1b,
4775 .global2_addr = 0x1c,
4776 .age_time_coeff = 3750,
4777 .atu_move_port_mask = 0x1f,
4778 .g1_irqs = 9,
4779 .g2_irqs = 10,
4780 .pvt = true,
4781 .multi_chip = true,
4782 .tag_protocol = DSA_TAG_PROTO_EDSA,
4783 .ops = &mv88e6141_ops,
4784 },
4785
4786 [MV88E6161] = {
4787 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4788 .family = MV88E6XXX_FAMILY_6165,
4789 .name = "Marvell 88E6161",
4790 .num_databases = 4096,
4791 .num_macs = 1024,
4792 .num_ports = 6,
4793 .num_internal_phys = 5,
4794 .max_vid = 4095,
4795 .port_base_addr = 0x10,
4796 .phy_base_addr = 0x0,
4797 .global1_addr = 0x1b,
4798 .global2_addr = 0x1c,
4799 .age_time_coeff = 15000,
4800 .g1_irqs = 9,
4801 .g2_irqs = 10,
4802 .atu_move_port_mask = 0xf,
4803 .pvt = true,
4804 .multi_chip = true,
4805 .tag_protocol = DSA_TAG_PROTO_EDSA,
4806 .ptp_support = true,
4807 .ops = &mv88e6161_ops,
4808 },
4809
4810 [MV88E6165] = {
4811 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4812 .family = MV88E6XXX_FAMILY_6165,
4813 .name = "Marvell 88E6165",
4814 .num_databases = 4096,
4815 .num_macs = 8192,
4816 .num_ports = 6,
4817 .num_internal_phys = 0,
4818 .max_vid = 4095,
4819 .port_base_addr = 0x10,
4820 .phy_base_addr = 0x0,
4821 .global1_addr = 0x1b,
4822 .global2_addr = 0x1c,
4823 .age_time_coeff = 15000,
4824 .g1_irqs = 9,
4825 .g2_irqs = 10,
4826 .atu_move_port_mask = 0xf,
4827 .pvt = true,
4828 .multi_chip = true,
4829 .tag_protocol = DSA_TAG_PROTO_DSA,
4830 .ptp_support = true,
4831 .ops = &mv88e6165_ops,
4832 },
4833
4834 [MV88E6171] = {
4835 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4836 .family = MV88E6XXX_FAMILY_6351,
4837 .name = "Marvell 88E6171",
4838 .num_databases = 4096,
4839 .num_macs = 8192,
4840 .num_ports = 7,
4841 .num_internal_phys = 5,
4842 .max_vid = 4095,
4843 .port_base_addr = 0x10,
4844 .phy_base_addr = 0x0,
4845 .global1_addr = 0x1b,
4846 .global2_addr = 0x1c,
4847 .age_time_coeff = 15000,
4848 .g1_irqs = 9,
4849 .g2_irqs = 10,
4850 .atu_move_port_mask = 0xf,
4851 .pvt = true,
4852 .multi_chip = true,
4853 .tag_protocol = DSA_TAG_PROTO_EDSA,
4854 .ops = &mv88e6171_ops,
4855 },
4856
4857 [MV88E6172] = {
4858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4859 .family = MV88E6XXX_FAMILY_6352,
4860 .name = "Marvell 88E6172",
4861 .num_databases = 4096,
4862 .num_macs = 8192,
4863 .num_ports = 7,
4864 .num_internal_phys = 5,
4865 .num_gpio = 15,
4866 .max_vid = 4095,
4867 .port_base_addr = 0x10,
4868 .phy_base_addr = 0x0,
4869 .global1_addr = 0x1b,
4870 .global2_addr = 0x1c,
4871 .age_time_coeff = 15000,
4872 .g1_irqs = 9,
4873 .g2_irqs = 10,
4874 .atu_move_port_mask = 0xf,
4875 .pvt = true,
4876 .multi_chip = true,
4877 .tag_protocol = DSA_TAG_PROTO_EDSA,
4878 .ops = &mv88e6172_ops,
4879 },
4880
4881 [MV88E6175] = {
4882 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4883 .family = MV88E6XXX_FAMILY_6351,
4884 .name = "Marvell 88E6175",
4885 .num_databases = 4096,
4886 .num_macs = 8192,
4887 .num_ports = 7,
4888 .num_internal_phys = 5,
4889 .max_vid = 4095,
4890 .port_base_addr = 0x10,
4891 .phy_base_addr = 0x0,
4892 .global1_addr = 0x1b,
4893 .global2_addr = 0x1c,
4894 .age_time_coeff = 15000,
4895 .g1_irqs = 9,
4896 .g2_irqs = 10,
4897 .atu_move_port_mask = 0xf,
4898 .pvt = true,
4899 .multi_chip = true,
4900 .tag_protocol = DSA_TAG_PROTO_EDSA,
4901 .ops = &mv88e6175_ops,
4902 },
4903
4904 [MV88E6176] = {
4905 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4906 .family = MV88E6XXX_FAMILY_6352,
4907 .name = "Marvell 88E6176",
4908 .num_databases = 4096,
4909 .num_macs = 8192,
4910 .num_ports = 7,
4911 .num_internal_phys = 5,
4912 .num_gpio = 15,
4913 .max_vid = 4095,
4914 .port_base_addr = 0x10,
4915 .phy_base_addr = 0x0,
4916 .global1_addr = 0x1b,
4917 .global2_addr = 0x1c,
4918 .age_time_coeff = 15000,
4919 .g1_irqs = 9,
4920 .g2_irqs = 10,
4921 .atu_move_port_mask = 0xf,
4922 .pvt = true,
4923 .multi_chip = true,
4924 .tag_protocol = DSA_TAG_PROTO_EDSA,
4925 .ops = &mv88e6176_ops,
4926 },
4927
4928 [MV88E6185] = {
4929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4930 .family = MV88E6XXX_FAMILY_6185,
4931 .name = "Marvell 88E6185",
4932 .num_databases = 256,
4933 .num_macs = 8192,
4934 .num_ports = 10,
4935 .num_internal_phys = 0,
4936 .max_vid = 4095,
4937 .port_base_addr = 0x10,
4938 .phy_base_addr = 0x0,
4939 .global1_addr = 0x1b,
4940 .global2_addr = 0x1c,
4941 .age_time_coeff = 15000,
4942 .g1_irqs = 8,
4943 .atu_move_port_mask = 0xf,
4944 .multi_chip = true,
4945 .tag_protocol = DSA_TAG_PROTO_EDSA,
4946 .ops = &mv88e6185_ops,
4947 },
4948
4949 [MV88E6190] = {
4950 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4951 .family = MV88E6XXX_FAMILY_6390,
4952 .name = "Marvell 88E6190",
4953 .num_databases = 4096,
4954 .num_macs = 16384,
4955 .num_ports = 11, /* 10 + Z80 */
4956 .num_internal_phys = 9,
4957 .num_gpio = 16,
4958 .max_vid = 8191,
4959 .port_base_addr = 0x0,
4960 .phy_base_addr = 0x0,
4961 .global1_addr = 0x1b,
4962 .global2_addr = 0x1c,
4963 .tag_protocol = DSA_TAG_PROTO_DSA,
4964 .age_time_coeff = 3750,
4965 .g1_irqs = 9,
4966 .g2_irqs = 14,
4967 .pvt = true,
4968 .multi_chip = true,
4969 .atu_move_port_mask = 0x1f,
4970 .ops = &mv88e6190_ops,
4971 },
4972
4973 [MV88E6190X] = {
4974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4975 .family = MV88E6XXX_FAMILY_6390,
4976 .name = "Marvell 88E6190X",
4977 .num_databases = 4096,
4978 .num_macs = 16384,
4979 .num_ports = 11, /* 10 + Z80 */
4980 .num_internal_phys = 9,
4981 .num_gpio = 16,
4982 .max_vid = 8191,
4983 .port_base_addr = 0x0,
4984 .phy_base_addr = 0x0,
4985 .global1_addr = 0x1b,
4986 .global2_addr = 0x1c,
4987 .age_time_coeff = 3750,
4988 .g1_irqs = 9,
4989 .g2_irqs = 14,
4990 .atu_move_port_mask = 0x1f,
4991 .pvt = true,
4992 .multi_chip = true,
4993 .tag_protocol = DSA_TAG_PROTO_DSA,
4994 .ops = &mv88e6190x_ops,
4995 },
4996
4997 [MV88E6191] = {
4998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4999 .family = MV88E6XXX_FAMILY_6390,
5000 .name = "Marvell 88E6191",
5001 .num_databases = 4096,
5002 .num_macs = 16384,
5003 .num_ports = 11, /* 10 + Z80 */
5004 .num_internal_phys = 9,
5005 .max_vid = 8191,
5006 .port_base_addr = 0x0,
5007 .phy_base_addr = 0x0,
5008 .global1_addr = 0x1b,
5009 .global2_addr = 0x1c,
5010 .age_time_coeff = 3750,
5011 .g1_irqs = 9,
5012 .g2_irqs = 14,
5013 .atu_move_port_mask = 0x1f,
5014 .pvt = true,
5015 .multi_chip = true,
5016 .tag_protocol = DSA_TAG_PROTO_DSA,
5017 .ptp_support = true,
5018 .ops = &mv88e6191_ops,
5019 },
5020
5021 [MV88E6220] = {
5022 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5023 .family = MV88E6XXX_FAMILY_6250,
5024 .name = "Marvell 88E6220",
5025 .num_databases = 64,
5026
5027 /* Ports 2-4 are not routed to pins
5028 * => usable ports 0, 1, 5, 6
5029 */
5030 .num_ports = 7,
5031 .num_internal_phys = 2,
5032 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5033 .max_vid = 4095,
5034 .port_base_addr = 0x08,
5035 .phy_base_addr = 0x00,
5036 .global1_addr = 0x0f,
5037 .global2_addr = 0x07,
5038 .age_time_coeff = 15000,
5039 .g1_irqs = 9,
5040 .g2_irqs = 10,
5041 .atu_move_port_mask = 0xf,
5042 .dual_chip = true,
5043 .tag_protocol = DSA_TAG_PROTO_DSA,
5044 .ptp_support = true,
5045 .ops = &mv88e6250_ops,
5046 },
5047
5048 [MV88E6240] = {
5049 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5050 .family = MV88E6XXX_FAMILY_6352,
5051 .name = "Marvell 88E6240",
5052 .num_databases = 4096,
5053 .num_macs = 8192,
5054 .num_ports = 7,
5055 .num_internal_phys = 5,
5056 .num_gpio = 15,
5057 .max_vid = 4095,
5058 .port_base_addr = 0x10,
5059 .phy_base_addr = 0x0,
5060 .global1_addr = 0x1b,
5061 .global2_addr = 0x1c,
5062 .age_time_coeff = 15000,
5063 .g1_irqs = 9,
5064 .g2_irqs = 10,
5065 .atu_move_port_mask = 0xf,
5066 .pvt = true,
5067 .multi_chip = true,
5068 .tag_protocol = DSA_TAG_PROTO_EDSA,
5069 .ptp_support = true,
5070 .ops = &mv88e6240_ops,
5071 },
5072
5073 [MV88E6250] = {
5074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5075 .family = MV88E6XXX_FAMILY_6250,
5076 .name = "Marvell 88E6250",
5077 .num_databases = 64,
5078 .num_ports = 7,
5079 .num_internal_phys = 5,
5080 .max_vid = 4095,
5081 .port_base_addr = 0x08,
5082 .phy_base_addr = 0x00,
5083 .global1_addr = 0x0f,
5084 .global2_addr = 0x07,
5085 .age_time_coeff = 15000,
5086 .g1_irqs = 9,
5087 .g2_irqs = 10,
5088 .atu_move_port_mask = 0xf,
5089 .dual_chip = true,
5090 .tag_protocol = DSA_TAG_PROTO_DSA,
5091 .ptp_support = true,
5092 .ops = &mv88e6250_ops,
5093 },
5094
5095 [MV88E6290] = {
5096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5097 .family = MV88E6XXX_FAMILY_6390,
5098 .name = "Marvell 88E6290",
5099 .num_databases = 4096,
5100 .num_ports = 11, /* 10 + Z80 */
5101 .num_internal_phys = 9,
5102 .num_gpio = 16,
5103 .max_vid = 8191,
5104 .port_base_addr = 0x0,
5105 .phy_base_addr = 0x0,
5106 .global1_addr = 0x1b,
5107 .global2_addr = 0x1c,
5108 .age_time_coeff = 3750,
5109 .g1_irqs = 9,
5110 .g2_irqs = 14,
5111 .atu_move_port_mask = 0x1f,
5112 .pvt = true,
5113 .multi_chip = true,
5114 .tag_protocol = DSA_TAG_PROTO_DSA,
5115 .ptp_support = true,
5116 .ops = &mv88e6290_ops,
5117 },
5118
5119 [MV88E6320] = {
5120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5121 .family = MV88E6XXX_FAMILY_6320,
5122 .name = "Marvell 88E6320",
5123 .num_databases = 4096,
5124 .num_macs = 8192,
5125 .num_ports = 7,
5126 .num_internal_phys = 5,
5127 .num_gpio = 15,
5128 .max_vid = 4095,
5129 .port_base_addr = 0x10,
5130 .phy_base_addr = 0x0,
5131 .global1_addr = 0x1b,
5132 .global2_addr = 0x1c,
5133 .age_time_coeff = 15000,
5134 .g1_irqs = 8,
5135 .g2_irqs = 10,
5136 .atu_move_port_mask = 0xf,
5137 .pvt = true,
5138 .multi_chip = true,
5139 .tag_protocol = DSA_TAG_PROTO_EDSA,
5140 .ptp_support = true,
5141 .ops = &mv88e6320_ops,
5142 },
5143
5144 [MV88E6321] = {
5145 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5146 .family = MV88E6XXX_FAMILY_6320,
5147 .name = "Marvell 88E6321",
5148 .num_databases = 4096,
5149 .num_macs = 8192,
5150 .num_ports = 7,
5151 .num_internal_phys = 5,
5152 .num_gpio = 15,
5153 .max_vid = 4095,
5154 .port_base_addr = 0x10,
5155 .phy_base_addr = 0x0,
5156 .global1_addr = 0x1b,
5157 .global2_addr = 0x1c,
5158 .age_time_coeff = 15000,
5159 .g1_irqs = 8,
5160 .g2_irqs = 10,
5161 .atu_move_port_mask = 0xf,
5162 .multi_chip = true,
5163 .tag_protocol = DSA_TAG_PROTO_EDSA,
5164 .ptp_support = true,
5165 .ops = &mv88e6321_ops,
5166 },
5167
5168 [MV88E6341] = {
5169 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5170 .family = MV88E6XXX_FAMILY_6341,
5171 .name = "Marvell 88E6341",
5172 .num_databases = 4096,
5173 .num_macs = 2048,
5174 .num_internal_phys = 5,
5175 .num_ports = 6,
5176 .num_gpio = 11,
5177 .max_vid = 4095,
5178 .port_base_addr = 0x10,
5179 .phy_base_addr = 0x10,
5180 .global1_addr = 0x1b,
5181 .global2_addr = 0x1c,
5182 .age_time_coeff = 3750,
5183 .atu_move_port_mask = 0x1f,
5184 .g1_irqs = 9,
5185 .g2_irqs = 10,
5186 .pvt = true,
5187 .multi_chip = true,
5188 .tag_protocol = DSA_TAG_PROTO_EDSA,
5189 .ptp_support = true,
5190 .ops = &mv88e6341_ops,
5191 },
5192
5193 [MV88E6350] = {
5194 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5195 .family = MV88E6XXX_FAMILY_6351,
5196 .name = "Marvell 88E6350",
5197 .num_databases = 4096,
5198 .num_macs = 8192,
5199 .num_ports = 7,
5200 .num_internal_phys = 5,
5201 .max_vid = 4095,
5202 .port_base_addr = 0x10,
5203 .phy_base_addr = 0x0,
5204 .global1_addr = 0x1b,
5205 .global2_addr = 0x1c,
5206 .age_time_coeff = 15000,
5207 .g1_irqs = 9,
5208 .g2_irqs = 10,
5209 .atu_move_port_mask = 0xf,
5210 .pvt = true,
5211 .multi_chip = true,
5212 .tag_protocol = DSA_TAG_PROTO_EDSA,
5213 .ops = &mv88e6350_ops,
5214 },
5215
5216 [MV88E6351] = {
5217 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5218 .family = MV88E6XXX_FAMILY_6351,
5219 .name = "Marvell 88E6351",
5220 .num_databases = 4096,
5221 .num_macs = 8192,
5222 .num_ports = 7,
5223 .num_internal_phys = 5,
5224 .max_vid = 4095,
5225 .port_base_addr = 0x10,
5226 .phy_base_addr = 0x0,
5227 .global1_addr = 0x1b,
5228 .global2_addr = 0x1c,
5229 .age_time_coeff = 15000,
5230 .g1_irqs = 9,
5231 .g2_irqs = 10,
5232 .atu_move_port_mask = 0xf,
5233 .pvt = true,
5234 .multi_chip = true,
5235 .tag_protocol = DSA_TAG_PROTO_EDSA,
5236 .ops = &mv88e6351_ops,
5237 },
5238
5239 [MV88E6352] = {
5240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5241 .family = MV88E6XXX_FAMILY_6352,
5242 .name = "Marvell 88E6352",
5243 .num_databases = 4096,
5244 .num_macs = 8192,
5245 .num_ports = 7,
5246 .num_internal_phys = 5,
5247 .num_gpio = 15,
5248 .max_vid = 4095,
5249 .port_base_addr = 0x10,
5250 .phy_base_addr = 0x0,
5251 .global1_addr = 0x1b,
5252 .global2_addr = 0x1c,
5253 .age_time_coeff = 15000,
5254 .g1_irqs = 9,
5255 .g2_irqs = 10,
5256 .atu_move_port_mask = 0xf,
5257 .pvt = true,
5258 .multi_chip = true,
5259 .tag_protocol = DSA_TAG_PROTO_EDSA,
5260 .ptp_support = true,
5261 .ops = &mv88e6352_ops,
5262 },
5263 [MV88E6390] = {
5264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5265 .family = MV88E6XXX_FAMILY_6390,
5266 .name = "Marvell 88E6390",
5267 .num_databases = 4096,
5268 .num_macs = 16384,
5269 .num_ports = 11, /* 10 + Z80 */
5270 .num_internal_phys = 9,
5271 .num_gpio = 16,
5272 .max_vid = 8191,
5273 .port_base_addr = 0x0,
5274 .phy_base_addr = 0x0,
5275 .global1_addr = 0x1b,
5276 .global2_addr = 0x1c,
5277 .age_time_coeff = 3750,
5278 .g1_irqs = 9,
5279 .g2_irqs = 14,
5280 .atu_move_port_mask = 0x1f,
5281 .pvt = true,
5282 .multi_chip = true,
5283 .tag_protocol = DSA_TAG_PROTO_DSA,
5284 .ptp_support = true,
5285 .ops = &mv88e6390_ops,
5286 },
5287 [MV88E6390X] = {
5288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5289 .family = MV88E6XXX_FAMILY_6390,
5290 .name = "Marvell 88E6390X",
5291 .num_databases = 4096,
5292 .num_macs = 16384,
5293 .num_ports = 11, /* 10 + Z80 */
5294 .num_internal_phys = 9,
5295 .num_gpio = 16,
5296 .max_vid = 8191,
5297 .port_base_addr = 0x0,
5298 .phy_base_addr = 0x0,
5299 .global1_addr = 0x1b,
5300 .global2_addr = 0x1c,
5301 .age_time_coeff = 3750,
5302 .g1_irqs = 9,
5303 .g2_irqs = 14,
5304 .atu_move_port_mask = 0x1f,
5305 .pvt = true,
5306 .multi_chip = true,
5307 .tag_protocol = DSA_TAG_PROTO_DSA,
5308 .ptp_support = true,
5309 .ops = &mv88e6390x_ops,
5310 },
5311 };
5312
5313 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5314 {
5315 int i;
5316
5317 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5318 if (mv88e6xxx_table[i].prod_num == prod_num)
5319 return &mv88e6xxx_table[i];
5320
5321 return NULL;
5322 }
5323
5324 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5325 {
5326 const struct mv88e6xxx_info *info;
5327 unsigned int prod_num, rev;
5328 u16 id;
5329 int err;
5330
5331 mv88e6xxx_reg_lock(chip);
5332 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5333 mv88e6xxx_reg_unlock(chip);
5334 if (err)
5335 return err;
5336
5337 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5338 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5339
5340 info = mv88e6xxx_lookup_info(prod_num);
5341 if (!info)
5342 return -ENODEV;
5343
5344 /* Update the compatible info with the probed one */
5345 chip->info = info;
5346
5347 err = mv88e6xxx_g2_require(chip);
5348 if (err)
5349 return err;
5350
5351 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5352 chip->info->prod_num, chip->info->name, rev);
5353
5354 return 0;
5355 }
5356
5357 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5358 {
5359 struct mv88e6xxx_chip *chip;
5360
5361 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5362 if (!chip)
5363 return NULL;
5364
5365 chip->dev = dev;
5366
5367 mutex_init(&chip->reg_lock);
5368 INIT_LIST_HEAD(&chip->mdios);
5369 idr_init(&chip->policies);
5370
5371 return chip;
5372 }
5373
5374 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5375 int port,
5376 enum dsa_tag_protocol m)
5377 {
5378 struct mv88e6xxx_chip *chip = ds->priv;
5379
5380 return chip->info->tag_protocol;
5381 }
5382
5383 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5384 const struct switchdev_obj_port_mdb *mdb)
5385 {
5386 /* We don't need any dynamic resource from the kernel (yet),
5387 * so skip the prepare phase.
5388 */
5389
5390 return 0;
5391 }
5392
5393 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5394 const struct switchdev_obj_port_mdb *mdb)
5395 {
5396 struct mv88e6xxx_chip *chip = ds->priv;
5397
5398 mv88e6xxx_reg_lock(chip);
5399 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5400 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5401 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5402 port);
5403 mv88e6xxx_reg_unlock(chip);
5404 }
5405
5406 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5407 const struct switchdev_obj_port_mdb *mdb)
5408 {
5409 struct mv88e6xxx_chip *chip = ds->priv;
5410 int err;
5411
5412 mv88e6xxx_reg_lock(chip);
5413 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5414 mv88e6xxx_reg_unlock(chip);
5415
5416 return err;
5417 }
5418
5419 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5420 struct dsa_mall_mirror_tc_entry *mirror,
5421 bool ingress)
5422 {
5423 enum mv88e6xxx_egress_direction direction = ingress ?
5424 MV88E6XXX_EGRESS_DIR_INGRESS :
5425 MV88E6XXX_EGRESS_DIR_EGRESS;
5426 struct mv88e6xxx_chip *chip = ds->priv;
5427 bool other_mirrors = false;
5428 int i;
5429 int err;
5430
5431 if (!chip->info->ops->set_egress_port)
5432 return -EOPNOTSUPP;
5433
5434 mutex_lock(&chip->reg_lock);
5435 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5436 mirror->to_local_port) {
5437 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5438 other_mirrors |= ingress ?
5439 chip->ports[i].mirror_ingress :
5440 chip->ports[i].mirror_egress;
5441
5442 /* Can't change egress port when other mirror is active */
5443 if (other_mirrors) {
5444 err = -EBUSY;
5445 goto out;
5446 }
5447
5448 err = chip->info->ops->set_egress_port(chip,
5449 direction,
5450 mirror->to_local_port);
5451 if (err)
5452 goto out;
5453 }
5454
5455 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5456 out:
5457 mutex_unlock(&chip->reg_lock);
5458
5459 return err;
5460 }
5461
5462 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5463 struct dsa_mall_mirror_tc_entry *mirror)
5464 {
5465 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5466 MV88E6XXX_EGRESS_DIR_INGRESS :
5467 MV88E6XXX_EGRESS_DIR_EGRESS;
5468 struct mv88e6xxx_chip *chip = ds->priv;
5469 bool other_mirrors = false;
5470 int i;
5471
5472 mutex_lock(&chip->reg_lock);
5473 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5474 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5475
5476 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5477 other_mirrors |= mirror->ingress ?
5478 chip->ports[i].mirror_ingress :
5479 chip->ports[i].mirror_egress;
5480
5481 /* Reset egress port when no other mirror is active */
5482 if (!other_mirrors) {
5483 if (chip->info->ops->set_egress_port(chip,
5484 direction,
5485 dsa_upstream_port(ds,
5486 port)))
5487 dev_err(ds->dev, "failed to set egress port\n");
5488 }
5489
5490 mutex_unlock(&chip->reg_lock);
5491 }
5492
5493 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5494 bool unicast, bool multicast)
5495 {
5496 struct mv88e6xxx_chip *chip = ds->priv;
5497 int err = -EOPNOTSUPP;
5498
5499 mv88e6xxx_reg_lock(chip);
5500 if (chip->info->ops->port_set_egress_floods)
5501 err = chip->info->ops->port_set_egress_floods(chip, port,
5502 unicast,
5503 multicast);
5504 mv88e6xxx_reg_unlock(chip);
5505
5506 return err;
5507 }
5508
5509 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5510 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
5511 .setup = mv88e6xxx_setup,
5512 .teardown = mv88e6xxx_teardown,
5513 .phylink_validate = mv88e6xxx_validate,
5514 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5515 .phylink_mac_config = mv88e6xxx_mac_config,
5516 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5517 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
5518 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
5519 .get_strings = mv88e6xxx_get_strings,
5520 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
5521 .get_sset_count = mv88e6xxx_get_sset_count,
5522 .port_enable = mv88e6xxx_port_enable,
5523 .port_disable = mv88e6xxx_port_disable,
5524 .get_mac_eee = mv88e6xxx_get_mac_eee,
5525 .set_mac_eee = mv88e6xxx_set_mac_eee,
5526 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
5527 .get_eeprom = mv88e6xxx_get_eeprom,
5528 .set_eeprom = mv88e6xxx_set_eeprom,
5529 .get_regs_len = mv88e6xxx_get_regs_len,
5530 .get_regs = mv88e6xxx_get_regs,
5531 .get_rxnfc = mv88e6xxx_get_rxnfc,
5532 .set_rxnfc = mv88e6xxx_set_rxnfc,
5533 .set_ageing_time = mv88e6xxx_set_ageing_time,
5534 .port_bridge_join = mv88e6xxx_port_bridge_join,
5535 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
5536 .port_egress_floods = mv88e6xxx_port_egress_floods,
5537 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
5538 .port_fast_age = mv88e6xxx_port_fast_age,
5539 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
5540 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
5541 .port_vlan_add = mv88e6xxx_port_vlan_add,
5542 .port_vlan_del = mv88e6xxx_port_vlan_del,
5543 .port_fdb_add = mv88e6xxx_port_fdb_add,
5544 .port_fdb_del = mv88e6xxx_port_fdb_del,
5545 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
5546 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
5547 .port_mdb_add = mv88e6xxx_port_mdb_add,
5548 .port_mdb_del = mv88e6xxx_port_mdb_del,
5549 .port_mirror_add = mv88e6xxx_port_mirror_add,
5550 .port_mirror_del = mv88e6xxx_port_mirror_del,
5551 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
5552 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5553 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
5554 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
5555 .port_txtstamp = mv88e6xxx_port_txtstamp,
5556 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
5557 .get_ts_info = mv88e6xxx_get_ts_info,
5558 .devlink_param_get = mv88e6xxx_devlink_param_get,
5559 .devlink_param_set = mv88e6xxx_devlink_param_set,
5560 };
5561
5562 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5563 {
5564 struct device *dev = chip->dev;
5565 struct dsa_switch *ds;
5566
5567 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5568 if (!ds)
5569 return -ENOMEM;
5570
5571 ds->dev = dev;
5572 ds->num_ports = mv88e6xxx_num_ports(chip);
5573 ds->priv = chip;
5574 ds->dev = dev;
5575 ds->ops = &mv88e6xxx_switch_ops;
5576 ds->ageing_time_min = chip->info->age_time_coeff;
5577 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5578
5579 dev_set_drvdata(dev, ds);
5580
5581 return dsa_register_switch(ds);
5582 }
5583
5584 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5585 {
5586 dsa_unregister_switch(chip->ds);
5587 }
5588
5589 static const void *pdata_device_get_match_data(struct device *dev)
5590 {
5591 const struct of_device_id *matches = dev->driver->of_match_table;
5592 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5593
5594 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5595 matches++) {
5596 if (!strcmp(pdata->compatible, matches->compatible))
5597 return matches->data;
5598 }
5599 return NULL;
5600 }
5601
5602 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5603 * would be lost after a power cycle so prevent it to be suspended.
5604 */
5605 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5606 {
5607 return -EOPNOTSUPP;
5608 }
5609
5610 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5611 {
5612 return 0;
5613 }
5614
5615 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5616
5617 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5618 {
5619 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5620 const struct mv88e6xxx_info *compat_info = NULL;
5621 struct device *dev = &mdiodev->dev;
5622 struct device_node *np = dev->of_node;
5623 struct mv88e6xxx_chip *chip;
5624 int port;
5625 int err;
5626
5627 if (!np && !pdata)
5628 return -EINVAL;
5629
5630 if (np)
5631 compat_info = of_device_get_match_data(dev);
5632
5633 if (pdata) {
5634 compat_info = pdata_device_get_match_data(dev);
5635
5636 if (!pdata->netdev)
5637 return -EINVAL;
5638
5639 for (port = 0; port < DSA_MAX_PORTS; port++) {
5640 if (!(pdata->enabled_ports & (1 << port)))
5641 continue;
5642 if (strcmp(pdata->cd.port_names[port], "cpu"))
5643 continue;
5644 pdata->cd.netdev[port] = &pdata->netdev->dev;
5645 break;
5646 }
5647 }
5648
5649 if (!compat_info)
5650 return -EINVAL;
5651
5652 chip = mv88e6xxx_alloc_chip(dev);
5653 if (!chip) {
5654 err = -ENOMEM;
5655 goto out;
5656 }
5657
5658 chip->info = compat_info;
5659
5660 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5661 if (err)
5662 goto out;
5663
5664 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5665 if (IS_ERR(chip->reset)) {
5666 err = PTR_ERR(chip->reset);
5667 goto out;
5668 }
5669 if (chip->reset)
5670 usleep_range(1000, 2000);
5671
5672 err = mv88e6xxx_detect(chip);
5673 if (err)
5674 goto out;
5675
5676 mv88e6xxx_phy_init(chip);
5677
5678 if (chip->info->ops->get_eeprom) {
5679 if (np)
5680 of_property_read_u32(np, "eeprom-length",
5681 &chip->eeprom_len);
5682 else
5683 chip->eeprom_len = pdata->eeprom_len;
5684 }
5685
5686 mv88e6xxx_reg_lock(chip);
5687 err = mv88e6xxx_switch_reset(chip);
5688 mv88e6xxx_reg_unlock(chip);
5689 if (err)
5690 goto out;
5691
5692 if (np) {
5693 chip->irq = of_irq_get(np, 0);
5694 if (chip->irq == -EPROBE_DEFER) {
5695 err = chip->irq;
5696 goto out;
5697 }
5698 }
5699
5700 if (pdata)
5701 chip->irq = pdata->irq;
5702
5703 /* Has to be performed before the MDIO bus is created, because
5704 * the PHYs will link their interrupts to these interrupt
5705 * controllers
5706 */
5707 mv88e6xxx_reg_lock(chip);
5708 if (chip->irq > 0)
5709 err = mv88e6xxx_g1_irq_setup(chip);
5710 else
5711 err = mv88e6xxx_irq_poll_setup(chip);
5712 mv88e6xxx_reg_unlock(chip);
5713
5714 if (err)
5715 goto out;
5716
5717 if (chip->info->g2_irqs > 0) {
5718 err = mv88e6xxx_g2_irq_setup(chip);
5719 if (err)
5720 goto out_g1_irq;
5721 }
5722
5723 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5724 if (err)
5725 goto out_g2_irq;
5726
5727 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5728 if (err)
5729 goto out_g1_atu_prob_irq;
5730
5731 err = mv88e6xxx_mdios_register(chip, np);
5732 if (err)
5733 goto out_g1_vtu_prob_irq;
5734
5735 err = mv88e6xxx_register_switch(chip);
5736 if (err)
5737 goto out_mdio;
5738
5739 return 0;
5740
5741 out_mdio:
5742 mv88e6xxx_mdios_unregister(chip);
5743 out_g1_vtu_prob_irq:
5744 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5745 out_g1_atu_prob_irq:
5746 mv88e6xxx_g1_atu_prob_irq_free(chip);
5747 out_g2_irq:
5748 if (chip->info->g2_irqs > 0)
5749 mv88e6xxx_g2_irq_free(chip);
5750 out_g1_irq:
5751 if (chip->irq > 0)
5752 mv88e6xxx_g1_irq_free(chip);
5753 else
5754 mv88e6xxx_irq_poll_free(chip);
5755 out:
5756 if (pdata)
5757 dev_put(pdata->netdev);
5758
5759 return err;
5760 }
5761
5762 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5763 {
5764 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5765 struct mv88e6xxx_chip *chip = ds->priv;
5766
5767 if (chip->info->ptp_support) {
5768 mv88e6xxx_hwtstamp_free(chip);
5769 mv88e6xxx_ptp_free(chip);
5770 }
5771
5772 mv88e6xxx_phy_destroy(chip);
5773 mv88e6xxx_unregister_switch(chip);
5774 mv88e6xxx_mdios_unregister(chip);
5775
5776 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5777 mv88e6xxx_g1_atu_prob_irq_free(chip);
5778
5779 if (chip->info->g2_irqs > 0)
5780 mv88e6xxx_g2_irq_free(chip);
5781
5782 if (chip->irq > 0)
5783 mv88e6xxx_g1_irq_free(chip);
5784 else
5785 mv88e6xxx_irq_poll_free(chip);
5786 }
5787
5788 static const struct of_device_id mv88e6xxx_of_match[] = {
5789 {
5790 .compatible = "marvell,mv88e6085",
5791 .data = &mv88e6xxx_table[MV88E6085],
5792 },
5793 {
5794 .compatible = "marvell,mv88e6190",
5795 .data = &mv88e6xxx_table[MV88E6190],
5796 },
5797 {
5798 .compatible = "marvell,mv88e6250",
5799 .data = &mv88e6xxx_table[MV88E6250],
5800 },
5801 { /* sentinel */ },
5802 };
5803
5804 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5805
5806 static struct mdio_driver mv88e6xxx_driver = {
5807 .probe = mv88e6xxx_probe,
5808 .remove = mv88e6xxx_remove,
5809 .mdiodrv.driver = {
5810 .name = "mv88e6085",
5811 .of_match_table = mv88e6xxx_of_match,
5812 .pm = &mv88e6xxx_pm_ops,
5813 },
5814 };
5815
5816 mdio_module_driver(mv88e6xxx_driver);
5817
5818 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5819 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5820 MODULE_LICENSE("GPL");
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