drivers/net/dsa/mv88e6xxx/chip.h

   1 /*
   2  * Marvell 88E6xxx Ethernet switch single-chip definition
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef _MV88E6XXX_CHIP_H
  13 #define _MV88E6XXX_CHIP_H
  14
  15 #include <linux/if_vlan.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio/consumer.h>
  18 #include <linux/kthread.h>
  19 #include <linux/phy.h>
  20 #include <linux/ptp_clock_kernel.h>
  21 #include <linux/timecounter.h>
  22 #include <net/dsa.h>
  23
  24 #define MV88E6XXX_N_FID         4096
  25
  26 /* PVT limits for 4-bit port and 5-bit switch */
  27 #define MV88E6XXX_MAX_PVT_SWITCHES      32
  28 #define MV88E6XXX_MAX_PVT_PORTS         16
  29
  30 #define MV88E6XXX_MAX_GPIO      16
  31
  32 enum mv88e6xxx_egress_mode {
  33         MV88E6XXX_EGRESS_MODE_UNMODIFIED,
  34         MV88E6XXX_EGRESS_MODE_UNTAGGED,
  35         MV88E6XXX_EGRESS_MODE_TAGGED,
  36         MV88E6XXX_EGRESS_MODE_ETHERTYPE,
  37 };
  38
  39 enum mv88e6xxx_frame_mode {
  40         MV88E6XXX_FRAME_MODE_NORMAL,
  41         MV88E6XXX_FRAME_MODE_DSA,
  42         MV88E6XXX_FRAME_MODE_PROVIDER,
  43         MV88E6XXX_FRAME_MODE_ETHERTYPE,
  44 };
  45
  46 /* List of supported models */
  47 enum mv88e6xxx_model {
  48         MV88E6085,
  49         MV88E6095,
  50         MV88E6097,
  51         MV88E6123,
  52         MV88E6131,
  53         MV88E6141,
  54         MV88E6161,
  55         MV88E6165,
  56         MV88E6171,
  57         MV88E6172,
  58         MV88E6175,
  59         MV88E6176,
  60         MV88E6185,
  61         MV88E6190,
  62         MV88E6190X,
  63         MV88E6191,
  64         MV88E6240,
  65         MV88E6290,
  66         MV88E6320,
  67         MV88E6321,
  68         MV88E6341,
  69         MV88E6350,
  70         MV88E6351,
  71         MV88E6352,
  72         MV88E6390,
  73         MV88E6390X,
  74 };
  75
  76 enum mv88e6xxx_family {
  77         MV88E6XXX_FAMILY_NONE,
  78         MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
  79         MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
  80         MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
  81         MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
  82         MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
  83         MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
  84         MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
  85         MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
  86         MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
  87         MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
  88 };
  89
  90 struct mv88e6xxx_ops;
  91
  92 struct mv88e6xxx_info {
  93         enum mv88e6xxx_family family;
  94         u16 prod_num;
  95         const char *name;
  96         unsigned int num_databases;
  97         unsigned int num_ports;
  98         unsigned int num_internal_phys;
  99         unsigned int num_gpio;
 100         unsigned int max_vid;
 101         unsigned int port_base_addr;
 102         unsigned int phy_base_addr;
 103         unsigned int global1_addr;
 104         unsigned int global2_addr;
 105         unsigned int age_time_coeff;
 106         unsigned int g1_irqs;
 107         unsigned int g2_irqs;
 108         bool pvt;
 109
 110         /* Multi-chip Addressing Mode.
 111          * Some chips respond to only 2 registers of its own SMI device address
 112          * when it is non-zero, and use indirect access to internal registers.
 113          */
 114         bool multi_chip;
 115         enum dsa_tag_protocol tag_protocol;
 116
 117         /* Mask for FromPort and ToPort value of PortVec used in ATU Move
 118          * operation. 0 means that the ATU Move operation is not supported.
 119          */
 120         u8 atu_move_port_mask;
 121         const struct mv88e6xxx_ops *ops;
 122
 123         /* Supports PTP */
 124         bool ptp_support;
 125 };
 126
 127 struct mv88e6xxx_atu_entry {
 128         u8      state;
 129         bool    trunk;
 130         u16     portvec;
 131         u8      mac[ETH_ALEN];
 132 };
 133
 134 struct mv88e6xxx_vtu_entry {
 135         u16     vid;
 136         u16     fid;
 137         u8      sid;
 138         bool    valid;
 139         u8      member[DSA_MAX_PORTS];
 140         u8      state[DSA_MAX_PORTS];
 141 };
 142
 143 struct mv88e6xxx_bus_ops;
 144 struct mv88e6xxx_irq_ops;
 145 struct mv88e6xxx_gpio_ops;
 146 struct mv88e6xxx_avb_ops;
 147 struct mv88e6xxx_ptp_ops;
 148
 149 struct mv88e6xxx_irq {
 150         u16 masked;
 151         struct irq_chip chip;
 152         struct irq_domain *domain;
 153         unsigned int nirqs;
 154 };
 155
 156 /* state flags for mv88e6xxx_port_hwtstamp::state */
 157 enum {
 158         MV88E6XXX_HWTSTAMP_ENABLED,
 159         MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
 160 };
 161
 162 struct mv88e6xxx_port_hwtstamp {
 163         /* Port index */
 164         int port_id;
 165
 166         /* Timestamping state */
 167         unsigned long state;
 168
 169         /* Resources for receive timestamping */
 170         struct sk_buff_head rx_queue;
 171         struct sk_buff_head rx_queue2;
 172
 173         /* Resources for transmit timestamping */
 174         unsigned long tx_tstamp_start;
 175         struct sk_buff *tx_skb;
 176         u16 tx_seq_id;
 177
 178         /* Current timestamp configuration */
 179         struct hwtstamp_config tstamp_config;
 180 };
 181
 182 struct mv88e6xxx_port {
 183         struct mv88e6xxx_chip *chip;
 184         int port;
 185         u64 serdes_stats[2];
 186         u64 atu_member_violation;
 187         u64 atu_miss_violation;
 188         u64 atu_full_violation;
 189         u64 vtu_member_violation;
 190         u64 vtu_miss_violation;
 191         u8 cmode;
 192         int serdes_irq;
 193 };
 194
 195 struct mv88e6xxx_chip {
 196         const struct mv88e6xxx_info *info;
 197
 198         /* The dsa_switch this private structure is related to */
 199         struct dsa_switch *ds;
 200
 201         /* The device this structure is associated to */
 202         struct device *dev;
 203
 204         /* This mutex protects the access to the switch registers */
 205         struct mutex reg_lock;
 206
 207         /* The MII bus and the address on the bus that is used to
 208          * communication with the switch
 209          */
 210         const struct mv88e6xxx_bus_ops *smi_ops;
 211         struct mii_bus *bus;
 212         int sw_addr;
 213
 214         /* Handles automatic disabling and re-enabling of the PHY
 215          * polling unit.
 216          */
 217         const struct mv88e6xxx_bus_ops *phy_ops;
 218         struct mutex            ppu_mutex;
 219         int                     ppu_disabled;
 220         struct work_struct      ppu_work;
 221         struct timer_list       ppu_timer;
 222
 223         /* This mutex serialises access to the statistics unit.
 224          * Hold this mutex over snapshot + dump sequences.
 225          */
 226         struct mutex    stats_mutex;
 227
 228         /* A switch may have a GPIO line tied to its reset pin. Parse
 229          * this from the device tree, and use it before performing
 230          * switch soft reset.
 231          */
 232         struct gpio_desc *reset;
 233
 234         /* set to size of eeprom if supported by the switch */
 235         u32 eeprom_len;
 236
 237         /* List of mdio busses */
 238         struct list_head mdios;
 239
 240         /* There can be two interrupt controllers, which are chained
 241          * off a GPIO as interrupt source
 242          */
 243         struct mv88e6xxx_irq g1_irq;
 244         struct mv88e6xxx_irq g2_irq;
 245         int irq;
 246         int device_irq;
 247         int watchdog_irq;
 248
 249         int atu_prob_irq;
 250         int vtu_prob_irq;
 251         struct kthread_worker *kworker;
 252         struct kthread_delayed_work irq_poll_work;
 253
 254         /* GPIO resources */
 255         u8 gpio_data[2];
 256
 257         /* This cyclecounter abstracts the switch PTP time.
 258          * reg_lock must be held for any operation that read()s.
 259          */
 260         struct cyclecounter     tstamp_cc;
 261         struct timecounter      tstamp_tc;
 262         struct delayed_work     overflow_work;
 263
 264         struct ptp_clock        *ptp_clock;
 265         struct ptp_clock_info   ptp_clock_info;
 266         struct delayed_work     tai_event_work;
 267         struct ptp_pin_desc     pin_config[MV88E6XXX_MAX_GPIO];
 268         u16 trig_config;
 269         u16 evcap_config;
 270         u16 enable_count;
 271
 272         /* Per-port timestamping resources. */
 273         struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
 274
 275         /* Array of port structures. */
 276         struct mv88e6xxx_port ports[DSA_MAX_PORTS];
 277 };
 278
 279 struct mv88e6xxx_bus_ops {
 280         int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 281         int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 282 };
 283
 284 struct mv88e6xxx_mdio_bus {
 285         struct mii_bus *bus;
 286         struct mv88e6xxx_chip *chip;
 287         struct list_head list;
 288         bool external;
 289 };
 290
 291 struct mv88e6xxx_ops {
 292         /* Switch Setup Errata, called early in the switch setup to
 293          * allow any errata actions to be performed
 294          */
 295         int (*setup_errata)(struct mv88e6xxx_chip *chip);
 296
 297         int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
 298         int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
 299
 300         /* Ingress Rate Limit unit (IRL) operations */
 301         int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
 302
 303         int (*get_eeprom)(struct mv88e6xxx_chip *chip,
 304                           struct ethtool_eeprom *eeprom, u8 *data);
 305         int (*set_eeprom)(struct mv88e6xxx_chip *chip,
 306                           struct ethtool_eeprom *eeprom, u8 *data);
 307
 308         int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
 309
 310         int (*phy_read)(struct mv88e6xxx_chip *chip,
 311                         struct mii_bus *bus,
 312                         int addr, int reg, u16 *val);
 313         int (*phy_write)(struct mv88e6xxx_chip *chip,
 314                          struct mii_bus *bus,
 315                          int addr, int reg, u16 val);
 316
 317         /* Priority Override Table operations */
 318         int (*pot_clear)(struct mv88e6xxx_chip *chip);
 319
 320         /* PHY Polling Unit (PPU) operations */
 321         int (*ppu_enable)(struct mv88e6xxx_chip *chip);
 322         int (*ppu_disable)(struct mv88e6xxx_chip *chip);
 323
 324         /* Switch Software Reset */
 325         int (*reset)(struct mv88e6xxx_chip *chip);
 326
 327         /* RGMII Receive/Transmit Timing Control
 328          * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
 329          */
 330         int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
 331                                     phy_interface_t mode);
 332
 333 #define LINK_FORCED_DOWN        0
 334 #define LINK_FORCED_UP          1
 335 #define LINK_UNFORCED           -2
 336
 337         /* Port's MAC link state
 338          * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
 339          * or LINK_UNFORCED for normal link detection.
 340          */
 341         int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
 342
 343 #define DUPLEX_UNFORCED         -2
 344
 345         /* Port's MAC duplex mode
 346          *
 347          * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
 348          * or DUPLEX_UNFORCED for normal duplex detection.
 349          */
 350         int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
 351
 352 #define PAUSE_ON                1
 353 #define PAUSE_OFF               0
 354
 355         /* Enable/disable sending Pause */
 356         int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
 357                               int pause);
 358
 359 #define SPEED_MAX               INT_MAX
 360 #define SPEED_UNFORCED          -2
 361
 362         /* Port's MAC speed (in Mbps)
 363          *
 364          * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
 365          * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
 366          */
 367         int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
 368
 369         /* What interface mode should be used for maximum speed? */
 370         phy_interface_t (*port_max_speed_mode)(int port);
 371
 372         int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
 373
 374         int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
 375                                    enum mv88e6xxx_frame_mode mode);
 376         int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
 377                                       bool unicast, bool multicast);
 378         int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
 379                                    u16 etype);
 380         int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
 381                                    size_t size);
 382
 383         int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
 384         int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
 385                                 u8 out);
 386         int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
 387         int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
 388
 389         /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
 390          * Some chips allow this to be configured on specific ports.
 391          */
 392         int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
 393                               phy_interface_t mode);
 394         int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 395
 396         /* Some devices have a per port register indicating what is
 397          * the upstream port this port should forward to.
 398          */
 399         int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
 400                                       int upstream_port);
 401         /* Return the port link state, as required by phylink */
 402         int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
 403                                struct phylink_link_state *state);
 404
 405         /* Snapshot the statistics for a port. The statistics can then
 406          * be read back a leisure but still with a consistent view.
 407          */
 408         int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
 409
 410         /* Set the histogram mode for statistics, when the control registers
 411          * are separated out of the STATS_OP register.
 412          */
 413         int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
 414
 415         /* Return the number of strings describing statistics */
 416         int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
 417         int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
 418         int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 419                                uint64_t *data);
 420         int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
 421         int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
 422
 423 #define MV88E6XXX_CASCADE_PORT_NONE             0xe
 424 #define MV88E6XXX_CASCADE_PORT_MULTIPLE         0xf
 425
 426         int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
 427
 428         const struct mv88e6xxx_irq_ops *watchdog_ops;
 429
 430         int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
 431
 432         /* Power on/off a SERDES interface */
 433         int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
 434
 435         /* SERDES interrupt handling */
 436         int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
 437         void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);
 438
 439         /* Statistics from the SERDES interface */
 440         int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
 441         int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
 442                                   uint8_t *data);
 443         int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 444                                 uint64_t *data);
 445
 446         /* VLAN Translation Unit operations */
 447         int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
 448                            struct mv88e6xxx_vtu_entry *entry);
 449         int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
 450                              struct mv88e6xxx_vtu_entry *entry);
 451
 452         /* GPIO operations */
 453         const struct mv88e6xxx_gpio_ops *gpio_ops;
 454
 455         /* Interface to the AVB/PTP registers */
 456         const struct mv88e6xxx_avb_ops *avb_ops;
 457
 458         /* Remote Management Unit operations */
 459         int (*rmu_disable)(struct mv88e6xxx_chip *chip);
 460
 461         /* Precision Time Protocol operations */
 462         const struct mv88e6xxx_ptp_ops *ptp_ops;
 463
 464         /* Phylink */
 465         void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
 466                                  unsigned long *mask,
 467                                  struct phylink_link_state *state);
 468 };
 469
 470 struct mv88e6xxx_irq_ops {
 471         /* Action to be performed when the interrupt happens */
 472         int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
 473         /* Setup the hardware to generate the interrupt */
 474         int (*irq_setup)(struct mv88e6xxx_chip *chip);
 475         /* Reset the hardware to stop generating the interrupt */
 476         void (*irq_free)(struct mv88e6xxx_chip *chip);
 477 };
 478
 479 struct mv88e6xxx_gpio_ops {
 480         /* Get/set data on GPIO pin */
 481         int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
 482         int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
 483                         int value);
 484
 485         /* get/set GPIO direction */
 486         int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
 487         int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
 488                        bool input);
 489
 490         /* get/set GPIO pin control */
 491         int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 492                         int *func);
 493         int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 494                         int func);
 495 };
 496
 497 struct mv88e6xxx_avb_ops {
 498         /* Access port-scoped Precision Time Protocol registers */
 499         int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
 500                              u16 *data, int len);
 501         int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
 502                               u16 data);
 503
 504         /* Access global Precision Time Protocol registers */
 505         int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 506                         int len);
 507         int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 508
 509         /* Access global Time Application Interface registers */
 510         int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 511                         int len);
 512         int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 513 };
 514
 515 struct mv88e6xxx_ptp_ops {
 516         u64 (*clock_read)(const struct cyclecounter *cc);
 517         int (*ptp_enable)(struct ptp_clock_info *ptp,
 518                           struct ptp_clock_request *rq, int on);
 519         int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
 520                           enum ptp_pin_function func, unsigned int chan);
 521         void (*event_work)(struct work_struct *ugly);
 522         int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
 523         int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
 524         int (*global_enable)(struct mv88e6xxx_chip *chip);
 525         int (*global_disable)(struct mv88e6xxx_chip *chip);
 526         int n_ext_ts;
 527         int arr0_sts_reg;
 528         int arr1_sts_reg;
 529         int dep_sts_reg;
 530         u32 rx_filters;
 531 };
 532
 533 #define STATS_TYPE_PORT         BIT(0)
 534 #define STATS_TYPE_BANK0        BIT(1)
 535 #define STATS_TYPE_BANK1        BIT(2)
 536
 537 struct mv88e6xxx_hw_stat {
 538         char string[ETH_GSTRING_LEN];
 539         size_t size;
 540         int reg;
 541         int type;
 542 };
 543
 544 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
 545 {
 546         return chip->info->pvt;
 547 }
 548
 549 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 550 {
 551         return chip->info->num_databases;
 552 }
 553
 554 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
 555 {
 556         return chip->info->num_ports;
 557 }
 558
 559 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
 560 {
 561         return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
 562 }
 563
 564 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
 565 {
 566         return chip->info->num_gpio;
 567 }
 568
 569 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 570 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 571 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 572                      u16 update);
 573 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
 574 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 575                              int speed, int duplex, int pause,
 576                              phy_interface_t mode);
 577 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
 578
 579 #endif /* _MV88E6XXX_CHIP_H */