2 * Copyright (c) 2016, NVIDIA CORPORATION.
4 * SPDX-License-Identifier: GPL-2.0
6 * Portions based on U-Boot's rtl8169.c.
10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
11 * Service) IP block. The IP supports multiple options for bus type, clocking/
12 * reset structure, and feature list.
14 * The driver is written such that generic core logic is kept separate from
15 * configuration-specific logic. Code that interacts with configuration-
16 * specific resources is split out into separate functions to avoid polluting
17 * common code. If/when this driver is enhanced to support multiple
18 * configurations, the core code should be adapted to call all configuration-
19 * specific functions through function pointers, with the definition of those
20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
23 * The following configurations are currently supported:
25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
27 * supports a single RGMII PHY. This configuration also has SW control over
28 * all clock and reset signals to the HW block.
47 #define EQOS_MAC_REGS_BASE 0x000
48 struct eqos_mac_regs
{
49 uint32_t configuration
; /* 0x000 */
50 uint32_t unused_004
[(0x070 - 0x004) / 4]; /* 0x004 */
51 uint32_t q0_tx_flow_ctrl
; /* 0x070 */
52 uint32_t unused_070
[(0x090 - 0x074) / 4]; /* 0x074 */
53 uint32_t rx_flow_ctrl
; /* 0x090 */
54 uint32_t unused_094
; /* 0x094 */
55 uint32_t txq_prty_map0
; /* 0x098 */
56 uint32_t unused_09c
; /* 0x09c */
57 uint32_t rxq_ctrl0
; /* 0x0a0 */
58 uint32_t unused_0a4
; /* 0x0a4 */
59 uint32_t rxq_ctrl2
; /* 0x0a8 */
60 uint32_t unused_0ac
[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
61 uint32_t us_tic_counter
; /* 0x0dc */
62 uint32_t unused_0e0
[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
63 uint32_t hw_feature0
; /* 0x11c */
64 uint32_t hw_feature1
; /* 0x120 */
65 uint32_t hw_feature2
; /* 0x124 */
66 uint32_t unused_128
[(0x200 - 0x128) / 4]; /* 0x128 */
67 uint32_t mdio_address
; /* 0x200 */
68 uint32_t mdio_data
; /* 0x204 */
69 uint32_t unused_208
[(0x300 - 0x208) / 4]; /* 0x208 */
70 uint32_t address0_high
; /* 0x300 */
71 uint32_t address0_low
; /* 0x304 */
74 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
75 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
76 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
77 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
78 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
79 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
80 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
81 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
82 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
83 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
84 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
86 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
87 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
88 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
90 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
92 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
93 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
95 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
96 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
100 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
101 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
103 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
104 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
105 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
106 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
108 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
109 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
110 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
111 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
112 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
113 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
114 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
115 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
116 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
117 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
119 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
121 #define EQOS_MTL_REGS_BASE 0xd00
122 struct eqos_mtl_regs
{
123 uint32_t txq0_operation_mode
; /* 0xd00 */
124 uint32_t unused_d04
; /* 0xd04 */
125 uint32_t txq0_debug
; /* 0xd08 */
126 uint32_t unused_d0c
[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
127 uint32_t txq0_quantum_weight
; /* 0xd18 */
128 uint32_t unused_d1c
[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
129 uint32_t rxq0_operation_mode
; /* 0xd30 */
130 uint32_t unused_d34
; /* 0xd34 */
131 uint32_t rxq0_debug
; /* 0xd38 */
134 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
135 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
136 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
137 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
138 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
139 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
140 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
142 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
143 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
144 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
146 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
147 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
148 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
149 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
150 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
151 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
152 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
153 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
155 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
156 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
157 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
158 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
160 #define EQOS_DMA_REGS_BASE 0x1000
161 struct eqos_dma_regs
{
162 uint32_t mode
; /* 0x1000 */
163 uint32_t sysbus_mode
; /* 0x1004 */
164 uint32_t unused_1008
[(0x1100 - 0x1008) / 4]; /* 0x1008 */
165 uint32_t ch0_control
; /* 0x1100 */
166 uint32_t ch0_tx_control
; /* 0x1104 */
167 uint32_t ch0_rx_control
; /* 0x1108 */
168 uint32_t unused_110c
; /* 0x110c */
169 uint32_t ch0_txdesc_list_haddress
; /* 0x1110 */
170 uint32_t ch0_txdesc_list_address
; /* 0x1114 */
171 uint32_t ch0_rxdesc_list_haddress
; /* 0x1118 */
172 uint32_t ch0_rxdesc_list_address
; /* 0x111c */
173 uint32_t ch0_txdesc_tail_pointer
; /* 0x1120 */
174 uint32_t unused_1124
; /* 0x1124 */
175 uint32_t ch0_rxdesc_tail_pointer
; /* 0x1128 */
176 uint32_t ch0_txdesc_ring_length
; /* 0x112c */
177 uint32_t ch0_rxdesc_ring_length
; /* 0x1130 */
180 #define EQOS_DMA_MODE_SWR BIT(0)
182 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
183 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
184 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
185 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
186 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
187 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
189 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
191 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
192 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
193 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
194 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
196 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
197 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
198 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
199 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
200 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
202 /* These registers are Tegra186-specific */
203 #define EQOS_TEGRA186_REGS_BASE 0x8800
204 struct eqos_tegra186_regs
{
205 uint32_t sdmemcomppadctrl
; /* 0x8800 */
206 uint32_t auto_cal_config
; /* 0x8804 */
207 uint32_t unused_8808
; /* 0x8808 */
208 uint32_t auto_cal_status
; /* 0x880c */
211 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
213 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
214 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
216 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
220 #define EQOS_DESCRIPTOR_WORDS 4
221 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
222 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
223 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
224 #define EQOS_DESCRIPTORS_TX 4
225 #define EQOS_DESCRIPTORS_RX 4
226 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
227 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
228 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
229 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
230 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
231 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
234 * Warn if the cache-line size is larger than the descriptor size. In such
235 * cases the driver will likely fail because the CPU needs to flush the cache
236 * when requeuing RX buffers, therefore descriptors written by the hardware
237 * may be discarded. Architectures with full IO coherence, such as x86, do not
238 * experience this issue, and hence are excluded from this condition.
240 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
241 * the driver to allocate descriptors from a pool of non-cached memory.
243 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
244 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
245 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
246 #warning Cache line size is larger than descriptor size
257 #define EQOS_DESC3_OWN BIT(31)
258 #define EQOS_DESC3_FD BIT(29)
259 #define EQOS_DESC3_LD BIT(28)
260 #define EQOS_DESC3_BUF1V BIT(24)
263 bool reg_access_always_ok
;
268 const struct eqos_config
*config
;
270 struct eqos_mac_regs
*mac_regs
;
271 struct eqos_mtl_regs
*mtl_regs
;
272 struct eqos_dma_regs
*dma_regs
;
273 struct eqos_tegra186_regs
*tegra186_regs
;
274 struct reset_ctl reset_ctl
;
275 struct gpio_desc phy_reset_gpio
;
276 struct clk clk_master_bus
;
278 struct clk clk_ptp_ref
;
280 struct clk clk_slave_bus
;
282 struct phy_device
*phy
;
284 struct eqos_desc
*tx_descs
;
285 struct eqos_desc
*rx_descs
;
286 int tx_desc_idx
, rx_desc_idx
;
295 * TX and RX descriptors are 16 bytes. This causes problems with the cache
296 * maintenance on CPUs where the cache-line size exceeds the size of these
297 * descriptors. What will happen is that when the driver receives a packet
298 * it will be immediately requeued for the hardware to reuse. The CPU will
299 * therefore need to flush the cache-line containing the descriptor, which
300 * will cause all other descriptors in the same cache-line to be flushed
301 * along with it. If one of those descriptors had been written to by the
302 * device those changes (and the associated packet) will be lost.
304 * To work around this, we make use of non-cached memory if available. If
305 * descriptors are mapped uncached there's no need to manually flush them
306 * or invalidate them.
308 * Note that this only applies to descriptors. The packet data buffers do
309 * not have the same constraints since they are 1536 bytes large, so they
310 * are unlikely to share cache-lines.
312 static void *eqos_alloc_descs(unsigned int num
)
314 #ifdef CONFIG_SYS_NONCACHED_MEMORY
315 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE
,
316 EQOS_DESCRIPTOR_ALIGN
);
318 return memalign(EQOS_DESCRIPTOR_ALIGN
, EQOS_DESCRIPTORS_SIZE
);
322 static void eqos_free_descs(void *descs
)
324 #ifdef CONFIG_SYS_NONCACHED_MEMORY
325 /* FIXME: noncached_alloc() has no opposite */
331 static void eqos_inval_desc(void *desc
)
333 #ifndef CONFIG_SYS_NONCACHED_MEMORY
334 unsigned long start
= (unsigned long)desc
& ~(ARCH_DMA_MINALIGN
- 1);
335 unsigned long end
= ALIGN(start
+ EQOS_DESCRIPTOR_SIZE
,
338 invalidate_dcache_range(start
, end
);
342 static void eqos_flush_desc(void *desc
)
344 #ifndef CONFIG_SYS_NONCACHED_MEMORY
345 flush_cache((unsigned long)desc
, EQOS_DESCRIPTOR_SIZE
);
349 static void eqos_inval_buffer(void *buf
, size_t size
)
351 unsigned long start
= (unsigned long)buf
& ~(ARCH_DMA_MINALIGN
- 1);
352 unsigned long end
= ALIGN(start
+ size
, ARCH_DMA_MINALIGN
);
354 invalidate_dcache_range(start
, end
);
357 static void eqos_flush_buffer(void *buf
, size_t size
)
359 flush_cache((unsigned long)buf
, size
);
362 static int eqos_mdio_wait_idle(struct eqos_priv
*eqos
)
364 return wait_for_bit_le32(&eqos
->mac_regs
->mdio_address
,
365 EQOS_MAC_MDIO_ADDRESS_GB
, false,
369 static int eqos_mdio_read(struct mii_dev
*bus
, int mdio_addr
, int mdio_devad
,
372 struct eqos_priv
*eqos
= bus
->priv
;
376 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__
, eqos
->dev
, mdio_addr
,
379 ret
= eqos_mdio_wait_idle(eqos
);
381 pr_err("MDIO not idle at entry");
385 val
= readl(&eqos
->mac_regs
->mdio_address
);
386 val
&= EQOS_MAC_MDIO_ADDRESS_SKAP
|
387 EQOS_MAC_MDIO_ADDRESS_C45E
;
388 val
|= (mdio_addr
<< EQOS_MAC_MDIO_ADDRESS_PA_SHIFT
) |
389 (mdio_reg
<< EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT
) |
390 (EQOS_MAC_MDIO_ADDRESS_CR_20_35
<<
391 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT
) |
392 (EQOS_MAC_MDIO_ADDRESS_GOC_READ
<<
393 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT
) |
394 EQOS_MAC_MDIO_ADDRESS_GB
;
395 writel(val
, &eqos
->mac_regs
->mdio_address
);
399 ret
= eqos_mdio_wait_idle(eqos
);
401 pr_err("MDIO read didn't complete");
405 val
= readl(&eqos
->mac_regs
->mdio_data
);
406 val
&= EQOS_MAC_MDIO_DATA_GD_MASK
;
408 debug("%s: val=%x\n", __func__
, val
);
413 static int eqos_mdio_write(struct mii_dev
*bus
, int mdio_addr
, int mdio_devad
,
414 int mdio_reg
, u16 mdio_val
)
416 struct eqos_priv
*eqos
= bus
->priv
;
420 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__
, eqos
->dev
,
421 mdio_addr
, mdio_reg
, mdio_val
);
423 ret
= eqos_mdio_wait_idle(eqos
);
425 pr_err("MDIO not idle at entry");
429 writel(mdio_val
, &eqos
->mac_regs
->mdio_data
);
431 val
= readl(&eqos
->mac_regs
->mdio_address
);
432 val
&= EQOS_MAC_MDIO_ADDRESS_SKAP
|
433 EQOS_MAC_MDIO_ADDRESS_C45E
;
434 val
|= (mdio_addr
<< EQOS_MAC_MDIO_ADDRESS_PA_SHIFT
) |
435 (mdio_reg
<< EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT
) |
436 (EQOS_MAC_MDIO_ADDRESS_CR_20_35
<<
437 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT
) |
438 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE
<<
439 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT
) |
440 EQOS_MAC_MDIO_ADDRESS_GB
;
441 writel(val
, &eqos
->mac_regs
->mdio_address
);
445 ret
= eqos_mdio_wait_idle(eqos
);
447 pr_err("MDIO read didn't complete");
454 static int eqos_start_clks_tegra186(struct udevice
*dev
)
456 struct eqos_priv
*eqos
= dev_get_priv(dev
);
459 debug("%s(dev=%p):\n", __func__
, dev
);
461 ret
= clk_enable(&eqos
->clk_slave_bus
);
463 pr_err("clk_enable(clk_slave_bus) failed: %d", ret
);
467 ret
= clk_enable(&eqos
->clk_master_bus
);
469 pr_err("clk_enable(clk_master_bus) failed: %d", ret
);
470 goto err_disable_clk_slave_bus
;
473 ret
= clk_enable(&eqos
->clk_rx
);
475 pr_err("clk_enable(clk_rx) failed: %d", ret
);
476 goto err_disable_clk_master_bus
;
479 ret
= clk_enable(&eqos
->clk_ptp_ref
);
481 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret
);
482 goto err_disable_clk_rx
;
485 ret
= clk_set_rate(&eqos
->clk_ptp_ref
, 125 * 1000 * 1000);
487 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret
);
488 goto err_disable_clk_ptp_ref
;
491 ret
= clk_enable(&eqos
->clk_tx
);
493 pr_err("clk_enable(clk_tx) failed: %d", ret
);
494 goto err_disable_clk_ptp_ref
;
497 debug("%s: OK\n", __func__
);
500 err_disable_clk_ptp_ref
:
501 clk_disable(&eqos
->clk_ptp_ref
);
503 clk_disable(&eqos
->clk_rx
);
504 err_disable_clk_master_bus
:
505 clk_disable(&eqos
->clk_master_bus
);
506 err_disable_clk_slave_bus
:
507 clk_disable(&eqos
->clk_slave_bus
);
509 debug("%s: FAILED: %d\n", __func__
, ret
);
513 void eqos_stop_clks_tegra186(struct udevice
*dev
)
515 struct eqos_priv
*eqos
= dev_get_priv(dev
);
517 debug("%s(dev=%p):\n", __func__
, dev
);
519 clk_disable(&eqos
->clk_tx
);
520 clk_disable(&eqos
->clk_ptp_ref
);
521 clk_disable(&eqos
->clk_rx
);
522 clk_disable(&eqos
->clk_master_bus
);
523 clk_disable(&eqos
->clk_slave_bus
);
525 debug("%s: OK\n", __func__
);
528 static int eqos_start_resets_tegra186(struct udevice
*dev
)
530 struct eqos_priv
*eqos
= dev_get_priv(dev
);
533 debug("%s(dev=%p):\n", __func__
, dev
);
535 ret
= dm_gpio_set_value(&eqos
->phy_reset_gpio
, 1);
537 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret
);
543 ret
= dm_gpio_set_value(&eqos
->phy_reset_gpio
, 0);
545 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret
);
549 ret
= reset_assert(&eqos
->reset_ctl
);
551 pr_err("reset_assert() failed: %d", ret
);
557 ret
= reset_deassert(&eqos
->reset_ctl
);
559 pr_err("reset_deassert() failed: %d", ret
);
563 debug("%s: OK\n", __func__
);
567 static int eqos_stop_resets_tegra186(struct udevice
*dev
)
569 struct eqos_priv
*eqos
= dev_get_priv(dev
);
571 reset_assert(&eqos
->reset_ctl
);
572 dm_gpio_set_value(&eqos
->phy_reset_gpio
, 1);
577 static int eqos_calibrate_pads_tegra186(struct udevice
*dev
)
579 struct eqos_priv
*eqos
= dev_get_priv(dev
);
582 debug("%s(dev=%p):\n", __func__
, dev
);
584 setbits_le32(&eqos
->tegra186_regs
->sdmemcomppadctrl
,
585 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD
);
589 setbits_le32(&eqos
->tegra186_regs
->auto_cal_config
,
590 EQOS_AUTO_CAL_CONFIG_START
| EQOS_AUTO_CAL_CONFIG_ENABLE
);
592 ret
= wait_for_bit_le32(&eqos
->tegra186_regs
->auto_cal_status
,
593 EQOS_AUTO_CAL_STATUS_ACTIVE
, true, 10, false);
595 pr_err("calibrate didn't start");
599 ret
= wait_for_bit_le32(&eqos
->tegra186_regs
->auto_cal_status
,
600 EQOS_AUTO_CAL_STATUS_ACTIVE
, false, 10, false);
602 pr_err("calibrate didn't finish");
609 clrbits_le32(&eqos
->tegra186_regs
->sdmemcomppadctrl
,
610 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD
);
612 debug("%s: returns %d\n", __func__
, ret
);
617 static int eqos_disable_calibration_tegra186(struct udevice
*dev
)
619 struct eqos_priv
*eqos
= dev_get_priv(dev
);
621 debug("%s(dev=%p):\n", __func__
, dev
);
623 clrbits_le32(&eqos
->tegra186_regs
->auto_cal_config
,
624 EQOS_AUTO_CAL_CONFIG_ENABLE
);
629 static ulong
eqos_get_tick_clk_rate_tegra186(struct udevice
*dev
)
631 struct eqos_priv
*eqos
= dev_get_priv(dev
);
633 return clk_get_rate(&eqos
->clk_slave_bus
);
636 static int eqos_set_full_duplex(struct udevice
*dev
)
638 struct eqos_priv
*eqos
= dev_get_priv(dev
);
640 debug("%s(dev=%p):\n", __func__
, dev
);
642 setbits_le32(&eqos
->mac_regs
->configuration
, EQOS_MAC_CONFIGURATION_DM
);
647 static int eqos_set_half_duplex(struct udevice
*dev
)
649 struct eqos_priv
*eqos
= dev_get_priv(dev
);
651 debug("%s(dev=%p):\n", __func__
, dev
);
653 clrbits_le32(&eqos
->mac_regs
->configuration
, EQOS_MAC_CONFIGURATION_DM
);
655 /* WAR: Flush TX queue when switching to half-duplex */
656 setbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
657 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ
);
662 static int eqos_set_gmii_speed(struct udevice
*dev
)
664 struct eqos_priv
*eqos
= dev_get_priv(dev
);
666 debug("%s(dev=%p):\n", __func__
, dev
);
668 clrbits_le32(&eqos
->mac_regs
->configuration
,
669 EQOS_MAC_CONFIGURATION_PS
| EQOS_MAC_CONFIGURATION_FES
);
674 static int eqos_set_mii_speed_100(struct udevice
*dev
)
676 struct eqos_priv
*eqos
= dev_get_priv(dev
);
678 debug("%s(dev=%p):\n", __func__
, dev
);
680 setbits_le32(&eqos
->mac_regs
->configuration
,
681 EQOS_MAC_CONFIGURATION_PS
| EQOS_MAC_CONFIGURATION_FES
);
686 static int eqos_set_mii_speed_10(struct udevice
*dev
)
688 struct eqos_priv
*eqos
= dev_get_priv(dev
);
690 debug("%s(dev=%p):\n", __func__
, dev
);
692 clrsetbits_le32(&eqos
->mac_regs
->configuration
,
693 EQOS_MAC_CONFIGURATION_FES
, EQOS_MAC_CONFIGURATION_PS
);
698 static int eqos_set_tx_clk_speed_tegra186(struct udevice
*dev
)
700 struct eqos_priv
*eqos
= dev_get_priv(dev
);
704 debug("%s(dev=%p):\n", __func__
, dev
);
706 switch (eqos
->phy
->speed
) {
708 rate
= 125 * 1000 * 1000;
711 rate
= 25 * 1000 * 1000;
714 rate
= 2.5 * 1000 * 1000;
717 pr_err("invalid speed %d", eqos
->phy
->speed
);
721 ret
= clk_set_rate(&eqos
->clk_tx
, rate
);
723 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate
, ret
);
730 static int eqos_adjust_link(struct udevice
*dev
)
732 struct eqos_priv
*eqos
= dev_get_priv(dev
);
736 debug("%s(dev=%p):\n", __func__
, dev
);
738 if (eqos
->phy
->duplex
)
739 ret
= eqos_set_full_duplex(dev
);
741 ret
= eqos_set_half_duplex(dev
);
743 pr_err("eqos_set_*_duplex() failed: %d", ret
);
747 switch (eqos
->phy
->speed
) {
749 en_calibration
= true;
750 ret
= eqos_set_gmii_speed(dev
);
753 en_calibration
= true;
754 ret
= eqos_set_mii_speed_100(dev
);
757 en_calibration
= false;
758 ret
= eqos_set_mii_speed_10(dev
);
761 pr_err("invalid speed %d", eqos
->phy
->speed
);
765 pr_err("eqos_set_*mii_speed*() failed: %d", ret
);
769 if (en_calibration
) {
770 ret
= eqos_calibrate_pads_tegra186(dev
);
772 pr_err("eqos_calibrate_pads_tegra186() failed: %d", ret
);
776 ret
= eqos_disable_calibration_tegra186(dev
);
778 pr_err("eqos_disable_calibration_tegra186() failed: %d",
784 ret
= eqos_set_tx_clk_speed_tegra186(dev
);
786 pr_err("eqos_set_tx_clk_speed_tegra186() failed: %d", ret
);
793 static int eqos_write_hwaddr(struct udevice
*dev
)
795 struct eth_pdata
*plat
= dev_get_platdata(dev
);
796 struct eqos_priv
*eqos
= dev_get_priv(dev
);
800 * This function may be called before start() or after stop(). At that
801 * time, on at least some configurations of the EQoS HW, all clocks to
802 * the EQoS HW block will be stopped, and a reset signal applied. If
803 * any register access is attempted in this state, bus timeouts or CPU
804 * hangs may occur. This check prevents that.
806 * A simple solution to this problem would be to not implement
807 * write_hwaddr(), since start() always writes the MAC address into HW
808 * anyway. However, it is desirable to implement write_hwaddr() to
809 * support the case of SW that runs subsequent to U-Boot which expects
810 * the MAC address to already be programmed into the EQoS registers,
811 * which must happen irrespective of whether the U-Boot user (or
812 * scripts) actually made use of the EQoS device, and hence
813 * irrespective of whether start() was ever called.
815 * Note that this requirement by subsequent SW is not valid for
816 * Tegra186, and is likely not valid for any non-PCI instantiation of
817 * the EQoS HW block. This function is implemented solely as
818 * future-proofing with the expectation the driver will eventually be
819 * ported to some system where the expectation above is true.
821 if (!eqos
->config
->reg_access_always_ok
&& !eqos
->reg_access_ok
)
824 /* Update the MAC address */
825 val
= (plat
->enetaddr
[5] << 8) |
827 writel(val
, &eqos
->mac_regs
->address0_high
);
828 val
= (plat
->enetaddr
[3] << 24) |
829 (plat
->enetaddr
[2] << 16) |
830 (plat
->enetaddr
[1] << 8) |
832 writel(val
, &eqos
->mac_regs
->address0_low
);
837 static int eqos_start(struct udevice
*dev
)
839 struct eqos_priv
*eqos
= dev_get_priv(dev
);
842 u32 val
, tx_fifo_sz
, rx_fifo_sz
, tqs
, rqs
, pbl
;
845 debug("%s(dev=%p):\n", __func__
, dev
);
847 eqos
->tx_desc_idx
= 0;
848 eqos
->rx_desc_idx
= 0;
850 ret
= eqos_start_clks_tegra186(dev
);
852 pr_err("eqos_start_clks_tegra186() failed: %d", ret
);
856 ret
= eqos_start_resets_tegra186(dev
);
858 pr_err("eqos_start_resets_tegra186() failed: %d", ret
);
864 eqos
->reg_access_ok
= true;
866 ret
= wait_for_bit_le32(&eqos
->dma_regs
->mode
,
867 EQOS_DMA_MODE_SWR
, false, 10, false);
869 pr_err("EQOS_DMA_MODE_SWR stuck");
870 goto err_stop_resets
;
873 ret
= eqos_calibrate_pads_tegra186(dev
);
875 pr_err("eqos_calibrate_pads_tegra186() failed: %d", ret
);
876 goto err_stop_resets
;
879 rate
= eqos_get_tick_clk_rate_tegra186(dev
);
880 val
= (rate
/ 1000000) - 1;
881 writel(val
, &eqos
->mac_regs
->us_tic_counter
);
883 eqos
->phy
= phy_connect(eqos
->mii
, 0, dev
, 0);
885 pr_err("phy_connect() failed");
886 goto err_stop_resets
;
888 ret
= phy_config(eqos
->phy
);
890 pr_err("phy_config() failed: %d", ret
);
891 goto err_shutdown_phy
;
893 ret
= phy_startup(eqos
->phy
);
895 pr_err("phy_startup() failed: %d", ret
);
896 goto err_shutdown_phy
;
899 if (!eqos
->phy
->link
) {
901 goto err_shutdown_phy
;
904 ret
= eqos_adjust_link(dev
);
906 pr_err("eqos_adjust_link() failed: %d", ret
);
907 goto err_shutdown_phy
;
912 /* Enable Store and Forward mode for TX */
913 /* Program Tx operating mode */
914 setbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
915 EQOS_MTL_TXQ0_OPERATION_MODE_TSF
|
916 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED
<<
917 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT
));
919 /* Transmit Queue weight */
920 writel(0x10, &eqos
->mtl_regs
->txq0_quantum_weight
);
922 /* Enable Store and Forward mode for RX, since no jumbo frame */
923 setbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
924 EQOS_MTL_RXQ0_OPERATION_MODE_RSF
);
926 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
927 val
= readl(&eqos
->mac_regs
->hw_feature1
);
928 tx_fifo_sz
= (val
>> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT
) &
929 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK
;
930 rx_fifo_sz
= (val
>> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT
) &
931 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK
;
934 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
935 * r/tqs is encoded as (n / 256) - 1.
937 tqs
= (128 << tx_fifo_sz
) / 256 - 1;
938 rqs
= (128 << rx_fifo_sz
) / 256 - 1;
940 clrsetbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
941 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK
<<
942 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT
,
943 tqs
<< EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT
);
944 clrsetbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
945 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK
<<
946 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT
,
947 rqs
<< EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT
);
949 /* Flow control used only if each channel gets 4KB or more FIFO */
950 if (rqs
>= ((4096 / 256) - 1)) {
953 setbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
954 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC
);
957 * Set Threshold for Activating Flow Contol space for min 2
958 * frames ie, (1500 * 1) = 1500 bytes.
960 * Set Threshold for Deactivating Flow Contol for space of
961 * min 1 frame (frame size 1500bytes) in receive fifo
963 if (rqs
== ((4096 / 256) - 1)) {
965 * This violates the above formula because of FIFO size
966 * limit therefore overflow may occur inspite of this.
968 rfd
= 0x3; /* Full-3K */
969 rfa
= 0x1; /* Full-1.5K */
970 } else if (rqs
== ((8192 / 256) - 1)) {
971 rfd
= 0x6; /* Full-4K */
972 rfa
= 0xa; /* Full-6K */
973 } else if (rqs
== ((16384 / 256) - 1)) {
974 rfd
= 0x6; /* Full-4K */
975 rfa
= 0x12; /* Full-10K */
977 rfd
= 0x6; /* Full-4K */
978 rfa
= 0x1E; /* Full-16K */
981 clrsetbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
982 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK
<<
983 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT
) |
984 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK
<<
985 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT
),
987 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT
) |
989 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT
));
994 clrsetbits_le32(&eqos
->mac_regs
->rxq_ctrl0
,
995 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK
<<
996 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT
,
997 EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB
<<
998 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT
);
1000 /* Set TX flow control parameters */
1001 /* Set Pause Time */
1002 setbits_le32(&eqos
->mac_regs
->q0_tx_flow_ctrl
,
1003 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT
);
1004 /* Assign priority for TX flow control */
1005 clrbits_le32(&eqos
->mac_regs
->txq_prty_map0
,
1006 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK
<<
1007 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT
);
1008 /* Assign priority for RX flow control */
1009 clrbits_le32(&eqos
->mac_regs
->rxq_ctrl2
,
1010 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK
<<
1011 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT
);
1012 /* Enable flow control */
1013 setbits_le32(&eqos
->mac_regs
->q0_tx_flow_ctrl
,
1014 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE
);
1015 setbits_le32(&eqos
->mac_regs
->rx_flow_ctrl
,
1016 EQOS_MAC_RX_FLOW_CTRL_RFE
);
1018 clrsetbits_le32(&eqos
->mac_regs
->configuration
,
1019 EQOS_MAC_CONFIGURATION_GPSLCE
|
1020 EQOS_MAC_CONFIGURATION_WD
|
1021 EQOS_MAC_CONFIGURATION_JD
|
1022 EQOS_MAC_CONFIGURATION_JE
,
1023 EQOS_MAC_CONFIGURATION_CST
|
1024 EQOS_MAC_CONFIGURATION_ACS
);
1026 eqos_write_hwaddr(dev
);
1030 /* Enable OSP mode */
1031 setbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1032 EQOS_DMA_CH0_TX_CONTROL_OSP
);
1034 /* RX buffer size. Must be a multiple of bus width */
1035 clrsetbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1036 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK
<<
1037 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT
,
1038 EQOS_MAX_PACKET_SIZE
<<
1039 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT
);
1041 setbits_le32(&eqos
->dma_regs
->ch0_control
,
1042 EQOS_DMA_CH0_CONTROL_PBLX8
);
1045 * Burst length must be < 1/2 FIFO size.
1046 * FIFO size in tqs is encoded as (n / 256) - 1.
1047 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1048 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1053 clrsetbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1054 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK
<<
1055 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT
,
1056 pbl
<< EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT
);
1058 clrsetbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1059 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK
<<
1060 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT
,
1061 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT
);
1063 /* DMA performance configuration */
1064 val
= (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT
) |
1065 EQOS_DMA_SYSBUS_MODE_EAME
| EQOS_DMA_SYSBUS_MODE_BLEN16
|
1066 EQOS_DMA_SYSBUS_MODE_BLEN8
| EQOS_DMA_SYSBUS_MODE_BLEN4
;
1067 writel(val
, &eqos
->dma_regs
->sysbus_mode
);
1069 /* Set up descriptors */
1071 memset(eqos
->descs
, 0, EQOS_DESCRIPTORS_SIZE
);
1072 for (i
= 0; i
< EQOS_DESCRIPTORS_RX
; i
++) {
1073 struct eqos_desc
*rx_desc
= &(eqos
->rx_descs
[i
]);
1074 rx_desc
->des0
= (u32
)(ulong
)(eqos
->rx_dma_buf
+
1075 (i
* EQOS_MAX_PACKET_SIZE
));
1076 rx_desc
->des3
|= EQOS_DESC3_OWN
| EQOS_DESC3_BUF1V
;
1078 flush_cache((unsigned long)eqos
->descs
, EQOS_DESCRIPTORS_SIZE
);
1080 writel(0, &eqos
->dma_regs
->ch0_txdesc_list_haddress
);
1081 writel((ulong
)eqos
->tx_descs
, &eqos
->dma_regs
->ch0_txdesc_list_address
);
1082 writel(EQOS_DESCRIPTORS_TX
- 1,
1083 &eqos
->dma_regs
->ch0_txdesc_ring_length
);
1085 writel(0, &eqos
->dma_regs
->ch0_rxdesc_list_haddress
);
1086 writel((ulong
)eqos
->rx_descs
, &eqos
->dma_regs
->ch0_rxdesc_list_address
);
1087 writel(EQOS_DESCRIPTORS_RX
- 1,
1088 &eqos
->dma_regs
->ch0_rxdesc_ring_length
);
1090 /* Enable everything */
1092 setbits_le32(&eqos
->mac_regs
->configuration
,
1093 EQOS_MAC_CONFIGURATION_TE
| EQOS_MAC_CONFIGURATION_RE
);
1095 setbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1096 EQOS_DMA_CH0_TX_CONTROL_ST
);
1097 setbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1098 EQOS_DMA_CH0_RX_CONTROL_SR
);
1100 /* TX tail pointer not written until we need to TX a packet */
1102 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1103 * first descriptor, implying all descriptors were available. However,
1104 * that's not distinguishable from none of the descriptors being
1107 last_rx_desc
= (ulong
)&(eqos
->rx_descs
[(EQOS_DESCRIPTORS_RX
- 1)]);
1108 writel(last_rx_desc
, &eqos
->dma_regs
->ch0_rxdesc_tail_pointer
);
1110 eqos
->started
= true;
1112 debug("%s: OK\n", __func__
);
1116 phy_shutdown(eqos
->phy
);
1119 eqos_stop_resets_tegra186(dev
);
1121 eqos_stop_clks_tegra186(dev
);
1123 pr_err("FAILED: %d", ret
);
1127 void eqos_stop(struct udevice
*dev
)
1129 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1132 debug("%s(dev=%p):\n", __func__
, dev
);
1136 eqos
->started
= false;
1137 eqos
->reg_access_ok
= false;
1139 /* Disable TX DMA */
1140 clrbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1141 EQOS_DMA_CH0_TX_CONTROL_ST
);
1143 /* Wait for TX all packets to drain out of MTL */
1144 for (i
= 0; i
< 1000000; i
++) {
1145 u32 val
= readl(&eqos
->mtl_regs
->txq0_debug
);
1146 u32 trcsts
= (val
>> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT
) &
1147 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK
;
1148 u32 txqsts
= val
& EQOS_MTL_TXQ0_DEBUG_TXQSTS
;
1149 if ((trcsts
!= 1) && (!txqsts
))
1153 /* Turn off MAC TX and RX */
1154 clrbits_le32(&eqos
->mac_regs
->configuration
,
1155 EQOS_MAC_CONFIGURATION_TE
| EQOS_MAC_CONFIGURATION_RE
);
1157 /* Wait for all RX packets to drain out of MTL */
1158 for (i
= 0; i
< 1000000; i
++) {
1159 u32 val
= readl(&eqos
->mtl_regs
->rxq0_debug
);
1160 u32 prxq
= (val
>> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT
) &
1161 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK
;
1162 u32 rxqsts
= (val
>> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT
) &
1163 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK
;
1164 if ((!prxq
) && (!rxqsts
))
1168 /* Turn off RX DMA */
1169 clrbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1170 EQOS_DMA_CH0_RX_CONTROL_SR
);
1173 phy_shutdown(eqos
->phy
);
1176 eqos_stop_resets_tegra186(dev
);
1177 eqos_stop_clks_tegra186(dev
);
1179 debug("%s: OK\n", __func__
);
1182 int eqos_send(struct udevice
*dev
, void *packet
, int length
)
1184 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1185 struct eqos_desc
*tx_desc
;
1188 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__
, dev
, packet
,
1191 memcpy(eqos
->tx_dma_buf
, packet
, length
);
1192 eqos_flush_buffer(eqos
->tx_dma_buf
, length
);
1194 tx_desc
= &(eqos
->tx_descs
[eqos
->tx_desc_idx
]);
1195 eqos
->tx_desc_idx
++;
1196 eqos
->tx_desc_idx
%= EQOS_DESCRIPTORS_TX
;
1198 tx_desc
->des0
= (ulong
)eqos
->tx_dma_buf
;
1200 tx_desc
->des2
= length
;
1202 * Make sure that if HW sees the _OWN write below, it will see all the
1203 * writes to the rest of the descriptor too.
1206 tx_desc
->des3
= EQOS_DESC3_OWN
| EQOS_DESC3_FD
| EQOS_DESC3_LD
| length
;
1207 eqos_flush_desc(tx_desc
);
1209 writel((ulong
)(tx_desc
+ 1), &eqos
->dma_regs
->ch0_txdesc_tail_pointer
);
1211 for (i
= 0; i
< 1000000; i
++) {
1212 eqos_inval_desc(tx_desc
);
1213 if (!(readl(&tx_desc
->des3
) & EQOS_DESC3_OWN
))
1218 debug("%s: TX timeout\n", __func__
);
1223 int eqos_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
1225 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1226 struct eqos_desc
*rx_desc
;
1229 debug("%s(dev=%p, flags=%x):\n", __func__
, dev
, flags
);
1231 rx_desc
= &(eqos
->rx_descs
[eqos
->rx_desc_idx
]);
1232 if (rx_desc
->des3
& EQOS_DESC3_OWN
) {
1233 debug("%s: RX packet not available\n", __func__
);
1237 *packetp
= eqos
->rx_dma_buf
+
1238 (eqos
->rx_desc_idx
* EQOS_MAX_PACKET_SIZE
);
1239 length
= rx_desc
->des3
& 0x7fff;
1240 debug("%s: *packetp=%p, length=%d\n", __func__
, *packetp
, length
);
1242 eqos_inval_buffer(*packetp
, length
);
1247 int eqos_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
1249 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1250 uchar
*packet_expected
;
1251 struct eqos_desc
*rx_desc
;
1253 debug("%s(packet=%p, length=%d)\n", __func__
, packet
, length
);
1255 packet_expected
= eqos
->rx_dma_buf
+
1256 (eqos
->rx_desc_idx
* EQOS_MAX_PACKET_SIZE
);
1257 if (packet
!= packet_expected
) {
1258 debug("%s: Unexpected packet (expected %p)\n", __func__
,
1263 rx_desc
= &(eqos
->rx_descs
[eqos
->rx_desc_idx
]);
1264 rx_desc
->des0
= (u32
)(ulong
)packet
;
1268 * Make sure that if HW sees the _OWN write below, it will see all the
1269 * writes to the rest of the descriptor too.
1272 rx_desc
->des3
|= EQOS_DESC3_OWN
| EQOS_DESC3_BUF1V
;
1273 eqos_flush_desc(rx_desc
);
1275 writel((ulong
)rx_desc
, &eqos
->dma_regs
->ch0_rxdesc_tail_pointer
);
1277 eqos
->rx_desc_idx
++;
1278 eqos
->rx_desc_idx
%= EQOS_DESCRIPTORS_RX
;
1283 static int eqos_probe_resources_core(struct udevice
*dev
)
1285 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1288 debug("%s(dev=%p):\n", __func__
, dev
);
1290 eqos
->descs
= eqos_alloc_descs(EQOS_DESCRIPTORS_TX
+
1291 EQOS_DESCRIPTORS_RX
);
1293 debug("%s: eqos_alloc_descs() failed\n", __func__
);
1297 eqos
->tx_descs
= (struct eqos_desc
*)eqos
->descs
;
1298 eqos
->rx_descs
= (eqos
->tx_descs
+ EQOS_DESCRIPTORS_TX
);
1299 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__
, eqos
->tx_descs
,
1302 eqos
->tx_dma_buf
= memalign(EQOS_BUFFER_ALIGN
, EQOS_MAX_PACKET_SIZE
);
1303 if (!eqos
->tx_dma_buf
) {
1304 debug("%s: memalign(tx_dma_buf) failed\n", __func__
);
1306 goto err_free_descs
;
1308 debug("%s: rx_dma_buf=%p\n", __func__
, eqos
->rx_dma_buf
);
1310 eqos
->rx_dma_buf
= memalign(EQOS_BUFFER_ALIGN
, EQOS_RX_BUFFER_SIZE
);
1311 if (!eqos
->rx_dma_buf
) {
1312 debug("%s: memalign(rx_dma_buf) failed\n", __func__
);
1314 goto err_free_tx_dma_buf
;
1316 debug("%s: tx_dma_buf=%p\n", __func__
, eqos
->tx_dma_buf
);
1318 eqos
->rx_pkt
= malloc(EQOS_MAX_PACKET_SIZE
);
1319 if (!eqos
->rx_pkt
) {
1320 debug("%s: malloc(rx_pkt) failed\n", __func__
);
1322 goto err_free_rx_dma_buf
;
1324 debug("%s: rx_pkt=%p\n", __func__
, eqos
->rx_pkt
);
1326 debug("%s: OK\n", __func__
);
1329 err_free_rx_dma_buf
:
1330 free(eqos
->rx_dma_buf
);
1331 err_free_tx_dma_buf
:
1332 free(eqos
->tx_dma_buf
);
1334 eqos_free_descs(eqos
->descs
);
1337 debug("%s: returns %d\n", __func__
, ret
);
1341 static int eqos_remove_resources_core(struct udevice
*dev
)
1343 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1345 debug("%s(dev=%p):\n", __func__
, dev
);
1348 free(eqos
->rx_dma_buf
);
1349 free(eqos
->tx_dma_buf
);
1350 eqos_free_descs(eqos
->descs
);
1352 debug("%s: OK\n", __func__
);
1356 static int eqos_probe_resources_tegra186(struct udevice
*dev
)
1358 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1361 debug("%s(dev=%p):\n", __func__
, dev
);
1363 ret
= reset_get_by_name(dev
, "eqos", &eqos
->reset_ctl
);
1365 pr_err("reset_get_by_name(rst) failed: %d", ret
);
1369 ret
= gpio_request_by_name(dev
, "phy-reset-gpios", 0,
1370 &eqos
->phy_reset_gpio
,
1371 GPIOD_IS_OUT
| GPIOD_IS_OUT_ACTIVE
);
1373 pr_err("gpio_request_by_name(phy reset) failed: %d", ret
);
1374 goto err_free_reset_eqos
;
1377 ret
= clk_get_by_name(dev
, "slave_bus", &eqos
->clk_slave_bus
);
1379 pr_err("clk_get_by_name(slave_bus) failed: %d", ret
);
1380 goto err_free_gpio_phy_reset
;
1383 ret
= clk_get_by_name(dev
, "master_bus", &eqos
->clk_master_bus
);
1385 pr_err("clk_get_by_name(master_bus) failed: %d", ret
);
1386 goto err_free_clk_slave_bus
;
1389 ret
= clk_get_by_name(dev
, "rx", &eqos
->clk_rx
);
1391 pr_err("clk_get_by_name(rx) failed: %d", ret
);
1392 goto err_free_clk_master_bus
;
1395 ret
= clk_get_by_name(dev
, "ptp_ref", &eqos
->clk_ptp_ref
);
1397 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret
);
1398 goto err_free_clk_rx
;
1402 ret
= clk_get_by_name(dev
, "tx", &eqos
->clk_tx
);
1404 pr_err("clk_get_by_name(tx) failed: %d", ret
);
1405 goto err_free_clk_ptp_ref
;
1408 debug("%s: OK\n", __func__
);
1411 err_free_clk_ptp_ref
:
1412 clk_free(&eqos
->clk_ptp_ref
);
1414 clk_free(&eqos
->clk_rx
);
1415 err_free_clk_master_bus
:
1416 clk_free(&eqos
->clk_master_bus
);
1417 err_free_clk_slave_bus
:
1418 clk_free(&eqos
->clk_slave_bus
);
1419 err_free_gpio_phy_reset
:
1420 dm_gpio_free(dev
, &eqos
->phy_reset_gpio
);
1421 err_free_reset_eqos
:
1422 reset_free(&eqos
->reset_ctl
);
1424 debug("%s: returns %d\n", __func__
, ret
);
1428 static int eqos_remove_resources_tegra186(struct udevice
*dev
)
1430 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1432 debug("%s(dev=%p):\n", __func__
, dev
);
1434 clk_free(&eqos
->clk_tx
);
1435 clk_free(&eqos
->clk_ptp_ref
);
1436 clk_free(&eqos
->clk_rx
);
1437 clk_free(&eqos
->clk_slave_bus
);
1438 clk_free(&eqos
->clk_master_bus
);
1439 dm_gpio_free(dev
, &eqos
->phy_reset_gpio
);
1440 reset_free(&eqos
->reset_ctl
);
1442 debug("%s: OK\n", __func__
);
1446 static int eqos_probe(struct udevice
*dev
)
1448 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1451 debug("%s(dev=%p):\n", __func__
, dev
);
1454 eqos
->config
= (void *)dev_get_driver_data(dev
);
1456 eqos
->regs
= devfdt_get_addr(dev
);
1457 if (eqos
->regs
== FDT_ADDR_T_NONE
) {
1458 pr_err("devfdt_get_addr() failed");
1461 eqos
->mac_regs
= (void *)(eqos
->regs
+ EQOS_MAC_REGS_BASE
);
1462 eqos
->mtl_regs
= (void *)(eqos
->regs
+ EQOS_MTL_REGS_BASE
);
1463 eqos
->dma_regs
= (void *)(eqos
->regs
+ EQOS_DMA_REGS_BASE
);
1464 eqos
->tegra186_regs
= (void *)(eqos
->regs
+ EQOS_TEGRA186_REGS_BASE
);
1466 ret
= eqos_probe_resources_core(dev
);
1468 pr_err("eqos_probe_resources_core() failed: %d", ret
);
1472 ret
= eqos_probe_resources_tegra186(dev
);
1474 pr_err("eqos_probe_resources_tegra186() failed: %d", ret
);
1475 goto err_remove_resources_core
;
1478 eqos
->mii
= mdio_alloc();
1480 pr_err("mdio_alloc() failed");
1481 goto err_remove_resources_tegra
;
1483 eqos
->mii
->read
= eqos_mdio_read
;
1484 eqos
->mii
->write
= eqos_mdio_write
;
1485 eqos
->mii
->priv
= eqos
;
1486 strcpy(eqos
->mii
->name
, dev
->name
);
1488 ret
= mdio_register(eqos
->mii
);
1490 pr_err("mdio_register() failed: %d", ret
);
1494 debug("%s: OK\n", __func__
);
1498 mdio_free(eqos
->mii
);
1499 err_remove_resources_tegra
:
1500 eqos_remove_resources_tegra186(dev
);
1501 err_remove_resources_core
:
1502 eqos_remove_resources_core(dev
);
1504 debug("%s: returns %d\n", __func__
, ret
);
1508 static int eqos_remove(struct udevice
*dev
)
1510 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1512 debug("%s(dev=%p):\n", __func__
, dev
);
1514 mdio_unregister(eqos
->mii
);
1515 mdio_free(eqos
->mii
);
1516 eqos_remove_resources_tegra186(dev
);
1517 eqos_probe_resources_core(dev
);
1519 debug("%s: OK\n", __func__
);
1523 static const struct eth_ops eqos_ops
= {
1524 .start
= eqos_start
,
1528 .free_pkt
= eqos_free_pkt
,
1529 .write_hwaddr
= eqos_write_hwaddr
,
1532 static const struct eqos_config eqos_tegra186_config
= {
1533 .reg_access_always_ok
= false,
1536 static const struct udevice_id eqos_ids
[] = {
1538 .compatible
= "nvidia,tegra186-eqos",
1539 .data
= (ulong
)&eqos_tegra186_config
1544 U_BOOT_DRIVER(eth_eqos
) = {
1547 .of_match
= eqos_ids
,
1548 .probe
= eqos_probe
,
1549 .remove
= eqos_remove
,
1551 .priv_auto_alloc_size
= sizeof(struct eqos_priv
),
1552 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),