2 * Copyright (c) 2016, NVIDIA CORPORATION.
4 * SPDX-License-Identifier: GPL-2.0
6 * Portions based on U-Boot's rtl8169.c.
10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
11 * Service) IP block. The IP supports multiple options for bus type, clocking/
12 * reset structure, and feature list.
14 * The driver is written such that generic core logic is kept separate from
15 * configuration-specific logic. Code that interacts with configuration-
16 * specific resources is split out into separate functions to avoid polluting
17 * common code. If/when this driver is enhanced to support multiple
18 * configurations, the core code should be adapted to call all configuration-
19 * specific functions through function pointers, with the definition of those
20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
23 * The following configurations are currently supported:
25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
27 * supports a single RGMII PHY. This configuration also has SW control over
28 * all clock and reset signals to the HW block.
47 #define EQOS_MAC_REGS_BASE 0x000
48 struct eqos_mac_regs
{
49 uint32_t configuration
; /* 0x000 */
50 uint32_t unused_004
[(0x070 - 0x004) / 4]; /* 0x004 */
51 uint32_t q0_tx_flow_ctrl
; /* 0x070 */
52 uint32_t unused_070
[(0x090 - 0x074) / 4]; /* 0x074 */
53 uint32_t rx_flow_ctrl
; /* 0x090 */
54 uint32_t unused_094
; /* 0x094 */
55 uint32_t txq_prty_map0
; /* 0x098 */
56 uint32_t unused_09c
; /* 0x09c */
57 uint32_t rxq_ctrl0
; /* 0x0a0 */
58 uint32_t unused_0a4
; /* 0x0a4 */
59 uint32_t rxq_ctrl2
; /* 0x0a8 */
60 uint32_t unused_0ac
[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
61 uint32_t us_tic_counter
; /* 0x0dc */
62 uint32_t unused_0e0
[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
63 uint32_t hw_feature0
; /* 0x11c */
64 uint32_t hw_feature1
; /* 0x120 */
65 uint32_t hw_feature2
; /* 0x124 */
66 uint32_t unused_128
[(0x200 - 0x128) / 4]; /* 0x128 */
67 uint32_t mdio_address
; /* 0x200 */
68 uint32_t mdio_data
; /* 0x204 */
69 uint32_t unused_208
[(0x300 - 0x208) / 4]; /* 0x208 */
70 uint32_t address0_high
; /* 0x300 */
71 uint32_t address0_low
; /* 0x304 */
74 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
75 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
76 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
77 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
78 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
79 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
80 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
81 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
82 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
83 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
84 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
86 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
87 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
88 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
90 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
92 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
93 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
95 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
96 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
100 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
101 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
103 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
104 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
105 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
106 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
108 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
109 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
110 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
111 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
112 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
113 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
114 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
115 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
116 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
117 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
119 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
121 #define EQOS_MTL_REGS_BASE 0xd00
122 struct eqos_mtl_regs
{
123 uint32_t txq0_operation_mode
; /* 0xd00 */
124 uint32_t unused_d04
; /* 0xd04 */
125 uint32_t txq0_debug
; /* 0xd08 */
126 uint32_t unused_d0c
[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
127 uint32_t txq0_quantum_weight
; /* 0xd18 */
128 uint32_t unused_d1c
[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
129 uint32_t rxq0_operation_mode
; /* 0xd30 */
130 uint32_t unused_d34
; /* 0xd34 */
131 uint32_t rxq0_debug
; /* 0xd38 */
134 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
135 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
136 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
137 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
138 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
139 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
140 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
142 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
143 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
144 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
146 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
147 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
148 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
149 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
150 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
151 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
152 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
153 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
155 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
156 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
157 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
158 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
160 #define EQOS_DMA_REGS_BASE 0x1000
161 struct eqos_dma_regs
{
162 uint32_t mode
; /* 0x1000 */
163 uint32_t sysbus_mode
; /* 0x1004 */
164 uint32_t unused_1008
[(0x1100 - 0x1008) / 4]; /* 0x1008 */
165 uint32_t ch0_control
; /* 0x1100 */
166 uint32_t ch0_tx_control
; /* 0x1104 */
167 uint32_t ch0_rx_control
; /* 0x1108 */
168 uint32_t unused_110c
; /* 0x110c */
169 uint32_t ch0_txdesc_list_haddress
; /* 0x1110 */
170 uint32_t ch0_txdesc_list_address
; /* 0x1114 */
171 uint32_t ch0_rxdesc_list_haddress
; /* 0x1118 */
172 uint32_t ch0_rxdesc_list_address
; /* 0x111c */
173 uint32_t ch0_txdesc_tail_pointer
; /* 0x1120 */
174 uint32_t unused_1124
; /* 0x1124 */
175 uint32_t ch0_rxdesc_tail_pointer
; /* 0x1128 */
176 uint32_t ch0_txdesc_ring_length
; /* 0x112c */
177 uint32_t ch0_rxdesc_ring_length
; /* 0x1130 */
180 #define EQOS_DMA_MODE_SWR BIT(0)
182 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
183 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
184 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
185 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
186 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
187 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
189 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
191 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
192 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
193 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
194 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
196 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
197 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
198 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
199 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
200 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
202 /* These registers are Tegra186-specific */
203 #define EQOS_TEGRA186_REGS_BASE 0x8800
204 struct eqos_tegra186_regs
{
205 uint32_t sdmemcomppadctrl
; /* 0x8800 */
206 uint32_t auto_cal_config
; /* 0x8804 */
207 uint32_t unused_8808
; /* 0x8808 */
208 uint32_t auto_cal_status
; /* 0x880c */
211 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
213 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
214 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
216 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
220 #define EQOS_DESCRIPTOR_WORDS 4
221 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
222 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
223 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
224 #define EQOS_DESCRIPTORS_TX 4
225 #define EQOS_DESCRIPTORS_RX 4
226 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
227 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
228 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
229 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
230 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
231 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
234 * Warn if the cache-line size is larger than the descriptor size. In such
235 * cases the driver will likely fail because the CPU needs to flush the cache
236 * when requeuing RX buffers, therefore descriptors written by the hardware
237 * may be discarded. Architectures with full IO coherence, such as x86, do not
238 * experience this issue, and hence are excluded from this condition.
240 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
241 * the driver to allocate descriptors from a pool of non-cached memory.
243 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
244 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
245 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
246 #warning Cache line size is larger than descriptor size
257 #define EQOS_DESC3_OWN BIT(31)
258 #define EQOS_DESC3_FD BIT(29)
259 #define EQOS_DESC3_LD BIT(28)
260 #define EQOS_DESC3_BUF1V BIT(24)
263 bool reg_access_always_ok
;
268 const struct eqos_config
*config
;
270 struct eqos_mac_regs
*mac_regs
;
271 struct eqos_mtl_regs
*mtl_regs
;
272 struct eqos_dma_regs
*dma_regs
;
273 struct eqos_tegra186_regs
*tegra186_regs
;
274 struct reset_ctl reset_ctl
;
275 struct gpio_desc phy_reset_gpio
;
276 struct clk clk_master_bus
;
278 struct clk clk_ptp_ref
;
280 struct clk clk_slave_bus
;
282 struct phy_device
*phy
;
284 struct eqos_desc
*tx_descs
;
285 struct eqos_desc
*rx_descs
;
286 int tx_desc_idx
, rx_desc_idx
;
295 * TX and RX descriptors are 16 bytes. This causes problems with the cache
296 * maintenance on CPUs where the cache-line size exceeds the size of these
297 * descriptors. What will happen is that when the driver receives a packet
298 * it will be immediately requeued for the hardware to reuse. The CPU will
299 * therefore need to flush the cache-line containing the descriptor, which
300 * will cause all other descriptors in the same cache-line to be flushed
301 * along with it. If one of those descriptors had been written to by the
302 * device those changes (and the associated packet) will be lost.
304 * To work around this, we make use of non-cached memory if available. If
305 * descriptors are mapped uncached there's no need to manually flush them
306 * or invalidate them.
308 * Note that this only applies to descriptors. The packet data buffers do
309 * not have the same constraints since they are 1536 bytes large, so they
310 * are unlikely to share cache-lines.
312 static void *eqos_alloc_descs(unsigned int num
)
314 #ifdef CONFIG_SYS_NONCACHED_MEMORY
315 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE
,
316 EQOS_DESCRIPTOR_ALIGN
);
318 return memalign(EQOS_DESCRIPTOR_ALIGN
, EQOS_DESCRIPTORS_SIZE
);
322 static void eqos_free_descs(void *descs
)
324 #ifdef CONFIG_SYS_NONCACHED_MEMORY
325 /* FIXME: noncached_alloc() has no opposite */
331 static void eqos_inval_desc(void *desc
)
333 #ifndef CONFIG_SYS_NONCACHED_MEMORY
334 unsigned long start
= (unsigned long)desc
& ~(ARCH_DMA_MINALIGN
- 1);
335 unsigned long end
= ALIGN(start
+ EQOS_DESCRIPTOR_SIZE
,
338 invalidate_dcache_range(start
, end
);
342 static void eqos_flush_desc(void *desc
)
344 #ifndef CONFIG_SYS_NONCACHED_MEMORY
345 flush_cache((unsigned long)desc
, EQOS_DESCRIPTOR_SIZE
);
349 static void eqos_inval_buffer(void *buf
, size_t size
)
351 unsigned long start
= (unsigned long)buf
& ~(ARCH_DMA_MINALIGN
- 1);
352 unsigned long end
= ALIGN(start
+ size
, ARCH_DMA_MINALIGN
);
354 invalidate_dcache_range(start
, end
);
357 static void eqos_flush_buffer(void *buf
, size_t size
)
359 flush_cache((unsigned long)buf
, size
);
362 static int eqos_mdio_wait_idle(struct eqos_priv
*eqos
)
364 return wait_for_bit(__func__
, &eqos
->mac_regs
->mdio_address
,
365 EQOS_MAC_MDIO_ADDRESS_GB
, false, 1000000, true);
368 static int eqos_mdio_read(struct mii_dev
*bus
, int mdio_addr
, int mdio_devad
,
371 struct eqos_priv
*eqos
= bus
->priv
;
375 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__
, eqos
->dev
, mdio_addr
,
378 ret
= eqos_mdio_wait_idle(eqos
);
380 error("MDIO not idle at entry");
384 val
= readl(&eqos
->mac_regs
->mdio_address
);
385 val
&= EQOS_MAC_MDIO_ADDRESS_SKAP
|
386 EQOS_MAC_MDIO_ADDRESS_C45E
;
387 val
|= (mdio_addr
<< EQOS_MAC_MDIO_ADDRESS_PA_SHIFT
) |
388 (mdio_reg
<< EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT
) |
389 (EQOS_MAC_MDIO_ADDRESS_CR_20_35
<<
390 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT
) |
391 (EQOS_MAC_MDIO_ADDRESS_GOC_READ
<<
392 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT
) |
393 EQOS_MAC_MDIO_ADDRESS_GB
;
394 writel(val
, &eqos
->mac_regs
->mdio_address
);
398 ret
= eqos_mdio_wait_idle(eqos
);
400 error("MDIO read didn't complete");
404 val
= readl(&eqos
->mac_regs
->mdio_data
);
405 val
&= EQOS_MAC_MDIO_DATA_GD_MASK
;
407 debug("%s: val=%x\n", __func__
, val
);
412 static int eqos_mdio_write(struct mii_dev
*bus
, int mdio_addr
, int mdio_devad
,
413 int mdio_reg
, u16 mdio_val
)
415 struct eqos_priv
*eqos
= bus
->priv
;
419 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__
, eqos
->dev
,
420 mdio_addr
, mdio_reg
, mdio_val
);
422 ret
= eqos_mdio_wait_idle(eqos
);
424 error("MDIO not idle at entry");
428 writel(mdio_val
, &eqos
->mac_regs
->mdio_data
);
430 val
= readl(&eqos
->mac_regs
->mdio_address
);
431 val
&= EQOS_MAC_MDIO_ADDRESS_SKAP
|
432 EQOS_MAC_MDIO_ADDRESS_C45E
;
433 val
|= (mdio_addr
<< EQOS_MAC_MDIO_ADDRESS_PA_SHIFT
) |
434 (mdio_reg
<< EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT
) |
435 (EQOS_MAC_MDIO_ADDRESS_CR_20_35
<<
436 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT
) |
437 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE
<<
438 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT
) |
439 EQOS_MAC_MDIO_ADDRESS_GB
;
440 writel(val
, &eqos
->mac_regs
->mdio_address
);
444 ret
= eqos_mdio_wait_idle(eqos
);
446 error("MDIO read didn't complete");
453 static int eqos_start_clks_tegra186(struct udevice
*dev
)
455 struct eqos_priv
*eqos
= dev_get_priv(dev
);
458 debug("%s(dev=%p):\n", __func__
, dev
);
460 ret
= clk_enable(&eqos
->clk_slave_bus
);
462 error("clk_enable(clk_slave_bus) failed: %d", ret
);
466 ret
= clk_enable(&eqos
->clk_master_bus
);
468 error("clk_enable(clk_master_bus) failed: %d", ret
);
469 goto err_disable_clk_slave_bus
;
472 ret
= clk_enable(&eqos
->clk_rx
);
474 error("clk_enable(clk_rx) failed: %d", ret
);
475 goto err_disable_clk_master_bus
;
478 ret
= clk_enable(&eqos
->clk_ptp_ref
);
480 error("clk_enable(clk_ptp_ref) failed: %d", ret
);
481 goto err_disable_clk_rx
;
484 ret
= clk_set_rate(&eqos
->clk_ptp_ref
, 125 * 1000 * 1000);
486 error("clk_set_rate(clk_ptp_ref) failed: %d", ret
);
487 goto err_disable_clk_ptp_ref
;
490 ret
= clk_enable(&eqos
->clk_tx
);
492 error("clk_enable(clk_tx) failed: %d", ret
);
493 goto err_disable_clk_ptp_ref
;
496 debug("%s: OK\n", __func__
);
499 err_disable_clk_ptp_ref
:
500 clk_disable(&eqos
->clk_ptp_ref
);
502 clk_disable(&eqos
->clk_rx
);
503 err_disable_clk_master_bus
:
504 clk_disable(&eqos
->clk_master_bus
);
505 err_disable_clk_slave_bus
:
506 clk_disable(&eqos
->clk_slave_bus
);
508 debug("%s: FAILED: %d\n", __func__
, ret
);
512 void eqos_stop_clks_tegra186(struct udevice
*dev
)
514 struct eqos_priv
*eqos
= dev_get_priv(dev
);
516 debug("%s(dev=%p):\n", __func__
, dev
);
518 clk_disable(&eqos
->clk_tx
);
519 clk_disable(&eqos
->clk_ptp_ref
);
520 clk_disable(&eqos
->clk_rx
);
521 clk_disable(&eqos
->clk_master_bus
);
522 clk_disable(&eqos
->clk_slave_bus
);
524 debug("%s: OK\n", __func__
);
527 static int eqos_start_resets_tegra186(struct udevice
*dev
)
529 struct eqos_priv
*eqos
= dev_get_priv(dev
);
532 debug("%s(dev=%p):\n", __func__
, dev
);
534 ret
= dm_gpio_set_value(&eqos
->phy_reset_gpio
, 1);
536 error("dm_gpio_set_value(phy_reset, assert) failed: %d", ret
);
542 ret
= dm_gpio_set_value(&eqos
->phy_reset_gpio
, 0);
544 error("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret
);
548 ret
= reset_assert(&eqos
->reset_ctl
);
550 error("reset_assert() failed: %d", ret
);
556 ret
= reset_deassert(&eqos
->reset_ctl
);
558 error("reset_deassert() failed: %d", ret
);
562 debug("%s: OK\n", __func__
);
566 static int eqos_stop_resets_tegra186(struct udevice
*dev
)
568 struct eqos_priv
*eqos
= dev_get_priv(dev
);
570 reset_assert(&eqos
->reset_ctl
);
571 dm_gpio_set_value(&eqos
->phy_reset_gpio
, 1);
576 static int eqos_calibrate_pads_tegra186(struct udevice
*dev
)
578 struct eqos_priv
*eqos
= dev_get_priv(dev
);
581 debug("%s(dev=%p):\n", __func__
, dev
);
583 setbits_le32(&eqos
->tegra186_regs
->sdmemcomppadctrl
,
584 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD
);
588 setbits_le32(&eqos
->tegra186_regs
->auto_cal_config
,
589 EQOS_AUTO_CAL_CONFIG_START
| EQOS_AUTO_CAL_CONFIG_ENABLE
);
591 ret
= wait_for_bit(__func__
, &eqos
->tegra186_regs
->auto_cal_status
,
592 EQOS_AUTO_CAL_STATUS_ACTIVE
, true, 10, false);
594 error("calibrate didn't start");
598 ret
= wait_for_bit(__func__
, &eqos
->tegra186_regs
->auto_cal_status
,
599 EQOS_AUTO_CAL_STATUS_ACTIVE
, false, 10, false);
601 error("calibrate didn't finish");
608 clrbits_le32(&eqos
->tegra186_regs
->sdmemcomppadctrl
,
609 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD
);
611 debug("%s: returns %d\n", __func__
, ret
);
616 static int eqos_disable_calibration_tegra186(struct udevice
*dev
)
618 struct eqos_priv
*eqos
= dev_get_priv(dev
);
620 debug("%s(dev=%p):\n", __func__
, dev
);
622 clrbits_le32(&eqos
->tegra186_regs
->auto_cal_config
,
623 EQOS_AUTO_CAL_CONFIG_ENABLE
);
628 static ulong
eqos_get_tick_clk_rate_tegra186(struct udevice
*dev
)
630 struct eqos_priv
*eqos
= dev_get_priv(dev
);
632 return clk_get_rate(&eqos
->clk_slave_bus
);
635 static int eqos_set_full_duplex(struct udevice
*dev
)
637 struct eqos_priv
*eqos
= dev_get_priv(dev
);
639 debug("%s(dev=%p):\n", __func__
, dev
);
641 setbits_le32(&eqos
->mac_regs
->configuration
, EQOS_MAC_CONFIGURATION_DM
);
646 static int eqos_set_half_duplex(struct udevice
*dev
)
648 struct eqos_priv
*eqos
= dev_get_priv(dev
);
650 debug("%s(dev=%p):\n", __func__
, dev
);
652 clrbits_le32(&eqos
->mac_regs
->configuration
, EQOS_MAC_CONFIGURATION_DM
);
654 /* WAR: Flush TX queue when switching to half-duplex */
655 setbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
656 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ
);
661 static int eqos_set_gmii_speed(struct udevice
*dev
)
663 struct eqos_priv
*eqos
= dev_get_priv(dev
);
665 debug("%s(dev=%p):\n", __func__
, dev
);
667 clrbits_le32(&eqos
->mac_regs
->configuration
,
668 EQOS_MAC_CONFIGURATION_PS
| EQOS_MAC_CONFIGURATION_FES
);
673 static int eqos_set_mii_speed_100(struct udevice
*dev
)
675 struct eqos_priv
*eqos
= dev_get_priv(dev
);
677 debug("%s(dev=%p):\n", __func__
, dev
);
679 setbits_le32(&eqos
->mac_regs
->configuration
,
680 EQOS_MAC_CONFIGURATION_PS
| EQOS_MAC_CONFIGURATION_FES
);
685 static int eqos_set_mii_speed_10(struct udevice
*dev
)
687 struct eqos_priv
*eqos
= dev_get_priv(dev
);
689 debug("%s(dev=%p):\n", __func__
, dev
);
691 clrsetbits_le32(&eqos
->mac_regs
->configuration
,
692 EQOS_MAC_CONFIGURATION_FES
, EQOS_MAC_CONFIGURATION_PS
);
697 static int eqos_set_tx_clk_speed_tegra186(struct udevice
*dev
)
699 struct eqos_priv
*eqos
= dev_get_priv(dev
);
703 debug("%s(dev=%p):\n", __func__
, dev
);
705 switch (eqos
->phy
->speed
) {
707 rate
= 125 * 1000 * 1000;
710 rate
= 25 * 1000 * 1000;
713 rate
= 2.5 * 1000 * 1000;
716 error("invalid speed %d", eqos
->phy
->speed
);
720 ret
= clk_set_rate(&eqos
->clk_tx
, rate
);
722 error("clk_set_rate(tx_clk, %lu) failed: %d", rate
, ret
);
729 static int eqos_adjust_link(struct udevice
*dev
)
731 struct eqos_priv
*eqos
= dev_get_priv(dev
);
735 debug("%s(dev=%p):\n", __func__
, dev
);
737 if (eqos
->phy
->duplex
)
738 ret
= eqos_set_full_duplex(dev
);
740 ret
= eqos_set_half_duplex(dev
);
742 error("eqos_set_*_duplex() failed: %d", ret
);
746 switch (eqos
->phy
->speed
) {
748 en_calibration
= true;
749 ret
= eqos_set_gmii_speed(dev
);
752 en_calibration
= true;
753 ret
= eqos_set_mii_speed_100(dev
);
756 en_calibration
= false;
757 ret
= eqos_set_mii_speed_10(dev
);
760 error("invalid speed %d", eqos
->phy
->speed
);
764 error("eqos_set_*mii_speed*() failed: %d", ret
);
768 if (en_calibration
) {
769 ret
= eqos_calibrate_pads_tegra186(dev
);
771 error("eqos_calibrate_pads_tegra186() failed: %d", ret
);
775 ret
= eqos_disable_calibration_tegra186(dev
);
777 error("eqos_disable_calibration_tegra186() failed: %d",
783 ret
= eqos_set_tx_clk_speed_tegra186(dev
);
785 error("eqos_set_tx_clk_speed_tegra186() failed: %d", ret
);
792 static int eqos_write_hwaddr(struct udevice
*dev
)
794 struct eth_pdata
*plat
= dev_get_platdata(dev
);
795 struct eqos_priv
*eqos
= dev_get_priv(dev
);
799 * This function may be called before start() or after stop(). At that
800 * time, on at least some configurations of the EQoS HW, all clocks to
801 * the EQoS HW block will be stopped, and a reset signal applied. If
802 * any register access is attempted in this state, bus timeouts or CPU
803 * hangs may occur. This check prevents that.
805 * A simple solution to this problem would be to not implement
806 * write_hwaddr(), since start() always writes the MAC address into HW
807 * anyway. However, it is desirable to implement write_hwaddr() to
808 * support the case of SW that runs subsequent to U-Boot which expects
809 * the MAC address to already be programmed into the EQoS registers,
810 * which must happen irrespective of whether the U-Boot user (or
811 * scripts) actually made use of the EQoS device, and hence
812 * irrespective of whether start() was ever called.
814 * Note that this requirement by subsequent SW is not valid for
815 * Tegra186, and is likely not valid for any non-PCI instantiation of
816 * the EQoS HW block. This function is implemented solely as
817 * future-proofing with the expectation the driver will eventually be
818 * ported to some system where the expectation above is true.
820 if (!eqos
->config
->reg_access_always_ok
&& !eqos
->reg_access_ok
)
823 /* Update the MAC address */
824 val
= (plat
->enetaddr
[5] << 8) |
826 writel(val
, &eqos
->mac_regs
->address0_high
);
827 val
= (plat
->enetaddr
[3] << 24) |
828 (plat
->enetaddr
[2] << 16) |
829 (plat
->enetaddr
[1] << 8) |
831 writel(val
, &eqos
->mac_regs
->address0_low
);
836 static int eqos_start(struct udevice
*dev
)
838 struct eqos_priv
*eqos
= dev_get_priv(dev
);
841 u32 val
, tx_fifo_sz
, rx_fifo_sz
, tqs
, rqs
, pbl
;
844 debug("%s(dev=%p):\n", __func__
, dev
);
846 eqos
->tx_desc_idx
= 0;
847 eqos
->rx_desc_idx
= 0;
849 ret
= eqos_start_clks_tegra186(dev
);
851 error("eqos_start_clks_tegra186() failed: %d", ret
);
855 ret
= eqos_start_resets_tegra186(dev
);
857 error("eqos_start_resets_tegra186() failed: %d", ret
);
863 eqos
->reg_access_ok
= true;
865 ret
= wait_for_bit(__func__
, &eqos
->dma_regs
->mode
,
866 EQOS_DMA_MODE_SWR
, false, 10, false);
868 error("EQOS_DMA_MODE_SWR stuck");
869 goto err_stop_resets
;
872 ret
= eqos_calibrate_pads_tegra186(dev
);
874 error("eqos_calibrate_pads_tegra186() failed: %d", ret
);
875 goto err_stop_resets
;
878 rate
= eqos_get_tick_clk_rate_tegra186(dev
);
879 val
= (rate
/ 1000000) - 1;
880 writel(val
, &eqos
->mac_regs
->us_tic_counter
);
882 eqos
->phy
= phy_connect(eqos
->mii
, 0, dev
, 0);
884 error("phy_connect() failed");
885 goto err_stop_resets
;
887 ret
= phy_config(eqos
->phy
);
889 error("phy_config() failed: %d", ret
);
890 goto err_shutdown_phy
;
892 ret
= phy_startup(eqos
->phy
);
894 error("phy_startup() failed: %d", ret
);
895 goto err_shutdown_phy
;
898 if (!eqos
->phy
->link
) {
900 goto err_shutdown_phy
;
903 ret
= eqos_adjust_link(dev
);
905 error("eqos_adjust_link() failed: %d", ret
);
906 goto err_shutdown_phy
;
911 /* Enable Store and Forward mode for TX */
912 /* Program Tx operating mode */
913 setbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
914 EQOS_MTL_TXQ0_OPERATION_MODE_TSF
|
915 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED
<<
916 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT
));
918 /* Transmit Queue weight */
919 writel(0x10, &eqos
->mtl_regs
->txq0_quantum_weight
);
921 /* Enable Store and Forward mode for RX, since no jumbo frame */
922 setbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
923 EQOS_MTL_RXQ0_OPERATION_MODE_RSF
);
925 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
926 val
= readl(&eqos
->mac_regs
->hw_feature1
);
927 tx_fifo_sz
= (val
>> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT
) &
928 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK
;
929 rx_fifo_sz
= (val
>> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT
) &
930 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK
;
933 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
934 * r/tqs is encoded as (n / 256) - 1.
936 tqs
= (128 << tx_fifo_sz
) / 256 - 1;
937 rqs
= (128 << rx_fifo_sz
) / 256 - 1;
939 clrsetbits_le32(&eqos
->mtl_regs
->txq0_operation_mode
,
940 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK
<<
941 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT
,
942 tqs
<< EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT
);
943 clrsetbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
944 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK
<<
945 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT
,
946 rqs
<< EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT
);
948 /* Flow control used only if each channel gets 4KB or more FIFO */
949 if (rqs
>= ((4096 / 256) - 1)) {
952 setbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
953 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC
);
956 * Set Threshold for Activating Flow Contol space for min 2
957 * frames ie, (1500 * 1) = 1500 bytes.
959 * Set Threshold for Deactivating Flow Contol for space of
960 * min 1 frame (frame size 1500bytes) in receive fifo
962 if (rqs
== ((4096 / 256) - 1)) {
964 * This violates the above formula because of FIFO size
965 * limit therefore overflow may occur inspite of this.
967 rfd
= 0x3; /* Full-3K */
968 rfa
= 0x1; /* Full-1.5K */
969 } else if (rqs
== ((8192 / 256) - 1)) {
970 rfd
= 0x6; /* Full-4K */
971 rfa
= 0xa; /* Full-6K */
972 } else if (rqs
== ((16384 / 256) - 1)) {
973 rfd
= 0x6; /* Full-4K */
974 rfa
= 0x12; /* Full-10K */
976 rfd
= 0x6; /* Full-4K */
977 rfa
= 0x1E; /* Full-16K */
980 clrsetbits_le32(&eqos
->mtl_regs
->rxq0_operation_mode
,
981 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK
<<
982 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT
) |
983 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK
<<
984 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT
),
986 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT
) |
988 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT
));
993 clrsetbits_le32(&eqos
->mac_regs
->rxq_ctrl0
,
994 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK
<<
995 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT
,
996 EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB
<<
997 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT
);
999 /* Set TX flow control parameters */
1000 /* Set Pause Time */
1001 setbits_le32(&eqos
->mac_regs
->q0_tx_flow_ctrl
,
1002 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT
);
1003 /* Assign priority for TX flow control */
1004 clrbits_le32(&eqos
->mac_regs
->txq_prty_map0
,
1005 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK
<<
1006 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT
);
1007 /* Assign priority for RX flow control */
1008 clrbits_le32(&eqos
->mac_regs
->rxq_ctrl2
,
1009 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK
<<
1010 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT
);
1011 /* Enable flow control */
1012 setbits_le32(&eqos
->mac_regs
->q0_tx_flow_ctrl
,
1013 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE
);
1014 setbits_le32(&eqos
->mac_regs
->rx_flow_ctrl
,
1015 EQOS_MAC_RX_FLOW_CTRL_RFE
);
1017 clrsetbits_le32(&eqos
->mac_regs
->configuration
,
1018 EQOS_MAC_CONFIGURATION_GPSLCE
|
1019 EQOS_MAC_CONFIGURATION_WD
|
1020 EQOS_MAC_CONFIGURATION_JD
|
1021 EQOS_MAC_CONFIGURATION_JE
,
1022 EQOS_MAC_CONFIGURATION_CST
|
1023 EQOS_MAC_CONFIGURATION_ACS
);
1025 eqos_write_hwaddr(dev
);
1029 /* Enable OSP mode */
1030 setbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1031 EQOS_DMA_CH0_TX_CONTROL_OSP
);
1033 /* RX buffer size. Must be a multiple of bus width */
1034 clrsetbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1035 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK
<<
1036 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT
,
1037 EQOS_MAX_PACKET_SIZE
<<
1038 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT
);
1040 setbits_le32(&eqos
->dma_regs
->ch0_control
,
1041 EQOS_DMA_CH0_CONTROL_PBLX8
);
1044 * Burst length must be < 1/2 FIFO size.
1045 * FIFO size in tqs is encoded as (n / 256) - 1.
1046 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1047 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1052 clrsetbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1053 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK
<<
1054 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT
,
1055 pbl
<< EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT
);
1057 clrsetbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1058 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK
<<
1059 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT
,
1060 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT
);
1062 /* DMA performance configuration */
1063 val
= (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT
) |
1064 EQOS_DMA_SYSBUS_MODE_EAME
| EQOS_DMA_SYSBUS_MODE_BLEN16
|
1065 EQOS_DMA_SYSBUS_MODE_BLEN8
| EQOS_DMA_SYSBUS_MODE_BLEN4
;
1066 writel(val
, &eqos
->dma_regs
->sysbus_mode
);
1068 /* Set up descriptors */
1070 memset(eqos
->descs
, 0, EQOS_DESCRIPTORS_SIZE
);
1071 for (i
= 0; i
< EQOS_DESCRIPTORS_RX
; i
++) {
1072 struct eqos_desc
*rx_desc
= &(eqos
->rx_descs
[i
]);
1073 rx_desc
->des0
= (u32
)(ulong
)(eqos
->rx_dma_buf
+
1074 (i
* EQOS_MAX_PACKET_SIZE
));
1075 rx_desc
->des3
|= EQOS_DESC3_OWN
| EQOS_DESC3_BUF1V
;
1077 flush_cache((unsigned long)eqos
->descs
, EQOS_DESCRIPTORS_SIZE
);
1079 writel(0, &eqos
->dma_regs
->ch0_txdesc_list_haddress
);
1080 writel((ulong
)eqos
->tx_descs
, &eqos
->dma_regs
->ch0_txdesc_list_address
);
1081 writel(EQOS_DESCRIPTORS_TX
- 1,
1082 &eqos
->dma_regs
->ch0_txdesc_ring_length
);
1084 writel(0, &eqos
->dma_regs
->ch0_rxdesc_list_haddress
);
1085 writel((ulong
)eqos
->rx_descs
, &eqos
->dma_regs
->ch0_rxdesc_list_address
);
1086 writel(EQOS_DESCRIPTORS_RX
- 1,
1087 &eqos
->dma_regs
->ch0_rxdesc_ring_length
);
1089 /* Enable everything */
1091 setbits_le32(&eqos
->mac_regs
->configuration
,
1092 EQOS_MAC_CONFIGURATION_TE
| EQOS_MAC_CONFIGURATION_RE
);
1094 setbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1095 EQOS_DMA_CH0_TX_CONTROL_ST
);
1096 setbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1097 EQOS_DMA_CH0_RX_CONTROL_SR
);
1099 /* TX tail pointer not written until we need to TX a packet */
1101 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1102 * first descriptor, implying all descriptors were available. However,
1103 * that's not distinguishable from none of the descriptors being
1106 last_rx_desc
= (ulong
)&(eqos
->rx_descs
[(EQOS_DESCRIPTORS_RX
- 1)]);
1107 writel(last_rx_desc
, &eqos
->dma_regs
->ch0_rxdesc_tail_pointer
);
1109 eqos
->started
= true;
1111 debug("%s: OK\n", __func__
);
1115 phy_shutdown(eqos
->phy
);
1118 eqos_stop_resets_tegra186(dev
);
1120 eqos_stop_clks_tegra186(dev
);
1122 error("FAILED: %d", ret
);
1126 void eqos_stop(struct udevice
*dev
)
1128 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1131 debug("%s(dev=%p):\n", __func__
, dev
);
1135 eqos
->started
= false;
1136 eqos
->reg_access_ok
= false;
1138 /* Disable TX DMA */
1139 clrbits_le32(&eqos
->dma_regs
->ch0_tx_control
,
1140 EQOS_DMA_CH0_TX_CONTROL_ST
);
1142 /* Wait for TX all packets to drain out of MTL */
1143 for (i
= 0; i
< 1000000; i
++) {
1144 u32 val
= readl(&eqos
->mtl_regs
->txq0_debug
);
1145 u32 trcsts
= (val
>> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT
) &
1146 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK
;
1147 u32 txqsts
= val
& EQOS_MTL_TXQ0_DEBUG_TXQSTS
;
1148 if ((trcsts
!= 1) && (!txqsts
))
1152 /* Turn off MAC TX and RX */
1153 clrbits_le32(&eqos
->mac_regs
->configuration
,
1154 EQOS_MAC_CONFIGURATION_TE
| EQOS_MAC_CONFIGURATION_RE
);
1156 /* Wait for all RX packets to drain out of MTL */
1157 for (i
= 0; i
< 1000000; i
++) {
1158 u32 val
= readl(&eqos
->mtl_regs
->rxq0_debug
);
1159 u32 prxq
= (val
>> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT
) &
1160 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK
;
1161 u32 rxqsts
= (val
>> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT
) &
1162 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK
;
1163 if ((!prxq
) && (!rxqsts
))
1167 /* Turn off RX DMA */
1168 clrbits_le32(&eqos
->dma_regs
->ch0_rx_control
,
1169 EQOS_DMA_CH0_RX_CONTROL_SR
);
1172 phy_shutdown(eqos
->phy
);
1175 eqos_stop_resets_tegra186(dev
);
1176 eqos_stop_clks_tegra186(dev
);
1178 debug("%s: OK\n", __func__
);
1181 int eqos_send(struct udevice
*dev
, void *packet
, int length
)
1183 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1184 struct eqos_desc
*tx_desc
;
1187 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__
, dev
, packet
,
1190 memcpy(eqos
->tx_dma_buf
, packet
, length
);
1191 eqos_flush_buffer(eqos
->tx_dma_buf
, length
);
1193 tx_desc
= &(eqos
->tx_descs
[eqos
->tx_desc_idx
]);
1194 eqos
->tx_desc_idx
++;
1195 eqos
->tx_desc_idx
%= EQOS_DESCRIPTORS_TX
;
1197 tx_desc
->des0
= (ulong
)eqos
->tx_dma_buf
;
1199 tx_desc
->des2
= length
;
1201 * Make sure that if HW sees the _OWN write below, it will see all the
1202 * writes to the rest of the descriptor too.
1205 tx_desc
->des3
= EQOS_DESC3_OWN
| EQOS_DESC3_FD
| EQOS_DESC3_LD
| length
;
1206 eqos_flush_desc(tx_desc
);
1208 writel((ulong
)(tx_desc
+ 1), &eqos
->dma_regs
->ch0_txdesc_tail_pointer
);
1210 for (i
= 0; i
< 1000000; i
++) {
1211 eqos_inval_desc(tx_desc
);
1212 if (!(readl(&tx_desc
->des3
) & EQOS_DESC3_OWN
))
1217 debug("%s: TX timeout\n", __func__
);
1222 int eqos_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
1224 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1225 struct eqos_desc
*rx_desc
;
1228 debug("%s(dev=%p, flags=%x):\n", __func__
, dev
, flags
);
1230 rx_desc
= &(eqos
->rx_descs
[eqos
->rx_desc_idx
]);
1231 if (rx_desc
->des3
& EQOS_DESC3_OWN
) {
1232 debug("%s: RX packet not available\n", __func__
);
1236 *packetp
= eqos
->rx_dma_buf
+
1237 (eqos
->rx_desc_idx
* EQOS_MAX_PACKET_SIZE
);
1238 length
= rx_desc
->des3
& 0x7fff;
1239 debug("%s: *packetp=%p, length=%d\n", __func__
, *packetp
, length
);
1241 eqos_inval_buffer(*packetp
, length
);
1246 int eqos_free_pkt(struct udevice
*dev
, uchar
*packet
, int length
)
1248 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1249 uchar
*packet_expected
;
1250 struct eqos_desc
*rx_desc
;
1252 debug("%s(packet=%p, length=%d)\n", __func__
, packet
, length
);
1254 packet_expected
= eqos
->rx_dma_buf
+
1255 (eqos
->rx_desc_idx
* EQOS_MAX_PACKET_SIZE
);
1256 if (packet
!= packet_expected
) {
1257 debug("%s: Unexpected packet (expected %p)\n", __func__
,
1262 rx_desc
= &(eqos
->rx_descs
[eqos
->rx_desc_idx
]);
1263 rx_desc
->des0
= (u32
)(ulong
)packet
;
1267 * Make sure that if HW sees the _OWN write below, it will see all the
1268 * writes to the rest of the descriptor too.
1271 rx_desc
->des3
|= EQOS_DESC3_OWN
| EQOS_DESC3_BUF1V
;
1272 eqos_flush_desc(rx_desc
);
1274 writel((ulong
)rx_desc
, &eqos
->dma_regs
->ch0_rxdesc_tail_pointer
);
1276 eqos
->rx_desc_idx
++;
1277 eqos
->rx_desc_idx
%= EQOS_DESCRIPTORS_RX
;
1282 static int eqos_probe_resources_core(struct udevice
*dev
)
1284 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1287 debug("%s(dev=%p):\n", __func__
, dev
);
1289 eqos
->descs
= eqos_alloc_descs(EQOS_DESCRIPTORS_TX
+
1290 EQOS_DESCRIPTORS_RX
);
1292 debug("%s: eqos_alloc_descs() failed\n", __func__
);
1296 eqos
->tx_descs
= (struct eqos_desc
*)eqos
->descs
;
1297 eqos
->rx_descs
= (eqos
->tx_descs
+ EQOS_DESCRIPTORS_TX
);
1298 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__
, eqos
->tx_descs
,
1301 eqos
->tx_dma_buf
= memalign(EQOS_BUFFER_ALIGN
, EQOS_MAX_PACKET_SIZE
);
1302 if (!eqos
->tx_dma_buf
) {
1303 debug("%s: memalign(tx_dma_buf) failed\n", __func__
);
1305 goto err_free_descs
;
1307 debug("%s: rx_dma_buf=%p\n", __func__
, eqos
->rx_dma_buf
);
1309 eqos
->rx_dma_buf
= memalign(EQOS_BUFFER_ALIGN
, EQOS_RX_BUFFER_SIZE
);
1310 if (!eqos
->rx_dma_buf
) {
1311 debug("%s: memalign(rx_dma_buf) failed\n", __func__
);
1313 goto err_free_tx_dma_buf
;
1315 debug("%s: tx_dma_buf=%p\n", __func__
, eqos
->tx_dma_buf
);
1317 eqos
->rx_pkt
= malloc(EQOS_MAX_PACKET_SIZE
);
1318 if (!eqos
->rx_pkt
) {
1319 debug("%s: malloc(rx_pkt) failed\n", __func__
);
1321 goto err_free_rx_dma_buf
;
1323 debug("%s: rx_pkt=%p\n", __func__
, eqos
->rx_pkt
);
1325 debug("%s: OK\n", __func__
);
1328 err_free_rx_dma_buf
:
1329 free(eqos
->rx_dma_buf
);
1330 err_free_tx_dma_buf
:
1331 free(eqos
->tx_dma_buf
);
1333 eqos_free_descs(eqos
->descs
);
1336 debug("%s: returns %d\n", __func__
, ret
);
1340 static int eqos_remove_resources_core(struct udevice
*dev
)
1342 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1344 debug("%s(dev=%p):\n", __func__
, dev
);
1347 free(eqos
->rx_dma_buf
);
1348 free(eqos
->tx_dma_buf
);
1349 eqos_free_descs(eqos
->descs
);
1351 debug("%s: OK\n", __func__
);
1355 static int eqos_probe_resources_tegra186(struct udevice
*dev
)
1357 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1360 debug("%s(dev=%p):\n", __func__
, dev
);
1362 ret
= reset_get_by_name(dev
, "eqos", &eqos
->reset_ctl
);
1364 error("reset_get_by_name(rst) failed: %d", ret
);
1368 ret
= gpio_request_by_name(dev
, "phy-reset-gpios", 0,
1369 &eqos
->phy_reset_gpio
,
1370 GPIOD_IS_OUT
| GPIOD_IS_OUT_ACTIVE
);
1372 error("gpio_request_by_name(phy reset) failed: %d", ret
);
1373 goto err_free_reset_eqos
;
1376 ret
= clk_get_by_name(dev
, "slave_bus", &eqos
->clk_slave_bus
);
1378 error("clk_get_by_name(slave_bus) failed: %d", ret
);
1379 goto err_free_gpio_phy_reset
;
1382 ret
= clk_get_by_name(dev
, "master_bus", &eqos
->clk_master_bus
);
1384 error("clk_get_by_name(master_bus) failed: %d", ret
);
1385 goto err_free_clk_slave_bus
;
1388 ret
= clk_get_by_name(dev
, "rx", &eqos
->clk_rx
);
1390 error("clk_get_by_name(rx) failed: %d", ret
);
1391 goto err_free_clk_master_bus
;
1394 ret
= clk_get_by_name(dev
, "ptp_ref", &eqos
->clk_ptp_ref
);
1396 error("clk_get_by_name(ptp_ref) failed: %d", ret
);
1397 goto err_free_clk_rx
;
1401 ret
= clk_get_by_name(dev
, "tx", &eqos
->clk_tx
);
1403 error("clk_get_by_name(tx) failed: %d", ret
);
1404 goto err_free_clk_ptp_ref
;
1407 debug("%s: OK\n", __func__
);
1410 err_free_clk_ptp_ref
:
1411 clk_free(&eqos
->clk_ptp_ref
);
1413 clk_free(&eqos
->clk_rx
);
1414 err_free_clk_master_bus
:
1415 clk_free(&eqos
->clk_master_bus
);
1416 err_free_clk_slave_bus
:
1417 clk_free(&eqos
->clk_slave_bus
);
1418 err_free_gpio_phy_reset
:
1419 dm_gpio_free(dev
, &eqos
->phy_reset_gpio
);
1420 err_free_reset_eqos
:
1421 reset_free(&eqos
->reset_ctl
);
1423 debug("%s: returns %d\n", __func__
, ret
);
1427 static int eqos_remove_resources_tegra186(struct udevice
*dev
)
1429 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1431 debug("%s(dev=%p):\n", __func__
, dev
);
1433 clk_free(&eqos
->clk_tx
);
1434 clk_free(&eqos
->clk_ptp_ref
);
1435 clk_free(&eqos
->clk_rx
);
1436 clk_free(&eqos
->clk_slave_bus
);
1437 clk_free(&eqos
->clk_master_bus
);
1438 dm_gpio_free(dev
, &eqos
->phy_reset_gpio
);
1439 reset_free(&eqos
->reset_ctl
);
1441 debug("%s: OK\n", __func__
);
1445 static int eqos_probe(struct udevice
*dev
)
1447 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1450 debug("%s(dev=%p):\n", __func__
, dev
);
1453 eqos
->config
= (void *)dev_get_driver_data(dev
);
1455 eqos
->regs
= dev_get_addr(dev
);
1456 if (eqos
->regs
== FDT_ADDR_T_NONE
) {
1457 error("dev_get_addr() failed");
1460 eqos
->mac_regs
= (void *)(eqos
->regs
+ EQOS_MAC_REGS_BASE
);
1461 eqos
->mtl_regs
= (void *)(eqos
->regs
+ EQOS_MTL_REGS_BASE
);
1462 eqos
->dma_regs
= (void *)(eqos
->regs
+ EQOS_DMA_REGS_BASE
);
1463 eqos
->tegra186_regs
= (void *)(eqos
->regs
+ EQOS_TEGRA186_REGS_BASE
);
1465 ret
= eqos_probe_resources_core(dev
);
1467 error("eqos_probe_resources_core() failed: %d", ret
);
1471 ret
= eqos_probe_resources_tegra186(dev
);
1473 error("eqos_probe_resources_tegra186() failed: %d", ret
);
1474 goto err_remove_resources_core
;
1477 eqos
->mii
= mdio_alloc();
1479 error("mdio_alloc() failed");
1480 goto err_remove_resources_tegra
;
1482 eqos
->mii
->read
= eqos_mdio_read
;
1483 eqos
->mii
->write
= eqos_mdio_write
;
1484 eqos
->mii
->priv
= eqos
;
1485 strcpy(eqos
->mii
->name
, dev
->name
);
1487 ret
= mdio_register(eqos
->mii
);
1489 error("mdio_register() failed: %d", ret
);
1493 debug("%s: OK\n", __func__
);
1497 mdio_free(eqos
->mii
);
1498 err_remove_resources_tegra
:
1499 eqos_remove_resources_tegra186(dev
);
1500 err_remove_resources_core
:
1501 eqos_remove_resources_core(dev
);
1503 debug("%s: returns %d\n", __func__
, ret
);
1507 static int eqos_remove(struct udevice
*dev
)
1509 struct eqos_priv
*eqos
= dev_get_priv(dev
);
1511 debug("%s(dev=%p):\n", __func__
, dev
);
1513 mdio_unregister(eqos
->mii
);
1514 mdio_free(eqos
->mii
);
1515 eqos_remove_resources_tegra186(dev
);
1516 eqos_probe_resources_core(dev
);
1518 debug("%s: OK\n", __func__
);
1522 static const struct eth_ops eqos_ops
= {
1523 .start
= eqos_start
,
1527 .free_pkt
= eqos_free_pkt
,
1528 .write_hwaddr
= eqos_write_hwaddr
,
1531 static const struct eqos_config eqos_tegra186_config
= {
1532 .reg_access_always_ok
= false,
1535 static const struct udevice_id eqos_ids
[] = {
1537 .compatible
= "nvidia,tegra186-eqos",
1538 .data
= (ulong
)&eqos_tegra186_config
1543 U_BOOT_DRIVER(eth_eqos
) = {
1546 .of_match
= eqos_ids
,
1547 .probe
= eqos_probe
,
1548 .remove
= eqos_remove
,
1550 .priv_auto_alloc_size
= sizeof(struct eqos_priv
),
1551 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),