1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 * SPDX-License-Identifier: GPL-2.0+
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
34 #define TOUT_LOOP 100000
36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
39 #define E1000_DEFAULT_PCI_PBA 0x00000030
40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
42 /* NIC specific static variables go here */
44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
45 #define E1000_BUFFER_ALIGN 128
47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc
, tx_base
, 16, E1000_BUFFER_ALIGN
);
48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc
, rx_base
, 16, E1000_BUFFER_ALIGN
);
49 DEFINE_ALIGN_BUFFER(unsigned char, packet
, 4096, E1000_BUFFER_ALIGN
);
52 static int rx_tail
, rx_last
;
54 static struct pci_device_id e1000_supported
[] = {
55 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82542
},
56 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82543GC_FIBER
},
57 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82543GC_COPPER
},
58 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82544EI_COPPER
},
59 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82544EI_FIBER
},
60 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82544GC_COPPER
},
61 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82544GC_LOM
},
62 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82540EM
},
63 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82545EM_COPPER
},
64 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82545GM_COPPER
},
65 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82546EB_COPPER
},
66 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82545EM_FIBER
},
67 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82546EB_FIBER
},
68 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82546GB_COPPER
},
69 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82540EM_LOM
},
70 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82541ER
},
71 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82541GI_LF
},
73 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_COPPER
},
74 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_FIBER
},
75 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_SERDES
},
76 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER
},
77 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER
},
78 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER
},
79 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE
},
80 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL
},
81 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD
},
82 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82572EI_COPPER
},
83 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82572EI_FIBER
},
84 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82572EI_SERDES
},
85 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82572EI
},
86 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82573E
},
87 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82573E_IAMT
},
88 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82573L
},
89 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82574L
},
90 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3
},
91 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT
},
92 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT
},
93 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT
},
94 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT
},
95 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED
},
96 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED
},
97 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_COPPER
},
98 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I211_COPPER
},
99 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS
},
100 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_SERDES
},
101 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS
},
102 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I210_1000BASEKX
},
107 /* Function forward declarations */
108 static int e1000_setup_link(struct eth_device
*nic
);
109 static int e1000_setup_fiber_link(struct eth_device
*nic
);
110 static int e1000_setup_copper_link(struct eth_device
*nic
);
111 static int e1000_phy_setup_autoneg(struct e1000_hw
*hw
);
112 static void e1000_config_collision_dist(struct e1000_hw
*hw
);
113 static int e1000_config_mac_to_phy(struct e1000_hw
*hw
);
114 static int e1000_config_fc_after_link_up(struct e1000_hw
*hw
);
115 static int e1000_check_for_link(struct eth_device
*nic
);
116 static int e1000_wait_autoneg(struct e1000_hw
*hw
);
117 static int e1000_get_speed_and_duplex(struct e1000_hw
*hw
, uint16_t * speed
,
119 static int e1000_read_phy_reg(struct e1000_hw
*hw
, uint32_t reg_addr
,
120 uint16_t * phy_data
);
121 static int e1000_write_phy_reg(struct e1000_hw
*hw
, uint32_t reg_addr
,
123 static int32_t e1000_phy_hw_reset(struct e1000_hw
*hw
);
124 static int e1000_phy_reset(struct e1000_hw
*hw
);
125 static int e1000_detect_gig_phy(struct e1000_hw
*hw
);
126 static void e1000_set_media_type(struct e1000_hw
*hw
);
128 static int32_t e1000_swfw_sync_acquire(struct e1000_hw
*hw
, uint16_t mask
);
129 static int32_t e1000_check_phy_reset_block(struct e1000_hw
*hw
);
131 #ifndef CONFIG_E1000_NO_NVM
132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
);
133 static int32_t e1000_read_eeprom(struct e1000_hw
*hw
, uint16_t offset
,
136 /******************************************************************************
137 * Raises the EEPROM's clock input.
139 * hw - Struct containing variables accessed by shared code
140 * eecd - EECD's current value
141 *****************************************************************************/
142 void e1000_raise_ee_clk(struct e1000_hw
*hw
, uint32_t * eecd
)
144 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
145 * wait 50 microseconds.
147 *eecd
= *eecd
| E1000_EECD_SK
;
148 E1000_WRITE_REG(hw
, EECD
, *eecd
);
149 E1000_WRITE_FLUSH(hw
);
153 /******************************************************************************
154 * Lowers the EEPROM's clock input.
156 * hw - Struct containing variables accessed by shared code
157 * eecd - EECD's current value
158 *****************************************************************************/
159 void e1000_lower_ee_clk(struct e1000_hw
*hw
, uint32_t * eecd
)
161 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
162 * wait 50 microseconds.
164 *eecd
= *eecd
& ~E1000_EECD_SK
;
165 E1000_WRITE_REG(hw
, EECD
, *eecd
);
166 E1000_WRITE_FLUSH(hw
);
170 /******************************************************************************
171 * Shift data bits out to the EEPROM.
173 * hw - Struct containing variables accessed by shared code
174 * data - data to send to the EEPROM
175 * count - number of bits to shift out
176 *****************************************************************************/
178 e1000_shift_out_ee_bits(struct e1000_hw
*hw
, uint16_t data
, uint16_t count
)
183 /* We need to shift "count" bits out to the EEPROM. So, value in the
184 * "data" parameter will be shifted out to the EEPROM one bit at a time.
185 * In order to do this, "data" must be broken down into bits.
187 mask
= 0x01 << (count
- 1);
188 eecd
= E1000_READ_REG(hw
, EECD
);
189 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
191 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
192 * and then raising and then lowering the clock (the SK bit controls
193 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
194 * by setting "DI" to "0" and then raising and then lowering the clock.
196 eecd
&= ~E1000_EECD_DI
;
199 eecd
|= E1000_EECD_DI
;
201 E1000_WRITE_REG(hw
, EECD
, eecd
);
202 E1000_WRITE_FLUSH(hw
);
206 e1000_raise_ee_clk(hw
, &eecd
);
207 e1000_lower_ee_clk(hw
, &eecd
);
213 /* We leave the "DI" bit set to "0" when we leave this routine. */
214 eecd
&= ~E1000_EECD_DI
;
215 E1000_WRITE_REG(hw
, EECD
, eecd
);
218 /******************************************************************************
219 * Shift data bits in from the EEPROM
221 * hw - Struct containing variables accessed by shared code
222 *****************************************************************************/
224 e1000_shift_in_ee_bits(struct e1000_hw
*hw
, uint16_t count
)
230 /* In order to read a register from the EEPROM, we need to shift 'count'
231 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
232 * input to the EEPROM (setting the SK bit), and then reading the
233 * value of the "DO" bit. During this "shifting in" process the
234 * "DI" bit should always be clear.
237 eecd
= E1000_READ_REG(hw
, EECD
);
239 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
242 for (i
= 0; i
< count
; i
++) {
244 e1000_raise_ee_clk(hw
, &eecd
);
246 eecd
= E1000_READ_REG(hw
, EECD
);
248 eecd
&= ~(E1000_EECD_DI
);
249 if (eecd
& E1000_EECD_DO
)
252 e1000_lower_ee_clk(hw
, &eecd
);
258 /******************************************************************************
259 * Returns EEPROM to a "standby" state
261 * hw - Struct containing variables accessed by shared code
262 *****************************************************************************/
263 void e1000_standby_eeprom(struct e1000_hw
*hw
)
265 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
268 eecd
= E1000_READ_REG(hw
, EECD
);
270 if (eeprom
->type
== e1000_eeprom_microwire
) {
271 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
272 E1000_WRITE_REG(hw
, EECD
, eecd
);
273 E1000_WRITE_FLUSH(hw
);
274 udelay(eeprom
->delay_usec
);
277 eecd
|= E1000_EECD_SK
;
278 E1000_WRITE_REG(hw
, EECD
, eecd
);
279 E1000_WRITE_FLUSH(hw
);
280 udelay(eeprom
->delay_usec
);
283 eecd
|= E1000_EECD_CS
;
284 E1000_WRITE_REG(hw
, EECD
, eecd
);
285 E1000_WRITE_FLUSH(hw
);
286 udelay(eeprom
->delay_usec
);
289 eecd
&= ~E1000_EECD_SK
;
290 E1000_WRITE_REG(hw
, EECD
, eecd
);
291 E1000_WRITE_FLUSH(hw
);
292 udelay(eeprom
->delay_usec
);
293 } else if (eeprom
->type
== e1000_eeprom_spi
) {
294 /* Toggle CS to flush commands */
295 eecd
|= E1000_EECD_CS
;
296 E1000_WRITE_REG(hw
, EECD
, eecd
);
297 E1000_WRITE_FLUSH(hw
);
298 udelay(eeprom
->delay_usec
);
299 eecd
&= ~E1000_EECD_CS
;
300 E1000_WRITE_REG(hw
, EECD
, eecd
);
301 E1000_WRITE_FLUSH(hw
);
302 udelay(eeprom
->delay_usec
);
306 /***************************************************************************
307 * Description: Determines if the onboard NVM is FLASH or EEPROM.
309 * hw - Struct containing variables accessed by shared code
310 ****************************************************************************/
311 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
)
317 if (hw
->mac_type
== e1000_ich8lan
)
320 if (hw
->mac_type
== e1000_82573
|| hw
->mac_type
== e1000_82574
) {
321 eecd
= E1000_READ_REG(hw
, EECD
);
323 /* Isolate bits 15 & 16 */
324 eecd
= ((eecd
>> 15) & 0x03);
326 /* If both bits are set, device is Flash type */
333 /******************************************************************************
334 * Prepares EEPROM for access
336 * hw - Struct containing variables accessed by shared code
338 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
339 * function should be called before issuing a command to the EEPROM.
340 *****************************************************************************/
341 int32_t e1000_acquire_eeprom(struct e1000_hw
*hw
)
343 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
344 uint32_t eecd
, i
= 0;
348 if (e1000_swfw_sync_acquire(hw
, E1000_SWFW_EEP_SM
))
349 return -E1000_ERR_SWFW_SYNC
;
350 eecd
= E1000_READ_REG(hw
, EECD
);
352 if (hw
->mac_type
!= e1000_82573
&& hw
->mac_type
!= e1000_82574
) {
353 /* Request EEPROM Access */
354 if (hw
->mac_type
> e1000_82544
) {
355 eecd
|= E1000_EECD_REQ
;
356 E1000_WRITE_REG(hw
, EECD
, eecd
);
357 eecd
= E1000_READ_REG(hw
, EECD
);
358 while ((!(eecd
& E1000_EECD_GNT
)) &&
359 (i
< E1000_EEPROM_GRANT_ATTEMPTS
)) {
362 eecd
= E1000_READ_REG(hw
, EECD
);
364 if (!(eecd
& E1000_EECD_GNT
)) {
365 eecd
&= ~E1000_EECD_REQ
;
366 E1000_WRITE_REG(hw
, EECD
, eecd
);
367 DEBUGOUT("Could not acquire EEPROM grant\n");
368 return -E1000_ERR_EEPROM
;
373 /* Setup EEPROM for Read/Write */
375 if (eeprom
->type
== e1000_eeprom_microwire
) {
376 /* Clear SK and DI */
377 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
378 E1000_WRITE_REG(hw
, EECD
, eecd
);
381 eecd
|= E1000_EECD_CS
;
382 E1000_WRITE_REG(hw
, EECD
, eecd
);
383 } else if (eeprom
->type
== e1000_eeprom_spi
) {
384 /* Clear SK and CS */
385 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
386 E1000_WRITE_REG(hw
, EECD
, eecd
);
390 return E1000_SUCCESS
;
393 /******************************************************************************
394 * Sets up eeprom variables in the hw struct. Must be called after mac_type
395 * is configured. Additionally, if this is ICH8, the flash controller GbE
396 * registers must be mapped, or this will crash.
398 * hw - Struct containing variables accessed by shared code
399 *****************************************************************************/
400 static int32_t e1000_init_eeprom_params(struct e1000_hw
*hw
)
402 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
404 int32_t ret_val
= E1000_SUCCESS
;
405 uint16_t eeprom_size
;
407 if (hw
->mac_type
== e1000_igb
)
408 eecd
= E1000_READ_REG(hw
, I210_EECD
);
410 eecd
= E1000_READ_REG(hw
, EECD
);
414 switch (hw
->mac_type
) {
415 case e1000_82542_rev2_0
:
416 case e1000_82542_rev2_1
:
419 eeprom
->type
= e1000_eeprom_microwire
;
420 eeprom
->word_size
= 64;
421 eeprom
->opcode_bits
= 3;
422 eeprom
->address_bits
= 6;
423 eeprom
->delay_usec
= 50;
424 eeprom
->use_eerd
= false;
425 eeprom
->use_eewr
= false;
429 case e1000_82545_rev_3
:
431 case e1000_82546_rev_3
:
432 eeprom
->type
= e1000_eeprom_microwire
;
433 eeprom
->opcode_bits
= 3;
434 eeprom
->delay_usec
= 50;
435 if (eecd
& E1000_EECD_SIZE
) {
436 eeprom
->word_size
= 256;
437 eeprom
->address_bits
= 8;
439 eeprom
->word_size
= 64;
440 eeprom
->address_bits
= 6;
442 eeprom
->use_eerd
= false;
443 eeprom
->use_eewr
= false;
446 case e1000_82541_rev_2
:
448 case e1000_82547_rev_2
:
449 if (eecd
& E1000_EECD_TYPE
) {
450 eeprom
->type
= e1000_eeprom_spi
;
451 eeprom
->opcode_bits
= 8;
452 eeprom
->delay_usec
= 1;
453 if (eecd
& E1000_EECD_ADDR_BITS
) {
454 eeprom
->page_size
= 32;
455 eeprom
->address_bits
= 16;
457 eeprom
->page_size
= 8;
458 eeprom
->address_bits
= 8;
461 eeprom
->type
= e1000_eeprom_microwire
;
462 eeprom
->opcode_bits
= 3;
463 eeprom
->delay_usec
= 50;
464 if (eecd
& E1000_EECD_ADDR_BITS
) {
465 eeprom
->word_size
= 256;
466 eeprom
->address_bits
= 8;
468 eeprom
->word_size
= 64;
469 eeprom
->address_bits
= 6;
472 eeprom
->use_eerd
= false;
473 eeprom
->use_eewr
= false;
477 eeprom
->type
= e1000_eeprom_spi
;
478 eeprom
->opcode_bits
= 8;
479 eeprom
->delay_usec
= 1;
480 if (eecd
& E1000_EECD_ADDR_BITS
) {
481 eeprom
->page_size
= 32;
482 eeprom
->address_bits
= 16;
484 eeprom
->page_size
= 8;
485 eeprom
->address_bits
= 8;
487 eeprom
->use_eerd
= false;
488 eeprom
->use_eewr
= false;
492 eeprom
->type
= e1000_eeprom_spi
;
493 eeprom
->opcode_bits
= 8;
494 eeprom
->delay_usec
= 1;
495 if (eecd
& E1000_EECD_ADDR_BITS
) {
496 eeprom
->page_size
= 32;
497 eeprom
->address_bits
= 16;
499 eeprom
->page_size
= 8;
500 eeprom
->address_bits
= 8;
502 if (e1000_is_onboard_nvm_eeprom(hw
) == false) {
503 eeprom
->use_eerd
= true;
504 eeprom
->use_eewr
= true;
506 eeprom
->type
= e1000_eeprom_flash
;
507 eeprom
->word_size
= 2048;
509 /* Ensure that the Autonomous FLASH update bit is cleared due to
510 * Flash update issue on parts which use a FLASH for NVM. */
511 eecd
&= ~E1000_EECD_AUPDEN
;
512 E1000_WRITE_REG(hw
, EECD
, eecd
);
515 case e1000_80003es2lan
:
516 eeprom
->type
= e1000_eeprom_spi
;
517 eeprom
->opcode_bits
= 8;
518 eeprom
->delay_usec
= 1;
519 if (eecd
& E1000_EECD_ADDR_BITS
) {
520 eeprom
->page_size
= 32;
521 eeprom
->address_bits
= 16;
523 eeprom
->page_size
= 8;
524 eeprom
->address_bits
= 8;
526 eeprom
->use_eerd
= true;
527 eeprom
->use_eewr
= false;
530 /* i210 has 4k of iNVM mapped as EEPROM */
531 eeprom
->type
= e1000_eeprom_invm
;
532 eeprom
->opcode_bits
= 8;
533 eeprom
->delay_usec
= 1;
534 eeprom
->page_size
= 32;
535 eeprom
->address_bits
= 16;
536 eeprom
->use_eerd
= true;
537 eeprom
->use_eewr
= false;
540 /* ich8lan does not support currently. if needed, please
541 * add corresponding code and functions.
548 eeprom
->type
= e1000_eeprom_ich8
;
549 eeprom
->use_eerd
= false;
550 eeprom
->use_eewr
= false;
551 eeprom
->word_size
= E1000_SHADOW_RAM_WORDS
;
552 uint32_t flash_size
= E1000_READ_ICH_FLASH_REG(hw
,
554 /* Zero the shadow RAM structure. But don't load it from NVM
555 * so as to save time for driver init */
556 if (hw
->eeprom_shadow_ram
!= NULL
) {
557 for (i
= 0; i
< E1000_SHADOW_RAM_WORDS
; i
++) {
558 hw
->eeprom_shadow_ram
[i
].modified
= false;
559 hw
->eeprom_shadow_ram
[i
].eeprom_word
= 0xFFFF;
563 hw
->flash_base_addr
= (flash_size
& ICH_GFPREG_BASE_MASK
) *
564 ICH_FLASH_SECTOR_SIZE
;
566 hw
->flash_bank_size
= ((flash_size
>> 16)
567 & ICH_GFPREG_BASE_MASK
) + 1;
568 hw
->flash_bank_size
-= (flash_size
& ICH_GFPREG_BASE_MASK
);
570 hw
->flash_bank_size
*= ICH_FLASH_SECTOR_SIZE
;
572 hw
->flash_bank_size
/= 2 * sizeof(uint16_t);
580 if (eeprom
->type
== e1000_eeprom_spi
||
581 eeprom
->type
== e1000_eeprom_invm
) {
582 /* eeprom_size will be an enum [0..8] that maps
583 * to eeprom sizes 128B to
584 * 32KB (incremented by powers of 2).
586 if (hw
->mac_type
<= e1000_82547_rev_2
) {
587 /* Set to default value for initial eeprom read. */
588 eeprom
->word_size
= 64;
589 ret_val
= e1000_read_eeprom(hw
, EEPROM_CFG
, 1,
593 eeprom_size
= (eeprom_size
& EEPROM_SIZE_MASK
)
594 >> EEPROM_SIZE_SHIFT
;
595 /* 256B eeprom size was not supported in earlier
596 * hardware, so we bump eeprom_size up one to
597 * ensure that "1" (which maps to 256B) is never
598 * the result used in the shifting logic below. */
602 eeprom_size
= (uint16_t)((eecd
&
603 E1000_EECD_SIZE_EX_MASK
) >>
604 E1000_EECD_SIZE_EX_SHIFT
);
607 eeprom
->word_size
= 1 << (eeprom_size
+ EEPROM_WORD_SIZE_SHIFT
);
612 /******************************************************************************
613 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
615 * hw - Struct containing variables accessed by shared code
616 *****************************************************************************/
618 e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
)
620 uint32_t attempts
= 100000;
622 int32_t done
= E1000_ERR_EEPROM
;
624 for (i
= 0; i
< attempts
; i
++) {
625 if (eerd
== E1000_EEPROM_POLL_READ
) {
626 if (hw
->mac_type
== e1000_igb
)
627 reg
= E1000_READ_REG(hw
, I210_EERD
);
629 reg
= E1000_READ_REG(hw
, EERD
);
631 if (hw
->mac_type
== e1000_igb
)
632 reg
= E1000_READ_REG(hw
, I210_EEWR
);
634 reg
= E1000_READ_REG(hw
, EEWR
);
637 if (reg
& E1000_EEPROM_RW_REG_DONE
) {
638 done
= E1000_SUCCESS
;
647 /******************************************************************************
648 * Reads a 16 bit word from the EEPROM using the EERD register.
650 * hw - Struct containing variables accessed by shared code
651 * offset - offset of word in the EEPROM to read
652 * data - word read from the EEPROM
653 * words - number of words to read
654 *****************************************************************************/
656 e1000_read_eeprom_eerd(struct e1000_hw
*hw
,
661 uint32_t i
, eerd
= 0;
664 for (i
= 0; i
< words
; i
++) {
665 eerd
= ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) +
666 E1000_EEPROM_RW_REG_START
;
668 if (hw
->mac_type
== e1000_igb
)
669 E1000_WRITE_REG(hw
, I210_EERD
, eerd
);
671 E1000_WRITE_REG(hw
, EERD
, eerd
);
673 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_READ
);
678 if (hw
->mac_type
== e1000_igb
) {
679 data
[i
] = (E1000_READ_REG(hw
, I210_EERD
) >>
680 E1000_EEPROM_RW_REG_DATA
);
682 data
[i
] = (E1000_READ_REG(hw
, EERD
) >>
683 E1000_EEPROM_RW_REG_DATA
);
691 void e1000_release_eeprom(struct e1000_hw
*hw
)
697 eecd
= E1000_READ_REG(hw
, EECD
);
699 if (hw
->eeprom
.type
== e1000_eeprom_spi
) {
700 eecd
|= E1000_EECD_CS
; /* Pull CS high */
701 eecd
&= ~E1000_EECD_SK
; /* Lower SCK */
703 E1000_WRITE_REG(hw
, EECD
, eecd
);
705 udelay(hw
->eeprom
.delay_usec
);
706 } else if (hw
->eeprom
.type
== e1000_eeprom_microwire
) {
709 /* CS on Microwire is active-high */
710 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
712 E1000_WRITE_REG(hw
, EECD
, eecd
);
714 /* Rising edge of clock */
715 eecd
|= E1000_EECD_SK
;
716 E1000_WRITE_REG(hw
, EECD
, eecd
);
717 E1000_WRITE_FLUSH(hw
);
718 udelay(hw
->eeprom
.delay_usec
);
720 /* Falling edge of clock */
721 eecd
&= ~E1000_EECD_SK
;
722 E1000_WRITE_REG(hw
, EECD
, eecd
);
723 E1000_WRITE_FLUSH(hw
);
724 udelay(hw
->eeprom
.delay_usec
);
727 /* Stop requesting EEPROM access */
728 if (hw
->mac_type
> e1000_82544
) {
729 eecd
&= ~E1000_EECD_REQ
;
730 E1000_WRITE_REG(hw
, EECD
, eecd
);
733 /******************************************************************************
734 * Reads a 16 bit word from the EEPROM.
736 * hw - Struct containing variables accessed by shared code
737 *****************************************************************************/
739 e1000_spi_eeprom_ready(struct e1000_hw
*hw
)
741 uint16_t retry_count
= 0;
742 uint8_t spi_stat_reg
;
746 /* Read "Status Register" repeatedly until the LSB is cleared. The
747 * EEPROM will signal that the command has been completed by clearing
748 * bit 0 of the internal status register. If it's not cleared within
749 * 5 milliseconds, then error out.
753 e1000_shift_out_ee_bits(hw
, EEPROM_RDSR_OPCODE_SPI
,
754 hw
->eeprom
.opcode_bits
);
755 spi_stat_reg
= (uint8_t)e1000_shift_in_ee_bits(hw
, 8);
756 if (!(spi_stat_reg
& EEPROM_STATUS_RDY_SPI
))
762 e1000_standby_eeprom(hw
);
763 } while (retry_count
< EEPROM_MAX_RETRY_SPI
);
765 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
766 * only 0-5mSec on 5V devices)
768 if (retry_count
>= EEPROM_MAX_RETRY_SPI
) {
769 DEBUGOUT("SPI EEPROM Status error\n");
770 return -E1000_ERR_EEPROM
;
773 return E1000_SUCCESS
;
776 /******************************************************************************
777 * Reads a 16 bit word from the EEPROM.
779 * hw - Struct containing variables accessed by shared code
780 * offset - offset of word in the EEPROM to read
781 * data - word read from the EEPROM
782 *****************************************************************************/
784 e1000_read_eeprom(struct e1000_hw
*hw
, uint16_t offset
,
785 uint16_t words
, uint16_t *data
)
787 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
792 /* If eeprom is not yet detected, do so now */
793 if (eeprom
->word_size
== 0)
794 e1000_init_eeprom_params(hw
);
796 /* A check for invalid values: offset too large, too many words,
797 * and not enough words.
799 if ((offset
>= eeprom
->word_size
) ||
800 (words
> eeprom
->word_size
- offset
) ||
802 DEBUGOUT("\"words\" parameter out of bounds."
803 "Words = %d, size = %d\n", offset
, eeprom
->word_size
);
804 return -E1000_ERR_EEPROM
;
807 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
808 * directly. In this case, we need to acquire the EEPROM so that
809 * FW or other port software does not interrupt.
811 if (e1000_is_onboard_nvm_eeprom(hw
) == true &&
812 hw
->eeprom
.use_eerd
== false) {
814 /* Prepare the EEPROM for bit-bang reading */
815 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
816 return -E1000_ERR_EEPROM
;
819 /* Eerd register EEPROM access requires no eeprom aquire/release */
820 if (eeprom
->use_eerd
== true)
821 return e1000_read_eeprom_eerd(hw
, offset
, words
, data
);
823 /* ich8lan does not support currently. if needed, please
824 * add corresponding code and functions.
827 /* ICH EEPROM access is done via the ICH flash controller */
828 if (eeprom
->type
== e1000_eeprom_ich8
)
829 return e1000_read_eeprom_ich8(hw
, offset
, words
, data
);
831 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
832 * acquired the EEPROM at this point, so any returns should relase it */
833 if (eeprom
->type
== e1000_eeprom_spi
) {
835 uint8_t read_opcode
= EEPROM_READ_OPCODE_SPI
;
837 if (e1000_spi_eeprom_ready(hw
)) {
838 e1000_release_eeprom(hw
);
839 return -E1000_ERR_EEPROM
;
842 e1000_standby_eeprom(hw
);
844 /* Some SPI eeproms use the 8th address bit embedded in
846 if ((eeprom
->address_bits
== 8) && (offset
>= 128))
847 read_opcode
|= EEPROM_A8_OPCODE_SPI
;
849 /* Send the READ command (opcode + addr) */
850 e1000_shift_out_ee_bits(hw
, read_opcode
, eeprom
->opcode_bits
);
851 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
*2),
852 eeprom
->address_bits
);
854 /* Read the data. The address of the eeprom internally
855 * increments with each byte (spi) being read, saving on the
856 * overhead of eeprom setup and tear-down. The address
857 * counter will roll over if reading beyond the size of
858 * the eeprom, thus allowing the entire memory to be read
859 * starting from any offset. */
860 for (i
= 0; i
< words
; i
++) {
861 word_in
= e1000_shift_in_ee_bits(hw
, 16);
862 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
864 } else if (eeprom
->type
== e1000_eeprom_microwire
) {
865 for (i
= 0; i
< words
; i
++) {
866 /* Send the READ command (opcode + addr) */
867 e1000_shift_out_ee_bits(hw
,
868 EEPROM_READ_OPCODE_MICROWIRE
,
869 eeprom
->opcode_bits
);
870 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ i
),
871 eeprom
->address_bits
);
873 /* Read the data. For microwire, each word requires
874 * the overhead of eeprom setup and tear-down. */
875 data
[i
] = e1000_shift_in_ee_bits(hw
, 16);
876 e1000_standby_eeprom(hw
);
880 /* End this read operation */
881 e1000_release_eeprom(hw
);
883 return E1000_SUCCESS
;
886 /******************************************************************************
887 * Verifies that the EEPROM has a valid checksum
889 * hw - Struct containing variables accessed by shared code
891 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
892 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
894 *****************************************************************************/
895 static int e1000_validate_eeprom_checksum(struct e1000_hw
*hw
)
897 uint16_t i
, checksum
, checksum_reg
, *buf
;
901 /* Allocate a temporary buffer */
902 buf
= malloc(sizeof(buf
[0]) * (EEPROM_CHECKSUM_REG
+ 1));
904 E1000_ERR(hw
->nic
, "Unable to allocate EEPROM buffer!\n");
905 return -E1000_ERR_EEPROM
;
908 /* Read the EEPROM */
909 if (e1000_read_eeprom(hw
, 0, EEPROM_CHECKSUM_REG
+ 1, buf
) < 0) {
910 E1000_ERR(hw
->nic
, "Unable to read EEPROM!\n");
911 return -E1000_ERR_EEPROM
;
914 /* Compute the checksum */
916 for (i
= 0; i
< EEPROM_CHECKSUM_REG
; i
++)
918 checksum
= ((uint16_t)EEPROM_SUM
) - checksum
;
919 checksum_reg
= buf
[i
];
922 if (checksum
== checksum_reg
)
925 /* Hrm, verification failed, print an error */
926 E1000_ERR(hw
->nic
, "EEPROM checksum is incorrect!\n");
927 E1000_ERR(hw
->nic
, " ...register was 0x%04hx, calculated 0x%04hx\n",
928 checksum_reg
, checksum
);
930 return -E1000_ERR_EEPROM
;
932 #endif /* CONFIG_E1000_NO_NVM */
934 /*****************************************************************************
935 * Set PHY to class A mode
936 * Assumes the following operations will follow to enable the new class mode.
937 * 1. Do a PHY soft reset
938 * 2. Restart auto-negotiation or force link.
940 * hw - Struct containing variables accessed by shared code
941 ****************************************************************************/
943 e1000_set_phy_mode(struct e1000_hw
*hw
)
945 #ifndef CONFIG_E1000_NO_NVM
947 uint16_t eeprom_data
;
951 if ((hw
->mac_type
== e1000_82545_rev_3
) &&
952 (hw
->media_type
== e1000_media_type_copper
)) {
953 ret_val
= e1000_read_eeprom(hw
, EEPROM_PHY_CLASS_WORD
,
958 if ((eeprom_data
!= EEPROM_RESERVED_WORD
) &&
959 (eeprom_data
& EEPROM_PHY_CLASS_A
)) {
960 ret_val
= e1000_write_phy_reg(hw
,
961 M88E1000_PHY_PAGE_SELECT
, 0x000B);
964 ret_val
= e1000_write_phy_reg(hw
,
965 M88E1000_PHY_GEN_CONTROL
, 0x8104);
969 hw
->phy_reset_disable
= false;
973 return E1000_SUCCESS
;
976 #ifndef CONFIG_E1000_NO_NVM
977 /***************************************************************************
979 * Obtaining software semaphore bit (SMBI) before resetting PHY.
981 * hw: Struct containing variables accessed by shared code
983 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
984 * E1000_SUCCESS at any other case.
986 ***************************************************************************/
988 e1000_get_software_semaphore(struct e1000_hw
*hw
)
990 int32_t timeout
= hw
->eeprom
.word_size
+ 1;
995 swsm
= E1000_READ_REG(hw
, SWSM
);
996 swsm
&= ~E1000_SWSM_SMBI
;
997 E1000_WRITE_REG(hw
, SWSM
, swsm
);
999 if (hw
->mac_type
!= e1000_80003es2lan
)
1000 return E1000_SUCCESS
;
1003 swsm
= E1000_READ_REG(hw
, SWSM
);
1004 /* If SMBI bit cleared, it is now set and we hold
1006 if (!(swsm
& E1000_SWSM_SMBI
))
1013 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1014 return -E1000_ERR_RESET
;
1017 return E1000_SUCCESS
;
1021 /***************************************************************************
1022 * This function clears HW semaphore bits.
1024 * hw: Struct containing variables accessed by shared code
1028 ***************************************************************************/
1030 e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
)
1032 #ifndef CONFIG_E1000_NO_NVM
1037 if (!hw
->eeprom_semaphore_present
)
1040 swsm
= E1000_READ_REG(hw
, SWSM
);
1041 if (hw
->mac_type
== e1000_80003es2lan
) {
1042 /* Release both semaphores. */
1043 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1045 swsm
&= ~(E1000_SWSM_SWESMBI
);
1046 E1000_WRITE_REG(hw
, SWSM
, swsm
);
1050 /***************************************************************************
1052 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1053 * adapter or Eeprom access.
1055 * hw: Struct containing variables accessed by shared code
1057 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1058 * E1000_SUCCESS at any other case.
1060 ***************************************************************************/
1062 e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
)
1064 #ifndef CONFIG_E1000_NO_NVM
1070 if (!hw
->eeprom_semaphore_present
)
1071 return E1000_SUCCESS
;
1073 if (hw
->mac_type
== e1000_80003es2lan
) {
1074 /* Get the SW semaphore. */
1075 if (e1000_get_software_semaphore(hw
) != E1000_SUCCESS
)
1076 return -E1000_ERR_EEPROM
;
1079 /* Get the FW semaphore. */
1080 timeout
= hw
->eeprom
.word_size
+ 1;
1082 swsm
= E1000_READ_REG(hw
, SWSM
);
1083 swsm
|= E1000_SWSM_SWESMBI
;
1084 E1000_WRITE_REG(hw
, SWSM
, swsm
);
1085 /* if we managed to set the bit we got the semaphore. */
1086 swsm
= E1000_READ_REG(hw
, SWSM
);
1087 if (swsm
& E1000_SWSM_SWESMBI
)
1095 /* Release semaphores */
1096 e1000_put_hw_eeprom_semaphore(hw
);
1097 DEBUGOUT("Driver can't access the Eeprom - "
1098 "SWESMBI bit is set.\n");
1099 return -E1000_ERR_EEPROM
;
1102 return E1000_SUCCESS
;
1106 e1000_swfw_sync_acquire(struct e1000_hw
*hw
, uint16_t mask
)
1108 uint32_t swfw_sync
= 0;
1109 uint32_t swmask
= mask
;
1110 uint32_t fwmask
= mask
<< 16;
1111 int32_t timeout
= 200;
1115 if (e1000_get_hw_eeprom_semaphore(hw
))
1116 return -E1000_ERR_SWFW_SYNC
;
1118 if (hw
->mac_type
== e1000_igb
)
1119 swfw_sync
= E1000_READ_REG(hw
, I210_SW_FW_SYNC
);
1121 swfw_sync
= E1000_READ_REG(hw
, SW_FW_SYNC
);
1122 if (!(swfw_sync
& (fwmask
| swmask
)))
1125 /* firmware currently using resource (fwmask) */
1126 /* or other software thread currently using resource (swmask) */
1127 e1000_put_hw_eeprom_semaphore(hw
);
1133 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1134 return -E1000_ERR_SWFW_SYNC
;
1137 swfw_sync
|= swmask
;
1138 E1000_WRITE_REG(hw
, SW_FW_SYNC
, swfw_sync
);
1140 e1000_put_hw_eeprom_semaphore(hw
);
1141 return E1000_SUCCESS
;
1144 static bool e1000_is_second_port(struct e1000_hw
*hw
)
1146 switch (hw
->mac_type
) {
1147 case e1000_80003es2lan
:
1150 if (E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_FUNC_1
)
1158 #ifndef CONFIG_E1000_NO_NVM
1159 /******************************************************************************
1160 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1161 * second function of dual function devices
1163 * nic - Struct containing variables accessed by shared code
1164 *****************************************************************************/
1166 e1000_read_mac_addr(struct eth_device
*nic
)
1168 struct e1000_hw
*hw
= nic
->priv
;
1170 uint16_t eeprom_data
;
1171 uint32_t reg_data
= 0;
1176 for (i
= 0; i
< NODE_ADDRESS_SIZE
; i
+= 2) {
1178 if (hw
->mac_type
== e1000_igb
) {
1179 /* i210 preloads MAC address into RAL/RAH registers */
1181 reg_data
= E1000_READ_REG_ARRAY(hw
, RA
, 0);
1182 else if (offset
== 1)
1184 else if (offset
== 2)
1185 reg_data
= E1000_READ_REG_ARRAY(hw
, RA
, 1);
1186 eeprom_data
= reg_data
& 0xffff;
1187 } else if (e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
1188 DEBUGOUT("EEPROM Read Error\n");
1189 return -E1000_ERR_EEPROM
;
1191 nic
->enetaddr
[i
] = eeprom_data
& 0xff;
1192 nic
->enetaddr
[i
+ 1] = (eeprom_data
>> 8) & 0xff;
1195 /* Invert the last bit if this is the second device */
1196 if (e1000_is_second_port(hw
))
1197 nic
->enetaddr
[5] ^= 1;
1199 #ifdef CONFIG_E1000_FALLBACK_MAC
1200 if (!is_valid_ether_addr(nic
->enetaddr
)) {
1201 unsigned char fb_mac
[NODE_ADDRESS_SIZE
] = CONFIG_E1000_FALLBACK_MAC
;
1203 memcpy (nic
->enetaddr
, fb_mac
, NODE_ADDRESS_SIZE
);
1210 /******************************************************************************
1211 * Initializes receive address filters.
1213 * hw - Struct containing variables accessed by shared code
1215 * Places the MAC address in receive address register 0 and clears the rest
1216 * of the receive addresss registers. Clears the multicast table. Assumes
1217 * the receiver is in reset when the routine is called.
1218 *****************************************************************************/
1220 e1000_init_rx_addrs(struct eth_device
*nic
)
1222 struct e1000_hw
*hw
= nic
->priv
;
1229 /* Setup the receive address. */
1230 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1231 addr_low
= (nic
->enetaddr
[0] |
1232 (nic
->enetaddr
[1] << 8) |
1233 (nic
->enetaddr
[2] << 16) | (nic
->enetaddr
[3] << 24));
1235 addr_high
= (nic
->enetaddr
[4] | (nic
->enetaddr
[5] << 8) | E1000_RAH_AV
);
1237 E1000_WRITE_REG_ARRAY(hw
, RA
, 0, addr_low
);
1238 E1000_WRITE_REG_ARRAY(hw
, RA
, 1, addr_high
);
1240 /* Zero out the other 15 receive addresses. */
1241 DEBUGOUT("Clearing RAR[1-15]\n");
1242 for (i
= 1; i
< E1000_RAR_ENTRIES
; i
++) {
1243 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
1244 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
1248 /******************************************************************************
1249 * Clears the VLAN filer table
1251 * hw - Struct containing variables accessed by shared code
1252 *****************************************************************************/
1254 e1000_clear_vfta(struct e1000_hw
*hw
)
1258 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++)
1259 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, 0);
1262 /******************************************************************************
1263 * Set the mac type member in the hw struct.
1265 * hw - Struct containing variables accessed by shared code
1266 *****************************************************************************/
1268 e1000_set_mac_type(struct e1000_hw
*hw
)
1272 switch (hw
->device_id
) {
1273 case E1000_DEV_ID_82542
:
1274 switch (hw
->revision_id
) {
1275 case E1000_82542_2_0_REV_ID
:
1276 hw
->mac_type
= e1000_82542_rev2_0
;
1278 case E1000_82542_2_1_REV_ID
:
1279 hw
->mac_type
= e1000_82542_rev2_1
;
1282 /* Invalid 82542 revision ID */
1283 return -E1000_ERR_MAC_TYPE
;
1286 case E1000_DEV_ID_82543GC_FIBER
:
1287 case E1000_DEV_ID_82543GC_COPPER
:
1288 hw
->mac_type
= e1000_82543
;
1290 case E1000_DEV_ID_82544EI_COPPER
:
1291 case E1000_DEV_ID_82544EI_FIBER
:
1292 case E1000_DEV_ID_82544GC_COPPER
:
1293 case E1000_DEV_ID_82544GC_LOM
:
1294 hw
->mac_type
= e1000_82544
;
1296 case E1000_DEV_ID_82540EM
:
1297 case E1000_DEV_ID_82540EM_LOM
:
1298 case E1000_DEV_ID_82540EP
:
1299 case E1000_DEV_ID_82540EP_LOM
:
1300 case E1000_DEV_ID_82540EP_LP
:
1301 hw
->mac_type
= e1000_82540
;
1303 case E1000_DEV_ID_82545EM_COPPER
:
1304 case E1000_DEV_ID_82545EM_FIBER
:
1305 hw
->mac_type
= e1000_82545
;
1307 case E1000_DEV_ID_82545GM_COPPER
:
1308 case E1000_DEV_ID_82545GM_FIBER
:
1309 case E1000_DEV_ID_82545GM_SERDES
:
1310 hw
->mac_type
= e1000_82545_rev_3
;
1312 case E1000_DEV_ID_82546EB_COPPER
:
1313 case E1000_DEV_ID_82546EB_FIBER
:
1314 case E1000_DEV_ID_82546EB_QUAD_COPPER
:
1315 hw
->mac_type
= e1000_82546
;
1317 case E1000_DEV_ID_82546GB_COPPER
:
1318 case E1000_DEV_ID_82546GB_FIBER
:
1319 case E1000_DEV_ID_82546GB_SERDES
:
1320 case E1000_DEV_ID_82546GB_PCIE
:
1321 case E1000_DEV_ID_82546GB_QUAD_COPPER
:
1322 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3
:
1323 hw
->mac_type
= e1000_82546_rev_3
;
1325 case E1000_DEV_ID_82541EI
:
1326 case E1000_DEV_ID_82541EI_MOBILE
:
1327 case E1000_DEV_ID_82541ER_LOM
:
1328 hw
->mac_type
= e1000_82541
;
1330 case E1000_DEV_ID_82541ER
:
1331 case E1000_DEV_ID_82541GI
:
1332 case E1000_DEV_ID_82541GI_LF
:
1333 case E1000_DEV_ID_82541GI_MOBILE
:
1334 hw
->mac_type
= e1000_82541_rev_2
;
1336 case E1000_DEV_ID_82547EI
:
1337 case E1000_DEV_ID_82547EI_MOBILE
:
1338 hw
->mac_type
= e1000_82547
;
1340 case E1000_DEV_ID_82547GI
:
1341 hw
->mac_type
= e1000_82547_rev_2
;
1343 case E1000_DEV_ID_82571EB_COPPER
:
1344 case E1000_DEV_ID_82571EB_FIBER
:
1345 case E1000_DEV_ID_82571EB_SERDES
:
1346 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
1347 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
1348 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
1349 case E1000_DEV_ID_82571PT_QUAD_COPPER
:
1350 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
1351 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE
:
1352 hw
->mac_type
= e1000_82571
;
1354 case E1000_DEV_ID_82572EI_COPPER
:
1355 case E1000_DEV_ID_82572EI_FIBER
:
1356 case E1000_DEV_ID_82572EI_SERDES
:
1357 case E1000_DEV_ID_82572EI
:
1358 hw
->mac_type
= e1000_82572
;
1360 case E1000_DEV_ID_82573E
:
1361 case E1000_DEV_ID_82573E_IAMT
:
1362 case E1000_DEV_ID_82573L
:
1363 hw
->mac_type
= e1000_82573
;
1365 case E1000_DEV_ID_82574L
:
1366 hw
->mac_type
= e1000_82574
;
1368 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT
:
1369 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT
:
1370 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT
:
1371 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT
:
1372 hw
->mac_type
= e1000_80003es2lan
;
1374 case E1000_DEV_ID_ICH8_IGP_M_AMT
:
1375 case E1000_DEV_ID_ICH8_IGP_AMT
:
1376 case E1000_DEV_ID_ICH8_IGP_C
:
1377 case E1000_DEV_ID_ICH8_IFE
:
1378 case E1000_DEV_ID_ICH8_IFE_GT
:
1379 case E1000_DEV_ID_ICH8_IFE_G
:
1380 case E1000_DEV_ID_ICH8_IGP_M
:
1381 hw
->mac_type
= e1000_ich8lan
;
1383 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED
:
1384 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED
:
1385 case PCI_DEVICE_ID_INTEL_I210_COPPER
:
1386 case PCI_DEVICE_ID_INTEL_I211_COPPER
:
1387 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS
:
1388 case PCI_DEVICE_ID_INTEL_I210_SERDES
:
1389 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS
:
1390 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX
:
1391 hw
->mac_type
= e1000_igb
;
1394 /* Should never have loaded on this device */
1395 return -E1000_ERR_MAC_TYPE
;
1397 return E1000_SUCCESS
;
1400 /******************************************************************************
1401 * Reset the transmit and receive units; mask and clear all interrupts.
1403 * hw - Struct containing variables accessed by shared code
1404 *****************************************************************************/
1406 e1000_reset_hw(struct e1000_hw
*hw
)
1416 /* get the correct pba value for both PCI and PCIe*/
1417 if (hw
->mac_type
< e1000_82571
)
1418 pba
= E1000_DEFAULT_PCI_PBA
;
1420 pba
= E1000_DEFAULT_PCIE_PBA
;
1422 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1423 if (hw
->mac_type
== e1000_82542_rev2_0
) {
1424 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1425 pci_write_config_word(hw
->pdev
, PCI_COMMAND
,
1426 hw
->pci_cmd_word
& ~PCI_COMMAND_INVALIDATE
);
1429 /* Clear interrupt mask to stop board from generating interrupts */
1430 DEBUGOUT("Masking off all interrupts\n");
1431 if (hw
->mac_type
== e1000_igb
)
1432 E1000_WRITE_REG(hw
, I210_IAM
, 0);
1433 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
1435 /* Disable the Transmit and Receive units. Then delay to allow
1436 * any pending transactions to complete before we hit the MAC with
1439 E1000_WRITE_REG(hw
, RCTL
, 0);
1440 E1000_WRITE_REG(hw
, TCTL
, E1000_TCTL_PSP
);
1441 E1000_WRITE_FLUSH(hw
);
1443 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1444 hw
->tbi_compatibility_on
= false;
1446 /* Delay to allow any outstanding PCI transactions to complete before
1447 * resetting the device
1451 /* Issue a global reset to the MAC. This will reset the chip's
1452 * transmit, receive, DMA, and link units. It will not effect
1453 * the current PCI configuration. The global reset bit is self-
1454 * clearing, and should clear within a microsecond.
1456 DEBUGOUT("Issuing a global reset to MAC\n");
1457 ctrl
= E1000_READ_REG(hw
, CTRL
);
1459 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
1461 /* Force a reload from the EEPROM if necessary */
1462 if (hw
->mac_type
== e1000_igb
) {
1464 reg
= E1000_READ_REG(hw
, STATUS
);
1465 if (reg
& E1000_STATUS_PF_RST_DONE
)
1466 DEBUGOUT("PF OK\n");
1467 reg
= E1000_READ_REG(hw
, I210_EECD
);
1468 if (reg
& E1000_EECD_AUTO_RD
)
1469 DEBUGOUT("EEC OK\n");
1470 } else if (hw
->mac_type
< e1000_82540
) {
1471 /* Wait for reset to complete */
1473 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
1474 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
1475 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
1476 E1000_WRITE_FLUSH(hw
);
1477 /* Wait for EEPROM reload */
1480 /* Wait for EEPROM reload (it happens automatically) */
1482 /* Dissable HW ARPs on ASF enabled adapters */
1483 manc
= E1000_READ_REG(hw
, MANC
);
1484 manc
&= ~(E1000_MANC_ARP_EN
);
1485 E1000_WRITE_REG(hw
, MANC
, manc
);
1488 /* Clear interrupt mask to stop board from generating interrupts */
1489 DEBUGOUT("Masking off all interrupts\n");
1490 if (hw
->mac_type
== e1000_igb
)
1491 E1000_WRITE_REG(hw
, I210_IAM
, 0);
1492 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
1494 /* Clear any pending interrupt events. */
1495 E1000_READ_REG(hw
, ICR
);
1497 /* If MWI was previously enabled, reenable it. */
1498 if (hw
->mac_type
== e1000_82542_rev2_0
) {
1499 pci_write_config_word(hw
->pdev
, PCI_COMMAND
, hw
->pci_cmd_word
);
1501 if (hw
->mac_type
!= e1000_igb
)
1502 E1000_WRITE_REG(hw
, PBA
, pba
);
1505 /******************************************************************************
1507 * Initialize a number of hardware-dependent bits
1509 * hw: Struct containing variables accessed by shared code
1511 * This function contains hardware limitation workarounds for PCI-E adapters
1513 *****************************************************************************/
1515 e1000_initialize_hardware_bits(struct e1000_hw
*hw
)
1517 if ((hw
->mac_type
>= e1000_82571
) &&
1518 (!hw
->initialize_hw_bits_disable
)) {
1519 /* Settings common to all PCI-express silicon */
1520 uint32_t reg_ctrl
, reg_ctrl_ext
;
1521 uint32_t reg_tarc0
, reg_tarc1
;
1523 uint32_t reg_txdctl
, reg_txdctl1
;
1525 /* link autonegotiation/sync workarounds */
1526 reg_tarc0
= E1000_READ_REG(hw
, TARC0
);
1527 reg_tarc0
&= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1529 /* Enable not-done TX descriptor counting */
1530 reg_txdctl
= E1000_READ_REG(hw
, TXDCTL
);
1531 reg_txdctl
|= E1000_TXDCTL_COUNT_DESC
;
1532 E1000_WRITE_REG(hw
, TXDCTL
, reg_txdctl
);
1534 reg_txdctl1
= E1000_READ_REG(hw
, TXDCTL1
);
1535 reg_txdctl1
|= E1000_TXDCTL_COUNT_DESC
;
1536 E1000_WRITE_REG(hw
, TXDCTL1
, reg_txdctl1
);
1539 if (hw
->mac_type
== e1000_igb
)
1542 switch (hw
->mac_type
) {
1545 /* Clear PHY TX compatible mode bits */
1546 reg_tarc1
= E1000_READ_REG(hw
, TARC1
);
1547 reg_tarc1
&= ~((1 << 30)|(1 << 29));
1549 /* link autonegotiation/sync workarounds */
1550 reg_tarc0
|= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1552 /* TX ring control fixes */
1553 reg_tarc1
|= ((1 << 26)|(1 << 25)|(1 << 24));
1555 /* Multiple read bit is reversed polarity */
1556 reg_tctl
= E1000_READ_REG(hw
, TCTL
);
1557 if (reg_tctl
& E1000_TCTL_MULR
)
1558 reg_tarc1
&= ~(1 << 28);
1560 reg_tarc1
|= (1 << 28);
1562 E1000_WRITE_REG(hw
, TARC1
, reg_tarc1
);
1566 reg_ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
1567 reg_ctrl_ext
&= ~(1 << 23);
1568 reg_ctrl_ext
|= (1 << 22);
1570 /* TX byte count fix */
1571 reg_ctrl
= E1000_READ_REG(hw
, CTRL
);
1572 reg_ctrl
&= ~(1 << 29);
1574 E1000_WRITE_REG(hw
, CTRL_EXT
, reg_ctrl_ext
);
1575 E1000_WRITE_REG(hw
, CTRL
, reg_ctrl
);
1577 case e1000_80003es2lan
:
1578 /* improve small packet performace for fiber/serdes */
1579 if ((hw
->media_type
== e1000_media_type_fiber
)
1580 || (hw
->media_type
==
1581 e1000_media_type_internal_serdes
)) {
1582 reg_tarc0
&= ~(1 << 20);
1585 /* Multiple read bit is reversed polarity */
1586 reg_tctl
= E1000_READ_REG(hw
, TCTL
);
1587 reg_tarc1
= E1000_READ_REG(hw
, TARC1
);
1588 if (reg_tctl
& E1000_TCTL_MULR
)
1589 reg_tarc1
&= ~(1 << 28);
1591 reg_tarc1
|= (1 << 28);
1593 E1000_WRITE_REG(hw
, TARC1
, reg_tarc1
);
1596 /* Reduce concurrent DMA requests to 3 from 4 */
1597 if ((hw
->revision_id
< 3) ||
1598 ((hw
->device_id
!= E1000_DEV_ID_ICH8_IGP_M_AMT
) &&
1599 (hw
->device_id
!= E1000_DEV_ID_ICH8_IGP_M
)))
1600 reg_tarc0
|= ((1 << 29)|(1 << 28));
1602 reg_ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
1603 reg_ctrl_ext
|= (1 << 22);
1604 E1000_WRITE_REG(hw
, CTRL_EXT
, reg_ctrl_ext
);
1606 /* workaround TX hang with TSO=on */
1607 reg_tarc0
|= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1609 /* Multiple read bit is reversed polarity */
1610 reg_tctl
= E1000_READ_REG(hw
, TCTL
);
1611 reg_tarc1
= E1000_READ_REG(hw
, TARC1
);
1612 if (reg_tctl
& E1000_TCTL_MULR
)
1613 reg_tarc1
&= ~(1 << 28);
1615 reg_tarc1
|= (1 << 28);
1617 /* workaround TX hang with TSO=on */
1618 reg_tarc1
|= ((1 << 30)|(1 << 26)|(1 << 24));
1620 E1000_WRITE_REG(hw
, TARC1
, reg_tarc1
);
1626 E1000_WRITE_REG(hw
, TARC0
, reg_tarc0
);
1630 /******************************************************************************
1631 * Performs basic configuration of the adapter.
1633 * hw - Struct containing variables accessed by shared code
1635 * Assumes that the controller has previously been reset and is in a
1636 * post-reset uninitialized state. Initializes the receive address registers,
1637 * multicast table, and VLAN filter table. Calls routines to setup link
1638 * configuration and flow control settings. Clears all on-chip counters. Leaves
1639 * the transmit and receive units disabled and uninitialized.
1640 *****************************************************************************/
1642 e1000_init_hw(struct eth_device
*nic
)
1644 struct e1000_hw
*hw
= nic
->priv
;
1648 uint16_t pcix_cmd_word
;
1649 uint16_t pcix_stat_hi_word
;
1651 uint16_t stat_mmrbc
;
1656 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1657 if ((hw
->mac_type
== e1000_ich8lan
) &&
1658 ((hw
->revision_id
< 3) ||
1659 ((hw
->device_id
!= E1000_DEV_ID_ICH8_IGP_M_AMT
) &&
1660 (hw
->device_id
!= E1000_DEV_ID_ICH8_IGP_M
)))) {
1661 reg_data
= E1000_READ_REG(hw
, STATUS
);
1662 reg_data
&= ~0x80000000;
1663 E1000_WRITE_REG(hw
, STATUS
, reg_data
);
1665 /* Do not need initialize Identification LED */
1667 /* Set the media type and TBI compatibility */
1668 e1000_set_media_type(hw
);
1670 /* Must be called after e1000_set_media_type
1671 * because media_type is used */
1672 e1000_initialize_hardware_bits(hw
);
1674 /* Disabling VLAN filtering. */
1675 DEBUGOUT("Initializing the IEEE VLAN\n");
1676 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1677 if (hw
->mac_type
!= e1000_ich8lan
) {
1678 if (hw
->mac_type
< e1000_82545_rev_3
)
1679 E1000_WRITE_REG(hw
, VET
, 0);
1680 e1000_clear_vfta(hw
);
1683 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1684 if (hw
->mac_type
== e1000_82542_rev2_0
) {
1685 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1686 pci_write_config_word(hw
->pdev
, PCI_COMMAND
,
1688 pci_cmd_word
& ~PCI_COMMAND_INVALIDATE
);
1689 E1000_WRITE_REG(hw
, RCTL
, E1000_RCTL_RST
);
1690 E1000_WRITE_FLUSH(hw
);
1694 /* Setup the receive address. This involves initializing all of the Receive
1695 * Address Registers (RARs 0 - 15).
1697 e1000_init_rx_addrs(nic
);
1699 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1700 if (hw
->mac_type
== e1000_82542_rev2_0
) {
1701 E1000_WRITE_REG(hw
, RCTL
, 0);
1702 E1000_WRITE_FLUSH(hw
);
1704 pci_write_config_word(hw
->pdev
, PCI_COMMAND
, hw
->pci_cmd_word
);
1707 /* Zero out the Multicast HASH table */
1708 DEBUGOUT("Zeroing the MTA\n");
1709 mta_size
= E1000_MC_TBL_SIZE
;
1710 if (hw
->mac_type
== e1000_ich8lan
)
1711 mta_size
= E1000_MC_TBL_SIZE_ICH8LAN
;
1712 for (i
= 0; i
< mta_size
; i
++) {
1713 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
1714 /* use write flush to prevent Memory Write Block (MWB) from
1715 * occuring when accessing our register space */
1716 E1000_WRITE_FLUSH(hw
);
1719 /* Set the PCI priority bit correctly in the CTRL register. This
1720 * determines if the adapter gives priority to receives, or if it
1721 * gives equal priority to transmits and receives. Valid only on
1722 * 82542 and 82543 silicon.
1724 if (hw
->dma_fairness
&& hw
->mac_type
<= e1000_82543
) {
1725 ctrl
= E1000_READ_REG(hw
, CTRL
);
1726 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PRIOR
);
1729 switch (hw
->mac_type
) {
1730 case e1000_82545_rev_3
:
1731 case e1000_82546_rev_3
:
1735 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1736 if (hw
->bus_type
== e1000_bus_type_pcix
) {
1737 pci_read_config_word(hw
->pdev
, PCIX_COMMAND_REGISTER
,
1739 pci_read_config_word(hw
->pdev
, PCIX_STATUS_REGISTER_HI
,
1740 &pcix_stat_hi_word
);
1742 (pcix_cmd_word
& PCIX_COMMAND_MMRBC_MASK
) >>
1743 PCIX_COMMAND_MMRBC_SHIFT
;
1745 (pcix_stat_hi_word
& PCIX_STATUS_HI_MMRBC_MASK
) >>
1746 PCIX_STATUS_HI_MMRBC_SHIFT
;
1747 if (stat_mmrbc
== PCIX_STATUS_HI_MMRBC_4K
)
1748 stat_mmrbc
= PCIX_STATUS_HI_MMRBC_2K
;
1749 if (cmd_mmrbc
> stat_mmrbc
) {
1750 pcix_cmd_word
&= ~PCIX_COMMAND_MMRBC_MASK
;
1751 pcix_cmd_word
|= stat_mmrbc
<< PCIX_COMMAND_MMRBC_SHIFT
;
1752 pci_write_config_word(hw
->pdev
, PCIX_COMMAND_REGISTER
,
1759 /* More time needed for PHY to initialize */
1760 if (hw
->mac_type
== e1000_ich8lan
)
1762 if (hw
->mac_type
== e1000_igb
)
1765 /* Call a subroutine to configure the link and setup flow control. */
1766 ret_val
= e1000_setup_link(nic
);
1768 /* Set the transmit descriptor write-back policy */
1769 if (hw
->mac_type
> e1000_82544
) {
1770 ctrl
= E1000_READ_REG(hw
, TXDCTL
);
1772 (ctrl
& ~E1000_TXDCTL_WTHRESH
) |
1773 E1000_TXDCTL_FULL_TX_DESC_WB
;
1774 E1000_WRITE_REG(hw
, TXDCTL
, ctrl
);
1777 /* Set the receive descriptor write back policy */
1778 if (hw
->mac_type
>= e1000_82571
) {
1779 ctrl
= E1000_READ_REG(hw
, RXDCTL
);
1781 (ctrl
& ~E1000_RXDCTL_WTHRESH
) |
1782 E1000_RXDCTL_FULL_RX_DESC_WB
;
1783 E1000_WRITE_REG(hw
, RXDCTL
, ctrl
);
1786 switch (hw
->mac_type
) {
1789 case e1000_80003es2lan
:
1790 /* Enable retransmit on late collisions */
1791 reg_data
= E1000_READ_REG(hw
, TCTL
);
1792 reg_data
|= E1000_TCTL_RTLC
;
1793 E1000_WRITE_REG(hw
, TCTL
, reg_data
);
1795 /* Configure Gigabit Carry Extend Padding */
1796 reg_data
= E1000_READ_REG(hw
, TCTL_EXT
);
1797 reg_data
&= ~E1000_TCTL_EXT_GCEX_MASK
;
1798 reg_data
|= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX
;
1799 E1000_WRITE_REG(hw
, TCTL_EXT
, reg_data
);
1801 /* Configure Transmit Inter-Packet Gap */
1802 reg_data
= E1000_READ_REG(hw
, TIPG
);
1803 reg_data
&= ~E1000_TIPG_IPGT_MASK
;
1804 reg_data
|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000
;
1805 E1000_WRITE_REG(hw
, TIPG
, reg_data
);
1807 reg_data
= E1000_READ_REG_ARRAY(hw
, FFLT
, 0x0001);
1808 reg_data
&= ~0x00100000;
1809 E1000_WRITE_REG_ARRAY(hw
, FFLT
, 0x0001, reg_data
);
1814 ctrl
= E1000_READ_REG(hw
, TXDCTL1
);
1815 ctrl
= (ctrl
& ~E1000_TXDCTL_WTHRESH
)
1816 | E1000_TXDCTL_FULL_TX_DESC_WB
;
1817 E1000_WRITE_REG(hw
, TXDCTL1
, ctrl
);
1821 reg_data
= E1000_READ_REG(hw
, GCR
);
1822 reg_data
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
1823 E1000_WRITE_REG(hw
, GCR
, reg_data
);
1829 /* Clear all of the statistics registers (clear on read). It is
1830 * important that we do this after we have tried to establish link
1831 * because the symbol error count will increment wildly if there
1834 e1000_clear_hw_cntrs(hw
);
1836 /* ICH8 No-snoop bits are opposite polarity.
1837 * Set to snoop by default after reset. */
1838 if (hw
->mac_type
== e1000_ich8lan
)
1839 e1000_set_pci_ex_no_snoop(hw
, PCI_EX_82566_SNOOP_ALL
);
1842 if (hw
->device_id
== E1000_DEV_ID_82546GB_QUAD_COPPER
||
1843 hw
->device_id
== E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3
) {
1844 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
1845 /* Relaxed ordering must be disabled to avoid a parity
1846 * error crash in a PCI slot. */
1847 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
1848 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
1854 /******************************************************************************
1855 * Configures flow control and link settings.
1857 * hw - Struct containing variables accessed by shared code
1859 * Determines which flow control settings to use. Calls the apropriate media-
1860 * specific link configuration function. Configures the flow control settings.
1861 * Assuming the adapter has a valid link partner, a valid link should be
1862 * established. Assumes the hardware has previously been reset and the
1863 * transmitter and receiver are not enabled.
1864 *****************************************************************************/
1866 e1000_setup_link(struct eth_device
*nic
)
1868 struct e1000_hw
*hw
= nic
->priv
;
1870 #ifndef CONFIG_E1000_NO_NVM
1872 uint16_t eeprom_data
;
1877 /* In the case of the phy reset being blocked, we already have a link.
1878 * We do not have to set it up again. */
1879 if (e1000_check_phy_reset_block(hw
))
1880 return E1000_SUCCESS
;
1882 #ifndef CONFIG_E1000_NO_NVM
1883 /* Read and store word 0x0F of the EEPROM. This word contains bits
1884 * that determine the hardware's default PAUSE (flow control) mode,
1885 * a bit that determines whether the HW defaults to enabling or
1886 * disabling auto-negotiation, and the direction of the
1887 * SW defined pins. If there is no SW over-ride of the flow
1888 * control setting, then the variable hw->fc will
1889 * be initialized based on a value in the EEPROM.
1891 if (e1000_read_eeprom(hw
, EEPROM_INIT_CONTROL2_REG
, 1,
1892 &eeprom_data
) < 0) {
1893 DEBUGOUT("EEPROM Read Error\n");
1894 return -E1000_ERR_EEPROM
;
1897 if (hw
->fc
== e1000_fc_default
) {
1898 switch (hw
->mac_type
) {
1903 hw
->fc
= e1000_fc_full
;
1906 #ifndef CONFIG_E1000_NO_NVM
1907 ret_val
= e1000_read_eeprom(hw
,
1908 EEPROM_INIT_CONTROL2_REG
, 1, &eeprom_data
);
1910 DEBUGOUT("EEPROM Read Error\n");
1911 return -E1000_ERR_EEPROM
;
1913 if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) == 0)
1914 hw
->fc
= e1000_fc_none
;
1915 else if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) ==
1916 EEPROM_WORD0F_ASM_DIR
)
1917 hw
->fc
= e1000_fc_tx_pause
;
1920 hw
->fc
= e1000_fc_full
;
1925 /* We want to save off the original Flow Control configuration just
1926 * in case we get disconnected and then reconnected into a different
1927 * hub or switch with different Flow Control capabilities.
1929 if (hw
->mac_type
== e1000_82542_rev2_0
)
1930 hw
->fc
&= (~e1000_fc_tx_pause
);
1932 if ((hw
->mac_type
< e1000_82543
) && (hw
->report_tx_early
== 1))
1933 hw
->fc
&= (~e1000_fc_rx_pause
);
1935 hw
->original_fc
= hw
->fc
;
1937 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw
->fc
);
1939 #ifndef CONFIG_E1000_NO_NVM
1940 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1941 * polarity value for the SW controlled pins, and setup the
1942 * Extended Device Control reg with that info.
1943 * This is needed because one of the SW controlled pins is used for
1944 * signal detection. So this should be done before e1000_setup_pcs_link()
1945 * or e1000_phy_setup() is called.
1947 if (hw
->mac_type
== e1000_82543
) {
1948 ctrl_ext
= ((eeprom_data
& EEPROM_WORD0F_SWPDIO_EXT
) <<
1950 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
1954 /* Call the necessary subroutine to configure the link. */
1955 ret_val
= (hw
->media_type
== e1000_media_type_fiber
) ?
1956 e1000_setup_fiber_link(nic
) : e1000_setup_copper_link(nic
);
1961 /* Initialize the flow control address, type, and PAUSE timer
1962 * registers to their default values. This is done even if flow
1963 * control is disabled, because it does not hurt anything to
1964 * initialize these registers.
1966 DEBUGOUT("Initializing the Flow Control address, type"
1967 "and timer regs\n");
1969 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1970 if (hw
->mac_type
!= e1000_ich8lan
) {
1971 E1000_WRITE_REG(hw
, FCT
, FLOW_CONTROL_TYPE
);
1972 E1000_WRITE_REG(hw
, FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
1973 E1000_WRITE_REG(hw
, FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
1976 E1000_WRITE_REG(hw
, FCTTV
, hw
->fc_pause_time
);
1978 /* Set the flow control receive threshold registers. Normally,
1979 * these registers will be set to a default threshold that may be
1980 * adjusted later by the driver's runtime code. However, if the
1981 * ability to transmit pause frames in not enabled, then these
1982 * registers will be set to 0.
1984 if (!(hw
->fc
& e1000_fc_tx_pause
)) {
1985 E1000_WRITE_REG(hw
, FCRTL
, 0);
1986 E1000_WRITE_REG(hw
, FCRTH
, 0);
1988 /* We need to set up the Receive Threshold high and low water marks
1989 * as well as (optionally) enabling the transmission of XON frames.
1991 if (hw
->fc_send_xon
) {
1992 E1000_WRITE_REG(hw
, FCRTL
,
1993 (hw
->fc_low_water
| E1000_FCRTL_XONE
));
1994 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
1996 E1000_WRITE_REG(hw
, FCRTL
, hw
->fc_low_water
);
1997 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
2003 /******************************************************************************
2004 * Sets up link for a fiber based adapter
2006 * hw - Struct containing variables accessed by shared code
2008 * Manipulates Physical Coding Sublayer functions in order to configure
2009 * link. Assumes the hardware has been previously reset and the transmitter
2010 * and receiver are not enabled.
2011 *****************************************************************************/
2013 e1000_setup_fiber_link(struct eth_device
*nic
)
2015 struct e1000_hw
*hw
= nic
->priv
;
2024 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2025 * set when the optics detect a signal. On older adapters, it will be
2026 * cleared when there is a signal
2028 ctrl
= E1000_READ_REG(hw
, CTRL
);
2029 if ((hw
->mac_type
> e1000_82544
) && !(ctrl
& E1000_CTRL_ILOS
))
2030 signal
= E1000_CTRL_SWDPIN1
;
2034 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic
->name
, signal
,
2036 /* Take the link out of reset */
2037 ctrl
&= ~(E1000_CTRL_LRST
);
2039 e1000_config_collision_dist(hw
);
2041 /* Check for a software override of the flow control settings, and setup
2042 * the device accordingly. If auto-negotiation is enabled, then software
2043 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2044 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
2045 * auto-negotiation is disabled, then software will have to manually
2046 * configure the two flow control enable bits in the CTRL register.
2048 * The possible values of the "fc" parameter are:
2049 * 0: Flow control is completely disabled
2050 * 1: Rx flow control is enabled (we can receive pause frames, but
2051 * not send pause frames).
2052 * 2: Tx flow control is enabled (we can send pause frames but we do
2053 * not support receiving pause frames).
2054 * 3: Both Rx and TX flow control (symmetric) are enabled.
2058 /* Flow control is completely disabled by a software over-ride. */
2059 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
2061 case e1000_fc_rx_pause
:
2062 /* RX Flow control is enabled and TX Flow control is disabled by a
2063 * software over-ride. Since there really isn't a way to advertise
2064 * that we are capable of RX Pause ONLY, we will advertise that we
2065 * support both symmetric and asymmetric RX PAUSE. Later, we will
2066 * disable the adapter's ability to send PAUSE frames.
2068 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
2070 case e1000_fc_tx_pause
:
2071 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2072 * software over-ride.
2074 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
2077 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2078 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
2081 DEBUGOUT("Flow control param set incorrectly\n");
2082 return -E1000_ERR_CONFIG
;
2086 /* Since auto-negotiation is enabled, take the link out of reset (the link
2087 * will be in reset, because we previously reset the chip). This will
2088 * restart auto-negotiation. If auto-neogtiation is successful then the
2089 * link-up status bit will be set and the flow control enable bits (RFCE
2090 * and TFCE) will be set according to their negotiated value.
2092 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw
);
2094 E1000_WRITE_REG(hw
, TXCW
, txcw
);
2095 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2096 E1000_WRITE_FLUSH(hw
);
2101 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2102 * indication in the Device Status Register. Time-out if a link isn't
2103 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2104 * less than 500 milliseconds even if the other end is doing it in SW).
2106 if ((E1000_READ_REG(hw
, CTRL
) & E1000_CTRL_SWDPIN1
) == signal
) {
2107 DEBUGOUT("Looking for Link\n");
2108 for (i
= 0; i
< (LINK_UP_TIMEOUT
/ 10); i
++) {
2110 status
= E1000_READ_REG(hw
, STATUS
);
2111 if (status
& E1000_STATUS_LU
)
2114 if (i
== (LINK_UP_TIMEOUT
/ 10)) {
2115 /* AutoNeg failed to achieve a link, so we'll call
2116 * e1000_check_for_link. This routine will force the link up if we
2117 * detect a signal. This will allow us to communicate with
2118 * non-autonegotiating link partners.
2120 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2121 hw
->autoneg_failed
= 1;
2122 ret_val
= e1000_check_for_link(nic
);
2124 DEBUGOUT("Error while checking for link\n");
2127 hw
->autoneg_failed
= 0;
2129 hw
->autoneg_failed
= 0;
2130 DEBUGOUT("Valid Link Found\n");
2133 DEBUGOUT("No Signal Detected\n");
2134 return -E1000_ERR_NOLINK
;
2139 /******************************************************************************
2140 * Make sure we have a valid PHY and change PHY mode before link setup.
2142 * hw - Struct containing variables accessed by shared code
2143 ******************************************************************************/
2145 e1000_copper_link_preconfig(struct e1000_hw
*hw
)
2153 ctrl
= E1000_READ_REG(hw
, CTRL
);
2154 /* With 82543, we need to force speed and duplex on the MAC equal to what
2155 * the PHY speed and duplex configuration is. In addition, we need to
2156 * perform a hardware reset on the PHY to take it out of reset.
2158 if (hw
->mac_type
> e1000_82543
) {
2159 ctrl
|= E1000_CTRL_SLU
;
2160 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2161 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2163 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
2165 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2166 ret_val
= e1000_phy_hw_reset(hw
);
2171 /* Make sure we have a valid PHY */
2172 ret_val
= e1000_detect_gig_phy(hw
);
2174 DEBUGOUT("Error, did not detect valid phy.\n");
2177 DEBUGOUT("Phy ID = %x \n", hw
->phy_id
);
2179 /* Set PHY to class A mode (if necessary) */
2180 ret_val
= e1000_set_phy_mode(hw
);
2183 if ((hw
->mac_type
== e1000_82545_rev_3
) ||
2184 (hw
->mac_type
== e1000_82546_rev_3
)) {
2185 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
2187 phy_data
|= 0x00000008;
2188 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
,
2192 if (hw
->mac_type
<= e1000_82543
||
2193 hw
->mac_type
== e1000_82541
|| hw
->mac_type
== e1000_82547
||
2194 hw
->mac_type
== e1000_82541_rev_2
2195 || hw
->mac_type
== e1000_82547_rev_2
)
2196 hw
->phy_reset_disable
= false;
2198 return E1000_SUCCESS
;
2201 /*****************************************************************************
2203 * This function sets the lplu state according to the active flag. When
2204 * activating lplu this function also disables smart speed and vise versa.
2205 * lplu will not be activated unless the device autonegotiation advertisment
2206 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2207 * hw: Struct containing variables accessed by shared code
2208 * active - true to enable lplu false to disable lplu.
2210 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2211 * E1000_SUCCESS at any other case.
2213 ****************************************************************************/
2216 e1000_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
2218 uint32_t phy_ctrl
= 0;
2223 if (hw
->phy_type
!= e1000_phy_igp
&& hw
->phy_type
!= e1000_phy_igp_2
2224 && hw
->phy_type
!= e1000_phy_igp_3
)
2225 return E1000_SUCCESS
;
2227 /* During driver activity LPLU should not be used or it will attain link
2228 * from the lowest speeds starting from 10Mbps. The capability is used
2229 * for Dx transitions and states */
2230 if (hw
->mac_type
== e1000_82541_rev_2
2231 || hw
->mac_type
== e1000_82547_rev_2
) {
2232 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
2236 } else if (hw
->mac_type
== e1000_ich8lan
) {
2237 /* MAC writes into PHY register based on the state transition
2238 * and start auto-negotiation. SW driver can overwrite the
2239 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2240 phy_ctrl
= E1000_READ_REG(hw
, PHY_CTRL
);
2242 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
2249 if (hw
->mac_type
== e1000_82541_rev_2
||
2250 hw
->mac_type
== e1000_82547_rev_2
) {
2251 phy_data
&= ~IGP01E1000_GMII_FLEX_SPD
;
2252 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
2257 if (hw
->mac_type
== e1000_ich8lan
) {
2258 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
2259 E1000_WRITE_REG(hw
, PHY_CTRL
, phy_ctrl
);
2261 phy_data
&= ~IGP02E1000_PM_D3_LPLU
;
2262 ret_val
= e1000_write_phy_reg(hw
,
2263 IGP02E1000_PHY_POWER_MGMT
, phy_data
);
2269 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2270 * Dx states where the power conservation is most important. During
2271 * driver activity we should enable SmartSpeed, so performance is
2273 if (hw
->smart_speed
== e1000_smart_speed_on
) {
2274 ret_val
= e1000_read_phy_reg(hw
,
2275 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2279 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2280 ret_val
= e1000_write_phy_reg(hw
,
2281 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2284 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
2285 ret_val
= e1000_read_phy_reg(hw
,
2286 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2290 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2291 ret_val
= e1000_write_phy_reg(hw
,
2292 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2297 } else if ((hw
->autoneg_advertised
== AUTONEG_ADVERTISE_SPEED_DEFAULT
)
2298 || (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_ALL
) ||
2299 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_100_ALL
)) {
2301 if (hw
->mac_type
== e1000_82541_rev_2
||
2302 hw
->mac_type
== e1000_82547_rev_2
) {
2303 phy_data
|= IGP01E1000_GMII_FLEX_SPD
;
2304 ret_val
= e1000_write_phy_reg(hw
,
2305 IGP01E1000_GMII_FIFO
, phy_data
);
2309 if (hw
->mac_type
== e1000_ich8lan
) {
2310 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
2311 E1000_WRITE_REG(hw
, PHY_CTRL
, phy_ctrl
);
2313 phy_data
|= IGP02E1000_PM_D3_LPLU
;
2314 ret_val
= e1000_write_phy_reg(hw
,
2315 IGP02E1000_PHY_POWER_MGMT
, phy_data
);
2321 /* When LPLU is enabled we should disable SmartSpeed */
2322 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2327 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2328 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2333 return E1000_SUCCESS
;
2336 /*****************************************************************************
2338 * This function sets the lplu d0 state according to the active flag. When
2339 * activating lplu this function also disables smart speed and vise versa.
2340 * lplu will not be activated unless the device autonegotiation advertisment
2341 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2342 * hw: Struct containing variables accessed by shared code
2343 * active - true to enable lplu false to disable lplu.
2345 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2346 * E1000_SUCCESS at any other case.
2348 ****************************************************************************/
2351 e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
2353 uint32_t phy_ctrl
= 0;
2358 if (hw
->mac_type
<= e1000_82547_rev_2
)
2359 return E1000_SUCCESS
;
2361 if (hw
->mac_type
== e1000_ich8lan
) {
2362 phy_ctrl
= E1000_READ_REG(hw
, PHY_CTRL
);
2363 } else if (hw
->mac_type
== e1000_igb
) {
2364 phy_ctrl
= E1000_READ_REG(hw
, I210_PHY_CTRL
);
2366 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
2373 if (hw
->mac_type
== e1000_ich8lan
) {
2374 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
2375 E1000_WRITE_REG(hw
, PHY_CTRL
, phy_ctrl
);
2376 } else if (hw
->mac_type
== e1000_igb
) {
2377 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
2378 E1000_WRITE_REG(hw
, I210_PHY_CTRL
, phy_ctrl
);
2380 phy_data
&= ~IGP02E1000_PM_D0_LPLU
;
2381 ret_val
= e1000_write_phy_reg(hw
,
2382 IGP02E1000_PHY_POWER_MGMT
, phy_data
);
2387 if (hw
->mac_type
== e1000_igb
)
2388 return E1000_SUCCESS
;
2390 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2391 * Dx states where the power conservation is most important. During
2392 * driver activity we should enable SmartSpeed, so performance is
2394 if (hw
->smart_speed
== e1000_smart_speed_on
) {
2395 ret_val
= e1000_read_phy_reg(hw
,
2396 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2400 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2401 ret_val
= e1000_write_phy_reg(hw
,
2402 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2405 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
2406 ret_val
= e1000_read_phy_reg(hw
,
2407 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2411 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2412 ret_val
= e1000_write_phy_reg(hw
,
2413 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2421 if (hw
->mac_type
== e1000_ich8lan
) {
2422 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
2423 E1000_WRITE_REG(hw
, PHY_CTRL
, phy_ctrl
);
2424 } else if (hw
->mac_type
== e1000_igb
) {
2425 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
2426 E1000_WRITE_REG(hw
, I210_PHY_CTRL
, phy_ctrl
);
2428 phy_data
|= IGP02E1000_PM_D0_LPLU
;
2429 ret_val
= e1000_write_phy_reg(hw
,
2430 IGP02E1000_PHY_POWER_MGMT
, phy_data
);
2435 if (hw
->mac_type
== e1000_igb
)
2436 return E1000_SUCCESS
;
2438 /* When LPLU is enabled we should disable SmartSpeed */
2439 ret_val
= e1000_read_phy_reg(hw
,
2440 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2444 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2445 ret_val
= e1000_write_phy_reg(hw
,
2446 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2451 return E1000_SUCCESS
;
2454 /********************************************************************
2455 * Copper link setup for e1000_phy_igp series.
2457 * hw - Struct containing variables accessed by shared code
2458 *********************************************************************/
2460 e1000_copper_link_igp_setup(struct e1000_hw
*hw
)
2468 if (hw
->phy_reset_disable
)
2469 return E1000_SUCCESS
;
2471 ret_val
= e1000_phy_reset(hw
);
2473 DEBUGOUT("Error Resetting the PHY\n");
2477 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2479 if (hw
->mac_type
!= e1000_ich8lan
) {
2480 /* Configure activity LED after PHY reset */
2481 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
2482 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
2483 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
2484 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
2487 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2488 if (hw
->phy_type
== e1000_phy_igp
) {
2489 /* disable lplu d3 during driver init */
2490 ret_val
= e1000_set_d3_lplu_state(hw
, false);
2492 DEBUGOUT("Error Disabling LPLU D3\n");
2497 /* disable lplu d0 during driver init */
2498 ret_val
= e1000_set_d0_lplu_state(hw
, false);
2500 DEBUGOUT("Error Disabling LPLU D0\n");
2503 /* Configure mdi-mdix settings */
2504 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
2508 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
2509 hw
->dsp_config_state
= e1000_dsp_config_disabled
;
2510 /* Force MDI for earlier revs of the IGP PHY */
2511 phy_data
&= ~(IGP01E1000_PSCR_AUTO_MDIX
2512 | IGP01E1000_PSCR_FORCE_MDI_MDIX
);
2516 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
2517 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
2521 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
2524 phy_data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
2528 phy_data
|= IGP01E1000_PSCR_AUTO_MDIX
;
2532 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
2536 /* set auto-master slave resolution settings */
2538 e1000_ms_type phy_ms_setting
= hw
->master_slave
;
2540 if (hw
->ffe_config_state
== e1000_ffe_config_active
)
2541 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
2543 if (hw
->dsp_config_state
== e1000_dsp_config_activated
)
2544 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
2546 /* when autonegotiation advertisment is only 1000Mbps then we
2547 * should disable SmartSpeed and enable Auto MasterSlave
2548 * resolution as hardware default. */
2549 if (hw
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
2550 /* Disable SmartSpeed */
2551 ret_val
= e1000_read_phy_reg(hw
,
2552 IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
2555 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2556 ret_val
= e1000_write_phy_reg(hw
,
2557 IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
2560 /* Set auto Master/Slave resolution process */
2561 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
,
2565 phy_data
&= ~CR_1000T_MS_ENABLE
;
2566 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
,
2572 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
2576 /* load defaults for future use */
2577 hw
->original_master_slave
= (phy_data
& CR_1000T_MS_ENABLE
) ?
2578 ((phy_data
& CR_1000T_MS_VALUE
) ?
2579 e1000_ms_force_master
:
2580 e1000_ms_force_slave
) :
2583 switch (phy_ms_setting
) {
2584 case e1000_ms_force_master
:
2585 phy_data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
2587 case e1000_ms_force_slave
:
2588 phy_data
|= CR_1000T_MS_ENABLE
;
2589 phy_data
&= ~(CR_1000T_MS_VALUE
);
2592 phy_data
&= ~CR_1000T_MS_ENABLE
;
2596 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
2601 return E1000_SUCCESS
;
2604 /*****************************************************************************
2605 * This function checks the mode of the firmware.
2607 * returns - true when the mode is IAMT or false.
2608 ****************************************************************************/
2610 e1000_check_mng_mode(struct e1000_hw
*hw
)
2615 fwsm
= E1000_READ_REG(hw
, FWSM
);
2617 if (hw
->mac_type
== e1000_ich8lan
) {
2618 if ((fwsm
& E1000_FWSM_MODE_MASK
) ==
2619 (E1000_MNG_ICH_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
2621 } else if ((fwsm
& E1000_FWSM_MODE_MASK
) ==
2622 (E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
2629 e1000_write_kmrn_reg(struct e1000_hw
*hw
, uint32_t reg_addr
, uint16_t data
)
2631 uint16_t swfw
= E1000_SWFW_PHY0_SM
;
2635 if (e1000_is_second_port(hw
))
2636 swfw
= E1000_SWFW_PHY1_SM
;
2638 if (e1000_swfw_sync_acquire(hw
, swfw
))
2639 return -E1000_ERR_SWFW_SYNC
;
2641 reg_val
= ((reg_addr
<< E1000_KUMCTRLSTA_OFFSET_SHIFT
)
2642 & E1000_KUMCTRLSTA_OFFSET
) | data
;
2643 E1000_WRITE_REG(hw
, KUMCTRLSTA
, reg_val
);
2646 return E1000_SUCCESS
;
2650 e1000_read_kmrn_reg(struct e1000_hw
*hw
, uint32_t reg_addr
, uint16_t *data
)
2652 uint16_t swfw
= E1000_SWFW_PHY0_SM
;
2656 if (e1000_is_second_port(hw
))
2657 swfw
= E1000_SWFW_PHY1_SM
;
2659 if (e1000_swfw_sync_acquire(hw
, swfw
)) {
2660 debug("%s[%i]\n", __func__
, __LINE__
);
2661 return -E1000_ERR_SWFW_SYNC
;
2664 /* Write register address */
2665 reg_val
= ((reg_addr
<< E1000_KUMCTRLSTA_OFFSET_SHIFT
) &
2666 E1000_KUMCTRLSTA_OFFSET
) | E1000_KUMCTRLSTA_REN
;
2667 E1000_WRITE_REG(hw
, KUMCTRLSTA
, reg_val
);
2670 /* Read the data returned */
2671 reg_val
= E1000_READ_REG(hw
, KUMCTRLSTA
);
2672 *data
= (uint16_t)reg_val
;
2674 return E1000_SUCCESS
;
2677 /********************************************************************
2678 * Copper link setup for e1000_phy_gg82563 series.
2680 * hw - Struct containing variables accessed by shared code
2681 *********************************************************************/
2683 e1000_copper_link_ggp_setup(struct e1000_hw
*hw
)
2691 if (!hw
->phy_reset_disable
) {
2692 /* Enable CRS on TX for half-duplex operation. */
2693 ret_val
= e1000_read_phy_reg(hw
,
2694 GG82563_PHY_MAC_SPEC_CTRL
, &phy_data
);
2698 phy_data
|= GG82563_MSCR_ASSERT_CRS_ON_TX
;
2699 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2700 phy_data
|= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ
;
2702 ret_val
= e1000_write_phy_reg(hw
,
2703 GG82563_PHY_MAC_SPEC_CTRL
, phy_data
);
2708 * MDI/MDI-X = 0 (default)
2709 * 0 - Auto for all speeds
2712 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2714 ret_val
= e1000_read_phy_reg(hw
,
2715 GG82563_PHY_SPEC_CTRL
, &phy_data
);
2719 phy_data
&= ~GG82563_PSCR_CROSSOVER_MODE_MASK
;
2723 phy_data
|= GG82563_PSCR_CROSSOVER_MODE_MDI
;
2726 phy_data
|= GG82563_PSCR_CROSSOVER_MODE_MDIX
;
2730 phy_data
|= GG82563_PSCR_CROSSOVER_MODE_AUTO
;
2735 * disable_polarity_correction = 0 (default)
2736 * Automatic Correction for Reversed Cable Polarity
2740 phy_data
&= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE
;
2741 ret_val
= e1000_write_phy_reg(hw
,
2742 GG82563_PHY_SPEC_CTRL
, phy_data
);
2747 /* SW Reset the PHY so all changes take effect */
2748 ret_val
= e1000_phy_reset(hw
);
2750 DEBUGOUT("Error Resetting the PHY\n");
2753 } /* phy_reset_disable */
2755 if (hw
->mac_type
== e1000_80003es2lan
) {
2756 /* Bypass RX and TX FIFO's */
2757 ret_val
= e1000_write_kmrn_reg(hw
,
2758 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL
,
2759 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2760 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS
);
2764 ret_val
= e1000_read_phy_reg(hw
,
2765 GG82563_PHY_SPEC_CTRL_2
, &phy_data
);
2769 phy_data
&= ~GG82563_PSCR2_REVERSE_AUTO_NEG
;
2770 ret_val
= e1000_write_phy_reg(hw
,
2771 GG82563_PHY_SPEC_CTRL_2
, phy_data
);
2776 reg_data
= E1000_READ_REG(hw
, CTRL_EXT
);
2777 reg_data
&= ~(E1000_CTRL_EXT_LINK_MODE_MASK
);
2778 E1000_WRITE_REG(hw
, CTRL_EXT
, reg_data
);
2780 ret_val
= e1000_read_phy_reg(hw
,
2781 GG82563_PHY_PWR_MGMT_CTRL
, &phy_data
);
2785 /* Do not init these registers when the HW is in IAMT mode, since the
2786 * firmware will have already initialized them. We only initialize
2787 * them if the HW is not in IAMT mode.
2789 if (e1000_check_mng_mode(hw
) == false) {
2790 /* Enable Electrical Idle on the PHY */
2791 phy_data
|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE
;
2792 ret_val
= e1000_write_phy_reg(hw
,
2793 GG82563_PHY_PWR_MGMT_CTRL
, phy_data
);
2797 ret_val
= e1000_read_phy_reg(hw
,
2798 GG82563_PHY_KMRN_MODE_CTRL
, &phy_data
);
2802 phy_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
2803 ret_val
= e1000_write_phy_reg(hw
,
2804 GG82563_PHY_KMRN_MODE_CTRL
, phy_data
);
2810 /* Workaround: Disable padding in Kumeran interface in the MAC
2811 * and in the PHY to avoid CRC errors.
2813 ret_val
= e1000_read_phy_reg(hw
,
2814 GG82563_PHY_INBAND_CTRL
, &phy_data
);
2817 phy_data
|= GG82563_ICR_DIS_PADDING
;
2818 ret_val
= e1000_write_phy_reg(hw
,
2819 GG82563_PHY_INBAND_CTRL
, phy_data
);
2823 return E1000_SUCCESS
;
2826 /********************************************************************
2827 * Copper link setup for e1000_phy_m88 series.
2829 * hw - Struct containing variables accessed by shared code
2830 *********************************************************************/
2832 e1000_copper_link_mgp_setup(struct e1000_hw
*hw
)
2839 if (hw
->phy_reset_disable
)
2840 return E1000_SUCCESS
;
2842 /* Enable CRS on TX. This must be set for half-duplex operation. */
2843 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
2847 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
2850 * MDI/MDI-X = 0 (default)
2851 * 0 - Auto for all speeds
2854 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2856 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
2860 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
2863 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
2866 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
2870 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
2875 * disable_polarity_correction = 0 (default)
2876 * Automatic Correction for Reversed Cable Polarity
2880 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
2881 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
2885 if (hw
->phy_revision
< M88E1011_I_REV_4
) {
2886 /* Force TX_CLK in the Extended PHY Specific Control Register
2889 ret_val
= e1000_read_phy_reg(hw
,
2890 M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
2894 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
2896 if ((hw
->phy_revision
== E1000_REVISION_2
) &&
2897 (hw
->phy_id
== M88E1111_I_PHY_ID
)) {
2898 /* Vidalia Phy, set the downshift counter to 5x */
2899 phy_data
&= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
);
2900 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
2901 ret_val
= e1000_write_phy_reg(hw
,
2902 M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
2906 /* Configure Master and Slave downshift values */
2907 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2908 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
2909 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2910 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
2911 ret_val
= e1000_write_phy_reg(hw
,
2912 M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
2918 /* SW Reset the PHY so all changes take effect */
2919 ret_val
= e1000_phy_reset(hw
);
2921 DEBUGOUT("Error Resetting the PHY\n");
2925 return E1000_SUCCESS
;
2928 /********************************************************************
2929 * Setup auto-negotiation and flow control advertisements,
2930 * and then perform auto-negotiation.
2932 * hw - Struct containing variables accessed by shared code
2933 *********************************************************************/
2935 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
2942 /* Perform some bounds checking on the hw->autoneg_advertised
2943 * parameter. If this variable is zero, then set it to the default.
2945 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
2947 /* If autoneg_advertised is zero, we assume it was not defaulted
2948 * by the calling code so we set to advertise full capability.
2950 if (hw
->autoneg_advertised
== 0)
2951 hw
->autoneg_advertised
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
2953 /* IFE phy only supports 10/100 */
2954 if (hw
->phy_type
== e1000_phy_ife
)
2955 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_10_100_ALL
;
2957 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2958 ret_val
= e1000_phy_setup_autoneg(hw
);
2960 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2963 DEBUGOUT("Restarting Auto-Neg\n");
2965 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2966 * the Auto Neg Restart bit in the PHY control register.
2968 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
2972 phy_data
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
2973 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
2977 /* Does the user want to wait for Auto-Neg to complete here, or
2978 * check at a later time (for example, callback routine).
2980 /* If we do not wait for autonegtation to complete I
2981 * do not see a valid link status.
2982 * wait_autoneg_complete = 1 .
2984 if (hw
->wait_autoneg_complete
) {
2985 ret_val
= e1000_wait_autoneg(hw
);
2987 DEBUGOUT("Error while waiting for autoneg"
2993 hw
->get_link_status
= true;
2995 return E1000_SUCCESS
;
2998 /******************************************************************************
2999 * Config the MAC and the PHY after link is up.
3000 * 1) Set up the MAC to the current PHY speed/duplex
3001 * if we are on 82543. If we
3002 * are on newer silicon, we only need to configure
3003 * collision distance in the Transmit Control Register.
3004 * 2) Set up flow control on the MAC to that established with
3006 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3008 * hw - Struct containing variables accessed by shared code
3009 ******************************************************************************/
3011 e1000_copper_link_postconfig(struct e1000_hw
*hw
)
3016 if (hw
->mac_type
>= e1000_82544
) {
3017 e1000_config_collision_dist(hw
);
3019 ret_val
= e1000_config_mac_to_phy(hw
);
3021 DEBUGOUT("Error configuring MAC to PHY settings\n");
3025 ret_val
= e1000_config_fc_after_link_up(hw
);
3027 DEBUGOUT("Error Configuring Flow Control\n");
3030 return E1000_SUCCESS
;
3033 /******************************************************************************
3034 * Detects which PHY is present and setup the speed and duplex
3036 * hw - Struct containing variables accessed by shared code
3037 ******************************************************************************/
3039 e1000_setup_copper_link(struct eth_device
*nic
)
3041 struct e1000_hw
*hw
= nic
->priv
;
3049 switch (hw
->mac_type
) {
3050 case e1000_80003es2lan
:
3052 /* Set the mac to wait the maximum time between each
3053 * iteration and increase the max iterations when
3054 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3055 ret_val
= e1000_write_kmrn_reg(hw
,
3056 GG82563_REG(0x34, 4), 0xFFFF);
3059 ret_val
= e1000_read_kmrn_reg(hw
,
3060 GG82563_REG(0x34, 9), ®_data
);
3064 ret_val
= e1000_write_kmrn_reg(hw
,
3065 GG82563_REG(0x34, 9), reg_data
);
3072 /* Check if it is a valid PHY and set PHY mode if necessary. */
3073 ret_val
= e1000_copper_link_preconfig(hw
);
3076 switch (hw
->mac_type
) {
3077 case e1000_80003es2lan
:
3078 /* Kumeran registers are written-only */
3080 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT
;
3081 reg_data
|= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING
;
3082 ret_val
= e1000_write_kmrn_reg(hw
,
3083 E1000_KUMCTRLSTA_OFFSET_INB_CTRL
, reg_data
);
3091 if (hw
->phy_type
== e1000_phy_igp
||
3092 hw
->phy_type
== e1000_phy_igp_3
||
3093 hw
->phy_type
== e1000_phy_igp_2
) {
3094 ret_val
= e1000_copper_link_igp_setup(hw
);
3097 } else if (hw
->phy_type
== e1000_phy_m88
||
3098 hw
->phy_type
== e1000_phy_igb
) {
3099 ret_val
= e1000_copper_link_mgp_setup(hw
);
3102 } else if (hw
->phy_type
== e1000_phy_gg82563
) {
3103 ret_val
= e1000_copper_link_ggp_setup(hw
);
3109 /* Setup autoneg and flow control advertisement
3110 * and perform autonegotiation */
3111 ret_val
= e1000_copper_link_autoneg(hw
);
3115 /* Check link status. Wait up to 100 microseconds for link to become
3118 for (i
= 0; i
< 10; i
++) {
3119 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3122 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3126 if (phy_data
& MII_SR_LINK_STATUS
) {
3127 /* Config the MAC and PHY after link is up */
3128 ret_val
= e1000_copper_link_postconfig(hw
);
3132 DEBUGOUT("Valid link established!!!\n");
3133 return E1000_SUCCESS
;
3138 DEBUGOUT("Unable to establish link!!!\n");
3139 return E1000_SUCCESS
;
3142 /******************************************************************************
3143 * Configures PHY autoneg and flow control advertisement settings
3145 * hw - Struct containing variables accessed by shared code
3146 ******************************************************************************/
3148 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
3151 uint16_t mii_autoneg_adv_reg
;
3152 uint16_t mii_1000t_ctrl_reg
;
3156 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3157 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
3161 if (hw
->phy_type
!= e1000_phy_ife
) {
3162 /* Read the MII 1000Base-T Control Register (Address 9). */
3163 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
,
3164 &mii_1000t_ctrl_reg
);
3168 mii_1000t_ctrl_reg
= 0;
3170 /* Need to parse both autoneg_advertised and fc and set up
3171 * the appropriate PHY registers. First we will parse for
3172 * autoneg_advertised software override. Since we can advertise
3173 * a plethora of combinations, we need to check each bit
3177 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3178 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3179 * the 1000Base-T Control Register (Address 9).
3181 mii_autoneg_adv_reg
&= ~REG4_SPEED_MASK
;
3182 mii_1000t_ctrl_reg
&= ~REG9_SPEED_MASK
;
3184 DEBUGOUT("autoneg_advertised %x\n", hw
->autoneg_advertised
);
3186 /* Do we want to advertise 10 Mb Half Duplex? */
3187 if (hw
->autoneg_advertised
& ADVERTISE_10_HALF
) {
3188 DEBUGOUT("Advertise 10mb Half duplex\n");
3189 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
3192 /* Do we want to advertise 10 Mb Full Duplex? */
3193 if (hw
->autoneg_advertised
& ADVERTISE_10_FULL
) {
3194 DEBUGOUT("Advertise 10mb Full duplex\n");
3195 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
3198 /* Do we want to advertise 100 Mb Half Duplex? */
3199 if (hw
->autoneg_advertised
& ADVERTISE_100_HALF
) {
3200 DEBUGOUT("Advertise 100mb Half duplex\n");
3201 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
3204 /* Do we want to advertise 100 Mb Full Duplex? */
3205 if (hw
->autoneg_advertised
& ADVERTISE_100_FULL
) {
3206 DEBUGOUT("Advertise 100mb Full duplex\n");
3207 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
3210 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3211 if (hw
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
3213 ("Advertise 1000mb Half duplex requested, request denied!\n");
3216 /* Do we want to advertise 1000 Mb Full Duplex? */
3217 if (hw
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
3218 DEBUGOUT("Advertise 1000mb Full duplex\n");
3219 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
3222 /* Check for a software override of the flow control settings, and
3223 * setup the PHY advertisement registers accordingly. If
3224 * auto-negotiation is enabled, then software will have to set the
3225 * "PAUSE" bits to the correct value in the Auto-Negotiation
3226 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3228 * The possible values of the "fc" parameter are:
3229 * 0: Flow control is completely disabled
3230 * 1: Rx flow control is enabled (we can receive pause frames
3231 * but not send pause frames).
3232 * 2: Tx flow control is enabled (we can send pause frames
3233 * but we do not support receiving pause frames).
3234 * 3: Both Rx and TX flow control (symmetric) are enabled.
3235 * other: No software override. The flow control configuration
3236 * in the EEPROM is used.
3239 case e1000_fc_none
: /* 0 */
3240 /* Flow control (RX & TX) is completely disabled by a
3241 * software over-ride.
3243 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
3245 case e1000_fc_rx_pause
: /* 1 */
3246 /* RX Flow control is enabled, and TX Flow control is
3247 * disabled, by a software over-ride.
3249 /* Since there really isn't a way to advertise that we are
3250 * capable of RX Pause ONLY, we will advertise that we
3251 * support both symmetric and asymmetric RX PAUSE. Later
3252 * (in e1000_config_fc_after_link_up) we will disable the
3253 *hw's ability to send PAUSE frames.
3255 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
3257 case e1000_fc_tx_pause
: /* 2 */
3258 /* TX Flow control is enabled, and RX Flow control is
3259 * disabled, by a software over-ride.
3261 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
3262 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
3264 case e1000_fc_full
: /* 3 */
3265 /* Flow control (both RX and TX) is enabled by a software
3268 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
3271 DEBUGOUT("Flow control param set incorrectly\n");
3272 return -E1000_ERR_CONFIG
;
3275 ret_val
= e1000_write_phy_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
3279 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
3281 if (hw
->phy_type
!= e1000_phy_ife
) {
3282 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
,
3283 mii_1000t_ctrl_reg
);
3288 return E1000_SUCCESS
;
3291 /******************************************************************************
3292 * Sets the collision distance in the Transmit Control register
3294 * hw - Struct containing variables accessed by shared code
3296 * Link should have been established previously. Reads the speed and duplex
3297 * information from the Device Status register.
3298 ******************************************************************************/
3300 e1000_config_collision_dist(struct e1000_hw
*hw
)
3302 uint32_t tctl
, coll_dist
;
3306 if (hw
->mac_type
< e1000_82543
)
3307 coll_dist
= E1000_COLLISION_DISTANCE_82542
;
3309 coll_dist
= E1000_COLLISION_DISTANCE
;
3311 tctl
= E1000_READ_REG(hw
, TCTL
);
3313 tctl
&= ~E1000_TCTL_COLD
;
3314 tctl
|= coll_dist
<< E1000_COLD_SHIFT
;
3316 E1000_WRITE_REG(hw
, TCTL
, tctl
);
3317 E1000_WRITE_FLUSH(hw
);
3320 /******************************************************************************
3321 * Sets MAC speed and duplex settings to reflect the those in the PHY
3323 * hw - Struct containing variables accessed by shared code
3324 * mii_reg - data to write to the MII control register
3326 * The contents of the PHY register containing the needed information need to
3328 ******************************************************************************/
3330 e1000_config_mac_to_phy(struct e1000_hw
*hw
)
3337 /* Read the Device Control Register and set the bits to Force Speed
3340 ctrl
= E1000_READ_REG(hw
, CTRL
);
3341 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3342 ctrl
&= ~(E1000_CTRL_ILOS
);
3343 ctrl
|= (E1000_CTRL_SPD_SEL
);
3345 /* Set up duplex in the Device Control and Transmit Control
3346 * registers depending on negotiated values.
3348 if (e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
) < 0) {
3349 DEBUGOUT("PHY Read Error\n");
3350 return -E1000_ERR_PHY
;
3352 if (phy_data
& M88E1000_PSSR_DPLX
)
3353 ctrl
|= E1000_CTRL_FD
;
3355 ctrl
&= ~E1000_CTRL_FD
;
3357 e1000_config_collision_dist(hw
);
3359 /* Set up speed in the Device Control register depending on
3360 * negotiated values.
3362 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
3363 ctrl
|= E1000_CTRL_SPD_1000
;
3364 else if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
3365 ctrl
|= E1000_CTRL_SPD_100
;
3366 /* Write the configured values back to the Device Control Reg. */
3367 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
3371 /******************************************************************************
3372 * Forces the MAC's flow control settings.
3374 * hw - Struct containing variables accessed by shared code
3376 * Sets the TFCE and RFCE bits in the device control register to reflect
3377 * the adapter settings. TFCE and RFCE need to be explicitly set by
3378 * software when a Copper PHY is used because autonegotiation is managed
3379 * by the PHY rather than the MAC. Software must also configure these
3380 * bits when link is forced on a fiber connection.
3381 *****************************************************************************/
3383 e1000_force_mac_fc(struct e1000_hw
*hw
)
3389 /* Get the current configuration of the Device Control Register */
3390 ctrl
= E1000_READ_REG(hw
, CTRL
);
3392 /* Because we didn't get link via the internal auto-negotiation
3393 * mechanism (we either forced link or we got link via PHY
3394 * auto-neg), we have to manually enable/disable transmit an
3395 * receive flow control.
3397 * The "Case" statement below enables/disable flow control
3398 * according to the "hw->fc" parameter.
3400 * The possible values of the "fc" parameter are:
3401 * 0: Flow control is completely disabled
3402 * 1: Rx flow control is enabled (we can receive pause
3403 * frames but not send pause frames).
3404 * 2: Tx flow control is enabled (we can send pause frames
3405 * frames but we do not receive pause frames).
3406 * 3: Both Rx and TX flow control (symmetric) is enabled.
3407 * other: No other values should be possible at this point.
3412 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
3414 case e1000_fc_rx_pause
:
3415 ctrl
&= (~E1000_CTRL_TFCE
);
3416 ctrl
|= E1000_CTRL_RFCE
;
3418 case e1000_fc_tx_pause
:
3419 ctrl
&= (~E1000_CTRL_RFCE
);
3420 ctrl
|= E1000_CTRL_TFCE
;
3423 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
3426 DEBUGOUT("Flow control param set incorrectly\n");
3427 return -E1000_ERR_CONFIG
;
3430 /* Disable TX Flow Control for 82542 (rev 2.0) */
3431 if (hw
->mac_type
== e1000_82542_rev2_0
)
3432 ctrl
&= (~E1000_CTRL_TFCE
);
3434 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
3438 /******************************************************************************
3439 * Configures flow control settings after link is established
3441 * hw - Struct containing variables accessed by shared code
3443 * Should be called immediately after a valid link has been established.
3444 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3445 * and autonegotiation is enabled, the MAC flow control settings will be set
3446 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3447 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3448 *****************************************************************************/
3450 e1000_config_fc_after_link_up(struct e1000_hw
*hw
)
3453 uint16_t mii_status_reg
;
3454 uint16_t mii_nway_adv_reg
;
3455 uint16_t mii_nway_lp_ability_reg
;
3461 /* Check for the case where we have fiber media and auto-neg failed
3462 * so we had to force link. In this case, we need to force the
3463 * configuration of the MAC to match the "fc" parameter.
3465 if (((hw
->media_type
== e1000_media_type_fiber
) && (hw
->autoneg_failed
))
3466 || ((hw
->media_type
== e1000_media_type_internal_serdes
)
3467 && (hw
->autoneg_failed
))
3468 || ((hw
->media_type
== e1000_media_type_copper
)
3469 && (!hw
->autoneg
))) {
3470 ret_val
= e1000_force_mac_fc(hw
);
3472 DEBUGOUT("Error forcing flow control settings\n");
3477 /* Check for the case where we have copper media and auto-neg is
3478 * enabled. In this case, we need to check and see if Auto-Neg
3479 * has completed, and if so, how the PHY and link partner has
3480 * flow control configured.
3482 if (hw
->media_type
== e1000_media_type_copper
) {
3483 /* Read the MII Status Register and check to see if AutoNeg
3484 * has completed. We read this twice because this reg has
3485 * some "sticky" (latched) bits.
3487 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
) < 0) {
3488 DEBUGOUT("PHY Read Error \n");
3489 return -E1000_ERR_PHY
;
3491 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
) < 0) {
3492 DEBUGOUT("PHY Read Error \n");
3493 return -E1000_ERR_PHY
;
3496 if (mii_status_reg
& MII_SR_AUTONEG_COMPLETE
) {
3497 /* The AutoNeg process has completed, so we now need to
3498 * read both the Auto Negotiation Advertisement Register
3499 * (Address 4) and the Auto_Negotiation Base Page Ability
3500 * Register (Address 5) to determine how flow control was
3503 if (e1000_read_phy_reg
3504 (hw
, PHY_AUTONEG_ADV
, &mii_nway_adv_reg
) < 0) {
3505 DEBUGOUT("PHY Read Error\n");
3506 return -E1000_ERR_PHY
;
3508 if (e1000_read_phy_reg
3509 (hw
, PHY_LP_ABILITY
,
3510 &mii_nway_lp_ability_reg
) < 0) {
3511 DEBUGOUT("PHY Read Error\n");
3512 return -E1000_ERR_PHY
;
3515 /* Two bits in the Auto Negotiation Advertisement Register
3516 * (Address 4) and two bits in the Auto Negotiation Base
3517 * Page Ability Register (Address 5) determine flow control
3518 * for both the PHY and the link partner. The following
3519 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3520 * 1999, describes these PAUSE resolution bits and how flow
3521 * control is determined based upon these settings.
3522 * NOTE: DC = Don't Care
3524 * LOCAL DEVICE | LINK PARTNER
3525 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3526 *-------|---------|-------|---------|--------------------
3527 * 0 | 0 | DC | DC | e1000_fc_none
3528 * 0 | 1 | 0 | DC | e1000_fc_none
3529 * 0 | 1 | 1 | 0 | e1000_fc_none
3530 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3531 * 1 | 0 | 0 | DC | e1000_fc_none
3532 * 1 | DC | 1 | DC | e1000_fc_full
3533 * 1 | 1 | 0 | 0 | e1000_fc_none
3534 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3537 /* Are both PAUSE bits set to 1? If so, this implies
3538 * Symmetric Flow Control is enabled at both ends. The
3539 * ASM_DIR bits are irrelevant per the spec.
3541 * For Symmetric Flow Control:
3543 * LOCAL DEVICE | LINK PARTNER
3544 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3545 *-------|---------|-------|---------|--------------------
3546 * 1 | DC | 1 | DC | e1000_fc_full
3549 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
3550 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
3551 /* Now we need to check if the user selected RX ONLY
3552 * of pause frames. In this case, we had to advertise
3553 * FULL flow control because we could not advertise RX
3554 * ONLY. Hence, we must now check to see if we need to
3555 * turn OFF the TRANSMISSION of PAUSE frames.
3557 if (hw
->original_fc
== e1000_fc_full
) {
3558 hw
->fc
= e1000_fc_full
;
3559 DEBUGOUT("Flow Control = FULL.\r\n");
3561 hw
->fc
= e1000_fc_rx_pause
;
3563 ("Flow Control = RX PAUSE frames only.\r\n");
3566 /* For receiving PAUSE frames ONLY.
3568 * LOCAL DEVICE | LINK PARTNER
3569 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3570 *-------|---------|-------|---------|--------------------
3571 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3574 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
3575 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
3576 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
3577 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
))
3579 hw
->fc
= e1000_fc_tx_pause
;
3581 ("Flow Control = TX PAUSE frames only.\r\n");
3583 /* For transmitting PAUSE frames ONLY.
3585 * LOCAL DEVICE | LINK PARTNER
3586 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3587 *-------|---------|-------|---------|--------------------
3588 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3591 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
3592 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
3593 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
3594 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
))
3596 hw
->fc
= e1000_fc_rx_pause
;
3598 ("Flow Control = RX PAUSE frames only.\r\n");
3600 /* Per the IEEE spec, at this point flow control should be
3601 * disabled. However, we want to consider that we could
3602 * be connected to a legacy switch that doesn't advertise
3603 * desired flow control, but can be forced on the link
3604 * partner. So if we advertised no flow control, that is
3605 * what we will resolve to. If we advertised some kind of
3606 * receive capability (Rx Pause Only or Full Flow Control)
3607 * and the link partner advertised none, we will configure
3608 * ourselves to enable Rx Flow Control only. We can do
3609 * this safely for two reasons: If the link partner really
3610 * didn't want flow control enabled, and we enable Rx, no
3611 * harm done since we won't be receiving any PAUSE frames
3612 * anyway. If the intent on the link partner was to have
3613 * flow control enabled, then by us enabling RX only, we
3614 * can at least receive pause frames and process them.
3615 * This is a good idea because in most cases, since we are
3616 * predominantly a server NIC, more times than not we will
3617 * be asked to delay transmission of packets than asking
3618 * our link partner to pause transmission of frames.
3620 else if (hw
->original_fc
== e1000_fc_none
||
3621 hw
->original_fc
== e1000_fc_tx_pause
) {
3622 hw
->fc
= e1000_fc_none
;
3623 DEBUGOUT("Flow Control = NONE.\r\n");
3625 hw
->fc
= e1000_fc_rx_pause
;
3627 ("Flow Control = RX PAUSE frames only.\r\n");
3630 /* Now we need to do one last check... If we auto-
3631 * negotiated to HALF DUPLEX, flow control should not be
3632 * enabled per IEEE 802.3 spec.
3634 e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
3636 if (duplex
== HALF_DUPLEX
)
3637 hw
->fc
= e1000_fc_none
;
3639 /* Now we call a subroutine to actually force the MAC
3640 * controller to use the correct flow control settings.
3642 ret_val
= e1000_force_mac_fc(hw
);
3645 ("Error forcing flow control settings\n");
3650 ("Copper PHY and Auto Neg has not completed.\r\n");
3653 return E1000_SUCCESS
;
3656 /******************************************************************************
3657 * Checks to see if the link status of the hardware has changed.
3659 * hw - Struct containing variables accessed by shared code
3661 * Called by any function that needs to check the link status of the adapter.
3662 *****************************************************************************/
3664 e1000_check_for_link(struct eth_device
*nic
)
3666 struct e1000_hw
*hw
= nic
->priv
;
3674 uint16_t lp_capability
;
3678 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3679 * set when the optics detect a signal. On older adapters, it will be
3680 * cleared when there is a signal
3682 ctrl
= E1000_READ_REG(hw
, CTRL
);
3683 if ((hw
->mac_type
> e1000_82544
) && !(ctrl
& E1000_CTRL_ILOS
))
3684 signal
= E1000_CTRL_SWDPIN1
;
3688 status
= E1000_READ_REG(hw
, STATUS
);
3689 rxcw
= E1000_READ_REG(hw
, RXCW
);
3690 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl
, status
, rxcw
);
3692 /* If we have a copper PHY then we only want to go out to the PHY
3693 * registers to see if Auto-Neg has completed and/or if our link
3694 * status has changed. The get_link_status flag will be set if we
3695 * receive a Link Status Change interrupt or we have Rx Sequence
3698 if ((hw
->media_type
== e1000_media_type_copper
) && hw
->get_link_status
) {
3699 /* First we want to see if the MII Status Register reports
3700 * link. If so, then we want to get the current speed/duplex
3702 * Read the register twice since the link bit is sticky.
3704 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
) < 0) {
3705 DEBUGOUT("PHY Read Error\n");
3706 return -E1000_ERR_PHY
;
3708 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
) < 0) {
3709 DEBUGOUT("PHY Read Error\n");
3710 return -E1000_ERR_PHY
;
3713 if (phy_data
& MII_SR_LINK_STATUS
) {
3714 hw
->get_link_status
= false;
3716 /* No link detected */
3717 return -E1000_ERR_NOLINK
;
3720 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3721 * have Si on board that is 82544 or newer, Auto
3722 * Speed Detection takes care of MAC speed/duplex
3723 * configuration. So we only need to configure Collision
3724 * Distance in the MAC. Otherwise, we need to force
3725 * speed/duplex on the MAC to the current PHY speed/duplex
3728 if (hw
->mac_type
>= e1000_82544
)
3729 e1000_config_collision_dist(hw
);
3731 ret_val
= e1000_config_mac_to_phy(hw
);
3734 ("Error configuring MAC to PHY settings\n");
3739 /* Configure Flow Control now that Auto-Neg has completed. First, we
3740 * need to restore the desired flow control settings because we may
3741 * have had to re-autoneg with a different link partner.
3743 ret_val
= e1000_config_fc_after_link_up(hw
);
3745 DEBUGOUT("Error configuring flow control\n");
3749 /* At this point we know that we are on copper and we have
3750 * auto-negotiated link. These are conditions for checking the link
3751 * parter capability register. We use the link partner capability to
3752 * determine if TBI Compatibility needs to be turned on or off. If
3753 * the link partner advertises any speed in addition to Gigabit, then
3754 * we assume that they are GMII-based, and TBI compatibility is not
3755 * needed. If no other speeds are advertised, we assume the link
3756 * partner is TBI-based, and we turn on TBI Compatibility.
3758 if (hw
->tbi_compatibility_en
) {
3759 if (e1000_read_phy_reg
3760 (hw
, PHY_LP_ABILITY
, &lp_capability
) < 0) {
3761 DEBUGOUT("PHY Read Error\n");
3762 return -E1000_ERR_PHY
;
3764 if (lp_capability
& (NWAY_LPAR_10T_HD_CAPS
|
3765 NWAY_LPAR_10T_FD_CAPS
|
3766 NWAY_LPAR_100TX_HD_CAPS
|
3767 NWAY_LPAR_100TX_FD_CAPS
|
3768 NWAY_LPAR_100T4_CAPS
)) {
3769 /* If our link partner advertises anything in addition to
3770 * gigabit, we do not need to enable TBI compatibility.
3772 if (hw
->tbi_compatibility_on
) {
3773 /* If we previously were in the mode, turn it off. */
3774 rctl
= E1000_READ_REG(hw
, RCTL
);
3775 rctl
&= ~E1000_RCTL_SBP
;
3776 E1000_WRITE_REG(hw
, RCTL
, rctl
);
3777 hw
->tbi_compatibility_on
= false;
3780 /* If TBI compatibility is was previously off, turn it on. For
3781 * compatibility with a TBI link partner, we will store bad
3782 * packets. Some frames have an additional byte on the end and
3783 * will look like CRC errors to to the hardware.
3785 if (!hw
->tbi_compatibility_on
) {
3786 hw
->tbi_compatibility_on
= true;
3787 rctl
= E1000_READ_REG(hw
, RCTL
);
3788 rctl
|= E1000_RCTL_SBP
;
3789 E1000_WRITE_REG(hw
, RCTL
, rctl
);
3794 /* If we don't have link (auto-negotiation failed or link partner cannot
3795 * auto-negotiate), the cable is plugged in (we have signal), and our
3796 * link partner is not trying to auto-negotiate with us (we are receiving
3797 * idles or data), we need to force link up. We also need to give
3798 * auto-negotiation time to complete, in case the cable was just plugged
3799 * in. The autoneg_failed flag does this.
3801 else if ((hw
->media_type
== e1000_media_type_fiber
) &&
3802 (!(status
& E1000_STATUS_LU
)) &&
3803 ((ctrl
& E1000_CTRL_SWDPIN1
) == signal
) &&
3804 (!(rxcw
& E1000_RXCW_C
))) {
3805 if (hw
->autoneg_failed
== 0) {
3806 hw
->autoneg_failed
= 1;
3809 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3811 /* Disable auto-negotiation in the TXCW register */
3812 E1000_WRITE_REG(hw
, TXCW
, (hw
->txcw
& ~E1000_TXCW_ANE
));
3814 /* Force link-up and also force full-duplex. */
3815 ctrl
= E1000_READ_REG(hw
, CTRL
);
3816 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
3817 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
3819 /* Configure Flow Control after forcing link up. */
3820 ret_val
= e1000_config_fc_after_link_up(hw
);
3822 DEBUGOUT("Error configuring flow control\n");
3826 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3827 * auto-negotiation in the TXCW register and disable forced link in the
3828 * Device Control register in an attempt to auto-negotiate with our link
3831 else if ((hw
->media_type
== e1000_media_type_fiber
) &&
3832 (ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
3834 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3835 E1000_WRITE_REG(hw
, TXCW
, hw
->txcw
);
3836 E1000_WRITE_REG(hw
, CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
3841 /******************************************************************************
3842 * Configure the MAC-to-PHY interface for 10/100Mbps
3844 * hw - Struct containing variables accessed by shared code
3845 ******************************************************************************/
3847 e1000_configure_kmrn_for_10_100(struct e1000_hw
*hw
, uint16_t duplex
)
3849 int32_t ret_val
= E1000_SUCCESS
;
3855 reg_data
= E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT
;
3856 ret_val
= e1000_write_kmrn_reg(hw
,
3857 E1000_KUMCTRLSTA_OFFSET_HD_CTRL
, reg_data
);
3861 /* Configure Transmit Inter-Packet Gap */
3862 tipg
= E1000_READ_REG(hw
, TIPG
);
3863 tipg
&= ~E1000_TIPG_IPGT_MASK
;
3864 tipg
|= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100
;
3865 E1000_WRITE_REG(hw
, TIPG
, tipg
);
3867 ret_val
= e1000_read_phy_reg(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
3872 if (duplex
== HALF_DUPLEX
)
3873 reg_data
|= GG82563_KMCR_PASS_FALSE_CARRIER
;
3875 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
3877 ret_val
= e1000_write_phy_reg(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
3883 e1000_configure_kmrn_for_1000(struct e1000_hw
*hw
)
3885 int32_t ret_val
= E1000_SUCCESS
;
3891 reg_data
= E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT
;
3892 ret_val
= e1000_write_kmrn_reg(hw
,
3893 E1000_KUMCTRLSTA_OFFSET_HD_CTRL
, reg_data
);
3897 /* Configure Transmit Inter-Packet Gap */
3898 tipg
= E1000_READ_REG(hw
, TIPG
);
3899 tipg
&= ~E1000_TIPG_IPGT_MASK
;
3900 tipg
|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000
;
3901 E1000_WRITE_REG(hw
, TIPG
, tipg
);
3903 ret_val
= e1000_read_phy_reg(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
3908 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
3909 ret_val
= e1000_write_phy_reg(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
3914 /******************************************************************************
3915 * Detects the current speed and duplex settings of the hardware.
3917 * hw - Struct containing variables accessed by shared code
3918 * speed - Speed of the connection
3919 * duplex - Duplex setting of the connection
3920 *****************************************************************************/
3922 e1000_get_speed_and_duplex(struct e1000_hw
*hw
, uint16_t *speed
,
3931 if (hw
->mac_type
>= e1000_82543
) {
3932 status
= E1000_READ_REG(hw
, STATUS
);
3933 if (status
& E1000_STATUS_SPEED_1000
) {
3934 *speed
= SPEED_1000
;
3935 DEBUGOUT("1000 Mbs, ");
3936 } else if (status
& E1000_STATUS_SPEED_100
) {
3938 DEBUGOUT("100 Mbs, ");
3941 DEBUGOUT("10 Mbs, ");
3944 if (status
& E1000_STATUS_FD
) {
3945 *duplex
= FULL_DUPLEX
;
3946 DEBUGOUT("Full Duplex\r\n");
3948 *duplex
= HALF_DUPLEX
;
3949 DEBUGOUT(" Half Duplex\r\n");
3952 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3953 *speed
= SPEED_1000
;
3954 *duplex
= FULL_DUPLEX
;
3957 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3958 * even if it is operating at half duplex. Here we set the duplex
3959 * settings to match the duplex in the link partner's capabilities.
3961 if (hw
->phy_type
== e1000_phy_igp
&& hw
->speed_downgraded
) {
3962 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_EXP
, &phy_data
);
3966 if (!(phy_data
& NWAY_ER_LP_NWAY_CAPS
))
3967 *duplex
= HALF_DUPLEX
;
3969 ret_val
= e1000_read_phy_reg(hw
,
3970 PHY_LP_ABILITY
, &phy_data
);
3973 if ((*speed
== SPEED_100
&&
3974 !(phy_data
& NWAY_LPAR_100TX_FD_CAPS
))
3975 || (*speed
== SPEED_10
3976 && !(phy_data
& NWAY_LPAR_10T_FD_CAPS
)))
3977 *duplex
= HALF_DUPLEX
;
3981 if ((hw
->mac_type
== e1000_80003es2lan
) &&
3982 (hw
->media_type
== e1000_media_type_copper
)) {
3983 if (*speed
== SPEED_1000
)
3984 ret_val
= e1000_configure_kmrn_for_1000(hw
);
3986 ret_val
= e1000_configure_kmrn_for_10_100(hw
, *duplex
);
3990 return E1000_SUCCESS
;
3993 /******************************************************************************
3994 * Blocks until autoneg completes or times out (~4.5 seconds)
3996 * hw - Struct containing variables accessed by shared code
3997 ******************************************************************************/
3999 e1000_wait_autoneg(struct e1000_hw
*hw
)
4005 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4007 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4008 for (i
= PHY_AUTO_NEG_TIME
; i
> 0; i
--) {
4009 /* Read the MII Status Register and wait for Auto-Neg
4010 * Complete bit to be set.
4012 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
) < 0) {
4013 DEBUGOUT("PHY Read Error\n");
4014 return -E1000_ERR_PHY
;
4016 if (e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
) < 0) {
4017 DEBUGOUT("PHY Read Error\n");
4018 return -E1000_ERR_PHY
;
4020 if (phy_data
& MII_SR_AUTONEG_COMPLETE
) {
4021 DEBUGOUT("Auto-Neg complete.\n");
4026 DEBUGOUT("Auto-Neg timedout.\n");
4027 return -E1000_ERR_TIMEOUT
;
4030 /******************************************************************************
4031 * Raises the Management Data Clock
4033 * hw - Struct containing variables accessed by shared code
4034 * ctrl - Device control register's current value
4035 ******************************************************************************/
4037 e1000_raise_mdi_clk(struct e1000_hw
*hw
, uint32_t * ctrl
)
4039 /* Raise the clock input to the Management Data Clock (by setting the MDC
4040 * bit), and then delay 2 microseconds.
4042 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
| E1000_CTRL_MDC
));
4043 E1000_WRITE_FLUSH(hw
);
4047 /******************************************************************************
4048 * Lowers the Management Data Clock
4050 * hw - Struct containing variables accessed by shared code
4051 * ctrl - Device control register's current value
4052 ******************************************************************************/
4054 e1000_lower_mdi_clk(struct e1000_hw
*hw
, uint32_t * ctrl
)
4056 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4057 * bit), and then delay 2 microseconds.
4059 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
4060 E1000_WRITE_FLUSH(hw
);
4064 /******************************************************************************
4065 * Shifts data bits out to the PHY
4067 * hw - Struct containing variables accessed by shared code
4068 * data - Data to send out to the PHY
4069 * count - Number of bits to shift out
4071 * Bits are shifted out in MSB to LSB order.
4072 ******************************************************************************/
4074 e1000_shift_out_mdi_bits(struct e1000_hw
*hw
, uint32_t data
, uint16_t count
)
4079 /* We need to shift "count" number of bits out to the PHY. So, the value
4080 * in the "data" parameter will be shifted out to the PHY one bit at a
4081 * time. In order to do this, "data" must be broken down into bits.
4084 mask
<<= (count
- 1);
4086 ctrl
= E1000_READ_REG(hw
, CTRL
);
4088 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4089 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
4092 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4093 * then raising and lowering the Management Data Clock. A "0" is
4094 * shifted out to the PHY by setting the MDIO bit to "0" and then
4095 * raising and lowering the clock.
4098 ctrl
|= E1000_CTRL_MDIO
;
4100 ctrl
&= ~E1000_CTRL_MDIO
;
4102 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4103 E1000_WRITE_FLUSH(hw
);
4107 e1000_raise_mdi_clk(hw
, &ctrl
);
4108 e1000_lower_mdi_clk(hw
, &ctrl
);
4114 /******************************************************************************
4115 * Shifts data bits in from the PHY
4117 * hw - Struct containing variables accessed by shared code
4119 * Bits are shifted in in MSB to LSB order.
4120 ******************************************************************************/
4122 e1000_shift_in_mdi_bits(struct e1000_hw
*hw
)
4128 /* In order to read a register from the PHY, we need to shift in a total
4129 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4130 * to avoid contention on the MDIO pin when a read operation is performed.
4131 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4132 * by raising the input to the Management Data Clock (setting the MDC bit),
4133 * and then reading the value of the MDIO bit.
4135 ctrl
= E1000_READ_REG(hw
, CTRL
);
4137 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4138 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
4139 ctrl
&= ~E1000_CTRL_MDIO
;
4141 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4142 E1000_WRITE_FLUSH(hw
);
4144 /* Raise and Lower the clock before reading in the data. This accounts for
4145 * the turnaround bits. The first clock occurred when we clocked out the
4146 * last bit of the Register Address.
4148 e1000_raise_mdi_clk(hw
, &ctrl
);
4149 e1000_lower_mdi_clk(hw
, &ctrl
);
4151 for (data
= 0, i
= 0; i
< 16; i
++) {
4153 e1000_raise_mdi_clk(hw
, &ctrl
);
4154 ctrl
= E1000_READ_REG(hw
, CTRL
);
4155 /* Check to see if we shifted in a "1". */
4156 if (ctrl
& E1000_CTRL_MDIO
)
4158 e1000_lower_mdi_clk(hw
, &ctrl
);
4161 e1000_raise_mdi_clk(hw
, &ctrl
);
4162 e1000_lower_mdi_clk(hw
, &ctrl
);
4167 /*****************************************************************************
4168 * Reads the value from a PHY register
4170 * hw - Struct containing variables accessed by shared code
4171 * reg_addr - address of the PHY register to read
4172 ******************************************************************************/
4174 e1000_read_phy_reg(struct e1000_hw
*hw
, uint32_t reg_addr
, uint16_t * phy_data
)
4178 const uint32_t phy_addr
= 1;
4180 if (reg_addr
> MAX_PHY_REG_ADDRESS
) {
4181 DEBUGOUT("PHY Address %d is out of range\n", reg_addr
);
4182 return -E1000_ERR_PARAM
;
4185 if (hw
->mac_type
> e1000_82543
) {
4186 /* Set up Op-code, Phy Address, and register address in the MDI
4187 * Control register. The MAC will take care of interfacing with the
4188 * PHY to retrieve the desired data.
4190 mdic
= ((reg_addr
<< E1000_MDIC_REG_SHIFT
) |
4191 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
4192 (E1000_MDIC_OP_READ
));
4194 E1000_WRITE_REG(hw
, MDIC
, mdic
);
4196 /* Poll the ready bit to see if the MDI read completed */
4197 for (i
= 0; i
< 64; i
++) {
4199 mdic
= E1000_READ_REG(hw
, MDIC
);
4200 if (mdic
& E1000_MDIC_READY
)
4203 if (!(mdic
& E1000_MDIC_READY
)) {
4204 DEBUGOUT("MDI Read did not complete\n");
4205 return -E1000_ERR_PHY
;
4207 if (mdic
& E1000_MDIC_ERROR
) {
4208 DEBUGOUT("MDI Error\n");
4209 return -E1000_ERR_PHY
;
4211 *phy_data
= (uint16_t) mdic
;
4213 /* We must first send a preamble through the MDIO pin to signal the
4214 * beginning of an MII instruction. This is done by sending 32
4215 * consecutive "1" bits.
4217 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
4219 /* Now combine the next few fields that are required for a read
4220 * operation. We use this method instead of calling the
4221 * e1000_shift_out_mdi_bits routine five different times. The format of
4222 * a MII read instruction consists of a shift out of 14 bits and is
4223 * defined as follows:
4224 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4225 * followed by a shift in of 18 bits. This first two bits shifted in
4226 * are TurnAround bits used to avoid contention on the MDIO pin when a
4227 * READ operation is performed. These two bits are thrown away
4228 * followed by a shift in of 16 bits which contains the desired data.
4230 mdic
= ((reg_addr
) | (phy_addr
<< 5) |
4231 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
4233 e1000_shift_out_mdi_bits(hw
, mdic
, 14);
4235 /* Now that we've shifted out the read command to the MII, we need to
4236 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4239 *phy_data
= e1000_shift_in_mdi_bits(hw
);
4244 /******************************************************************************
4245 * Writes a value to a PHY register
4247 * hw - Struct containing variables accessed by shared code
4248 * reg_addr - address of the PHY register to write
4249 * data - data to write to the PHY
4250 ******************************************************************************/
4252 e1000_write_phy_reg(struct e1000_hw
*hw
, uint32_t reg_addr
, uint16_t phy_data
)
4256 const uint32_t phy_addr
= 1;
4258 if (reg_addr
> MAX_PHY_REG_ADDRESS
) {
4259 DEBUGOUT("PHY Address %d is out of range\n", reg_addr
);
4260 return -E1000_ERR_PARAM
;
4263 if (hw
->mac_type
> e1000_82543
) {
4264 /* Set up Op-code, Phy Address, register address, and data intended
4265 * for the PHY register in the MDI Control register. The MAC will take
4266 * care of interfacing with the PHY to send the desired data.
4268 mdic
= (((uint32_t) phy_data
) |
4269 (reg_addr
<< E1000_MDIC_REG_SHIFT
) |
4270 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
4271 (E1000_MDIC_OP_WRITE
));
4273 E1000_WRITE_REG(hw
, MDIC
, mdic
);
4275 /* Poll the ready bit to see if the MDI read completed */
4276 for (i
= 0; i
< 64; i
++) {
4278 mdic
= E1000_READ_REG(hw
, MDIC
);
4279 if (mdic
& E1000_MDIC_READY
)
4282 if (!(mdic
& E1000_MDIC_READY
)) {
4283 DEBUGOUT("MDI Write did not complete\n");
4284 return -E1000_ERR_PHY
;
4287 /* We'll need to use the SW defined pins to shift the write command
4288 * out to the PHY. We first send a preamble to the PHY to signal the
4289 * beginning of the MII instruction. This is done by sending 32
4290 * consecutive "1" bits.
4292 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
4294 /* Now combine the remaining required fields that will indicate a
4295 * write operation. We use this method instead of calling the
4296 * e1000_shift_out_mdi_bits routine for each field in the command. The
4297 * format of a MII write instruction is as follows:
4298 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4300 mdic
= ((PHY_TURNAROUND
) | (reg_addr
<< 2) | (phy_addr
<< 7) |
4301 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
4303 mdic
|= (uint32_t) phy_data
;
4305 e1000_shift_out_mdi_bits(hw
, mdic
, 32);
4310 /******************************************************************************
4311 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4312 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4313 * the caller to figure out how to deal with it.
4315 * hw - Struct containing variables accessed by shared code
4317 * returns: - E1000_BLK_PHY_RESET
4320 *****************************************************************************/
4322 e1000_check_phy_reset_block(struct e1000_hw
*hw
)
4327 if (hw
->mac_type
== e1000_ich8lan
) {
4328 fwsm
= E1000_READ_REG(hw
, FWSM
);
4329 return (fwsm
& E1000_FWSM_RSPCIPHY
) ? E1000_SUCCESS
4330 : E1000_BLK_PHY_RESET
;
4333 if (hw
->mac_type
> e1000_82547_rev_2
)
4334 manc
= E1000_READ_REG(hw
, MANC
);
4335 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
4336 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
4339 /***************************************************************************
4340 * Checks if the PHY configuration is done
4342 * hw: Struct containing variables accessed by shared code
4344 * returns: - E1000_ERR_RESET if fail to reset MAC
4345 * E1000_SUCCESS at any other case.
4347 ***************************************************************************/
4349 e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
4351 int32_t timeout
= PHY_CFG_TIMEOUT
;
4352 uint32_t cfg_mask
= E1000_EEPROM_CFG_DONE
;
4356 switch (hw
->mac_type
) {
4361 case e1000_80003es2lan
:
4362 /* Separate *_CFG_DONE_* bit for each port */
4363 if (e1000_is_second_port(hw
))
4364 cfg_mask
= E1000_EEPROM_CFG_DONE_PORT_1
;
4371 if (hw
->mac_type
== e1000_igb
) {
4372 if (E1000_READ_REG(hw
, I210_EEMNGCTL
) & cfg_mask
)
4375 if (E1000_READ_REG(hw
, EEMNGCTL
) & cfg_mask
)
4382 DEBUGOUT("MNG configuration cycle has not "
4384 return -E1000_ERR_RESET
;
4389 return E1000_SUCCESS
;
4392 /******************************************************************************
4393 * Returns the PHY to the power-on reset state
4395 * hw - Struct containing variables accessed by shared code
4396 ******************************************************************************/
4398 e1000_phy_hw_reset(struct e1000_hw
*hw
)
4400 uint16_t swfw
= E1000_SWFW_PHY0_SM
;
4401 uint32_t ctrl
, ctrl_ext
;
4407 /* In the case of the phy reset being blocked, it's not an error, we
4408 * simply return success without performing the reset. */
4409 ret_val
= e1000_check_phy_reset_block(hw
);
4411 return E1000_SUCCESS
;
4413 DEBUGOUT("Resetting Phy...\n");
4415 if (hw
->mac_type
> e1000_82543
) {
4416 if (e1000_is_second_port(hw
))
4417 swfw
= E1000_SWFW_PHY1_SM
;
4419 if (e1000_swfw_sync_acquire(hw
, swfw
)) {
4420 DEBUGOUT("Unable to acquire swfw sync\n");
4421 return -E1000_ERR_SWFW_SYNC
;
4424 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4425 * bit. Then, take it out of reset.
4427 ctrl
= E1000_READ_REG(hw
, CTRL
);
4428 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
4429 E1000_WRITE_FLUSH(hw
);
4431 if (hw
->mac_type
< e1000_82571
)
4436 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4437 E1000_WRITE_FLUSH(hw
);
4439 if (hw
->mac_type
>= e1000_82571
)
4442 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4443 * bit to put the PHY into reset. Then, take it out of reset.
4445 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
4446 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
4447 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
4448 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
4449 E1000_WRITE_FLUSH(hw
);
4451 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
4452 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
4453 E1000_WRITE_FLUSH(hw
);
4457 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
4458 /* Configure activity LED after PHY reset */
4459 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
4460 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
4461 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
4462 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
4465 /* Wait for FW to finish PHY configuration. */
4466 ret_val
= e1000_get_phy_cfg_done(hw
);
4467 if (ret_val
!= E1000_SUCCESS
)
4473 /******************************************************************************
4474 * IGP phy init script - initializes the GbE PHY
4476 * hw - Struct containing variables accessed by shared code
4477 *****************************************************************************/
4479 e1000_phy_init_script(struct e1000_hw
*hw
)
4482 uint16_t phy_saved_data
;
4485 if (hw
->phy_init_script
) {
4488 /* Save off the current value of register 0x2F5B to be
4489 * restored at the end of this routine. */
4490 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
4492 /* Disabled the PHY transmitter */
4493 e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
4497 e1000_write_phy_reg(hw
, 0x0000, 0x0140);
4501 switch (hw
->mac_type
) {
4504 e1000_write_phy_reg(hw
, 0x1F95, 0x0001);
4506 e1000_write_phy_reg(hw
, 0x1F71, 0xBD21);
4508 e1000_write_phy_reg(hw
, 0x1F79, 0x0018);
4510 e1000_write_phy_reg(hw
, 0x1F30, 0x1600);
4512 e1000_write_phy_reg(hw
, 0x1F31, 0x0014);
4514 e1000_write_phy_reg(hw
, 0x1F32, 0x161C);
4516 e1000_write_phy_reg(hw
, 0x1F94, 0x0003);
4518 e1000_write_phy_reg(hw
, 0x1F96, 0x003F);
4520 e1000_write_phy_reg(hw
, 0x2010, 0x0008);
4523 case e1000_82541_rev_2
:
4524 case e1000_82547_rev_2
:
4525 e1000_write_phy_reg(hw
, 0x1F73, 0x0099);
4531 e1000_write_phy_reg(hw
, 0x0000, 0x3300);
4535 /* Now enable the transmitter */
4537 e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
4539 if (hw
->mac_type
== e1000_82547
) {
4540 uint16_t fused
, fine
, coarse
;
4542 /* Move to analog registers page */
4543 e1000_read_phy_reg(hw
,
4544 IGP01E1000_ANALOG_SPARE_FUSE_STATUS
, &fused
);
4546 if (!(fused
& IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
)) {
4547 e1000_read_phy_reg(hw
,
4548 IGP01E1000_ANALOG_FUSE_STATUS
, &fused
);
4550 fine
= fused
& IGP01E1000_ANALOG_FUSE_FINE_MASK
;
4552 & IGP01E1000_ANALOG_FUSE_COARSE_MASK
;
4555 IGP01E1000_ANALOG_FUSE_COARSE_THRESH
) {
4557 IGP01E1000_ANALOG_FUSE_COARSE_10
;
4558 fine
-= IGP01E1000_ANALOG_FUSE_FINE_1
;
4560 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH
)
4561 fine
-= IGP01E1000_ANALOG_FUSE_FINE_10
;
4564 & IGP01E1000_ANALOG_FUSE_POLY_MASK
) |
4566 & IGP01E1000_ANALOG_FUSE_FINE_MASK
) |
4568 & IGP01E1000_ANALOG_FUSE_COARSE_MASK
);
4570 e1000_write_phy_reg(hw
,
4571 IGP01E1000_ANALOG_FUSE_CONTROL
, fused
);
4572 e1000_write_phy_reg(hw
,
4573 IGP01E1000_ANALOG_FUSE_BYPASS
,
4574 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
);
4580 /******************************************************************************
4583 * hw - Struct containing variables accessed by shared code
4585 * Sets bit 15 of the MII Control register
4586 ******************************************************************************/
4588 e1000_phy_reset(struct e1000_hw
*hw
)
4595 /* In the case of the phy reset being blocked, it's not an error, we
4596 * simply return success without performing the reset. */
4597 ret_val
= e1000_check_phy_reset_block(hw
);
4599 return E1000_SUCCESS
;
4601 switch (hw
->phy_type
) {
4603 case e1000_phy_igp_2
:
4604 case e1000_phy_igp_3
:
4607 ret_val
= e1000_phy_hw_reset(hw
);
4612 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
4616 phy_data
|= MII_CR_RESET
;
4617 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
4625 if (hw
->phy_type
== e1000_phy_igp
|| hw
->phy_type
== e1000_phy_igp_2
)
4626 e1000_phy_init_script(hw
);
4628 return E1000_SUCCESS
;
4631 static int e1000_set_phy_type (struct e1000_hw
*hw
)
4635 if (hw
->mac_type
== e1000_undefined
)
4636 return -E1000_ERR_PHY_TYPE
;
4638 switch (hw
->phy_id
) {
4639 case M88E1000_E_PHY_ID
:
4640 case M88E1000_I_PHY_ID
:
4641 case M88E1011_I_PHY_ID
:
4642 case M88E1111_I_PHY_ID
:
4643 hw
->phy_type
= e1000_phy_m88
;
4645 case IGP01E1000_I_PHY_ID
:
4646 if (hw
->mac_type
== e1000_82541
||
4647 hw
->mac_type
== e1000_82541_rev_2
||
4648 hw
->mac_type
== e1000_82547
||
4649 hw
->mac_type
== e1000_82547_rev_2
) {
4650 hw
->phy_type
= e1000_phy_igp
;
4653 case IGP03E1000_E_PHY_ID
:
4654 hw
->phy_type
= e1000_phy_igp_3
;
4657 case IFE_PLUS_E_PHY_ID
:
4658 case IFE_C_E_PHY_ID
:
4659 hw
->phy_type
= e1000_phy_ife
;
4661 case GG82563_E_PHY_ID
:
4662 if (hw
->mac_type
== e1000_80003es2lan
) {
4663 hw
->phy_type
= e1000_phy_gg82563
;
4666 case BME1000_E_PHY_ID
:
4667 hw
->phy_type
= e1000_phy_bm
;
4670 hw
->phy_type
= e1000_phy_igb
;
4674 /* Should never have loaded on this device */
4675 hw
->phy_type
= e1000_phy_undefined
;
4676 return -E1000_ERR_PHY_TYPE
;
4679 return E1000_SUCCESS
;
4682 /******************************************************************************
4683 * Probes the expected PHY address for known PHY IDs
4685 * hw - Struct containing variables accessed by shared code
4686 ******************************************************************************/
4688 e1000_detect_gig_phy(struct e1000_hw
*hw
)
4690 int32_t phy_init_status
, ret_val
;
4691 uint16_t phy_id_high
, phy_id_low
;
4696 /* The 82571 firmware may still be configuring the PHY. In this
4697 * case, we cannot access the PHY until the configuration is done. So
4698 * we explicitly set the PHY values. */
4699 if (hw
->mac_type
== e1000_82571
||
4700 hw
->mac_type
== e1000_82572
) {
4701 hw
->phy_id
= IGP01E1000_I_PHY_ID
;
4702 hw
->phy_type
= e1000_phy_igp_2
;
4703 return E1000_SUCCESS
;
4706 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4707 * work- around that forces PHY page 0 to be set or the reads fail.
4708 * The rest of the code in this routine uses e1000_read_phy_reg to
4709 * read the PHY ID. So for ESB-2 we need to have this set so our
4710 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4711 * the routines below will figure this out as well. */
4712 if (hw
->mac_type
== e1000_80003es2lan
)
4713 hw
->phy_type
= e1000_phy_gg82563
;
4715 /* Read the PHY ID Registers to identify which PHY is onboard. */
4716 ret_val
= e1000_read_phy_reg(hw
, PHY_ID1
, &phy_id_high
);
4720 hw
->phy_id
= (uint32_t) (phy_id_high
<< 16);
4722 ret_val
= e1000_read_phy_reg(hw
, PHY_ID2
, &phy_id_low
);
4726 hw
->phy_id
|= (uint32_t) (phy_id_low
& PHY_REVISION_MASK
);
4727 hw
->phy_revision
= (uint32_t) phy_id_low
& ~PHY_REVISION_MASK
;
4729 switch (hw
->mac_type
) {
4731 if (hw
->phy_id
== M88E1000_E_PHY_ID
)
4735 if (hw
->phy_id
== M88E1000_I_PHY_ID
)
4740 case e1000_82545_rev_3
:
4742 case e1000_82546_rev_3
:
4743 if (hw
->phy_id
== M88E1011_I_PHY_ID
)
4747 case e1000_82541_rev_2
:
4749 case e1000_82547_rev_2
:
4750 if(hw
->phy_id
== IGP01E1000_I_PHY_ID
)
4755 if (hw
->phy_id
== M88E1111_I_PHY_ID
)
4759 if (hw
->phy_id
== BME1000_E_PHY_ID
)
4762 case e1000_80003es2lan
:
4763 if (hw
->phy_id
== GG82563_E_PHY_ID
)
4767 if (hw
->phy_id
== IGP03E1000_E_PHY_ID
)
4769 if (hw
->phy_id
== IFE_E_PHY_ID
)
4771 if (hw
->phy_id
== IFE_PLUS_E_PHY_ID
)
4773 if (hw
->phy_id
== IFE_C_E_PHY_ID
)
4777 if (hw
->phy_id
== I210_I_PHY_ID
)
4781 DEBUGOUT("Invalid MAC type %d\n", hw
->mac_type
);
4782 return -E1000_ERR_CONFIG
;
4785 phy_init_status
= e1000_set_phy_type(hw
);
4787 if ((match
) && (phy_init_status
== E1000_SUCCESS
)) {
4788 DEBUGOUT("PHY ID 0x%X detected\n", hw
->phy_id
);
4791 DEBUGOUT("Invalid PHY ID 0x%X\n", hw
->phy_id
);
4792 return -E1000_ERR_PHY
;
4795 /*****************************************************************************
4796 * Set media type and TBI compatibility.
4798 * hw - Struct containing variables accessed by shared code
4799 * **************************************************************************/
4801 e1000_set_media_type(struct e1000_hw
*hw
)
4807 if (hw
->mac_type
!= e1000_82543
) {
4808 /* tbi_compatibility is only valid on 82543 */
4809 hw
->tbi_compatibility_en
= false;
4812 switch (hw
->device_id
) {
4813 case E1000_DEV_ID_82545GM_SERDES
:
4814 case E1000_DEV_ID_82546GB_SERDES
:
4815 case E1000_DEV_ID_82571EB_SERDES
:
4816 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
4817 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
4818 case E1000_DEV_ID_82572EI_SERDES
:
4819 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT
:
4820 hw
->media_type
= e1000_media_type_internal_serdes
;
4823 switch (hw
->mac_type
) {
4824 case e1000_82542_rev2_0
:
4825 case e1000_82542_rev2_1
:
4826 hw
->media_type
= e1000_media_type_fiber
;
4832 /* The STATUS_TBIMODE bit is reserved or reused
4833 * for the this device.
4835 hw
->media_type
= e1000_media_type_copper
;
4838 status
= E1000_READ_REG(hw
, STATUS
);
4839 if (status
& E1000_STATUS_TBIMODE
) {
4840 hw
->media_type
= e1000_media_type_fiber
;
4841 /* tbi_compatibility not valid on fiber */
4842 hw
->tbi_compatibility_en
= false;
4844 hw
->media_type
= e1000_media_type_copper
;
4852 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4854 * e1000_sw_init initializes the Adapter private data structure.
4855 * Fields are initialized based on PCI device information and
4856 * OS network device settings (MTU size).
4860 e1000_sw_init(struct eth_device
*nic
)
4862 struct e1000_hw
*hw
= (typeof(hw
)) nic
->priv
;
4865 /* PCI config space info */
4866 pci_read_config_word(hw
->pdev
, PCI_VENDOR_ID
, &hw
->vendor_id
);
4867 pci_read_config_word(hw
->pdev
, PCI_DEVICE_ID
, &hw
->device_id
);
4868 pci_read_config_word(hw
->pdev
, PCI_SUBSYSTEM_VENDOR_ID
,
4869 &hw
->subsystem_vendor_id
);
4870 pci_read_config_word(hw
->pdev
, PCI_SUBSYSTEM_ID
, &hw
->subsystem_id
);
4872 pci_read_config_byte(hw
->pdev
, PCI_REVISION_ID
, &hw
->revision_id
);
4873 pci_read_config_word(hw
->pdev
, PCI_COMMAND
, &hw
->pci_cmd_word
);
4875 /* identify the MAC */
4876 result
= e1000_set_mac_type(hw
);
4878 E1000_ERR(hw
->nic
, "Unknown MAC Type\n");
4882 switch (hw
->mac_type
) {
4887 case e1000_82541_rev_2
:
4888 case e1000_82547_rev_2
:
4889 hw
->phy_init_script
= 1;
4893 /* flow control settings */
4894 hw
->fc_high_water
= E1000_FC_HIGH_THRESH
;
4895 hw
->fc_low_water
= E1000_FC_LOW_THRESH
;
4896 hw
->fc_pause_time
= E1000_FC_PAUSE_TIME
;
4897 hw
->fc_send_xon
= 1;
4899 /* Media type - copper or fiber */
4900 hw
->tbi_compatibility_en
= true;
4901 e1000_set_media_type(hw
);
4903 if (hw
->mac_type
>= e1000_82543
) {
4904 uint32_t status
= E1000_READ_REG(hw
, STATUS
);
4906 if (status
& E1000_STATUS_TBIMODE
) {
4907 DEBUGOUT("fiber interface\n");
4908 hw
->media_type
= e1000_media_type_fiber
;
4910 DEBUGOUT("copper interface\n");
4911 hw
->media_type
= e1000_media_type_copper
;
4914 hw
->media_type
= e1000_media_type_fiber
;
4917 hw
->wait_autoneg_complete
= true;
4918 if (hw
->mac_type
< e1000_82543
)
4919 hw
->report_tx_early
= 0;
4921 hw
->report_tx_early
= 1;
4923 return E1000_SUCCESS
;
4927 fill_rx(struct e1000_hw
*hw
)
4929 struct e1000_rx_desc
*rd
;
4930 unsigned long flush_start
, flush_end
;
4933 rd
= rx_base
+ rx_tail
;
4934 rx_tail
= (rx_tail
+ 1) % 8;
4936 rd
->buffer_addr
= cpu_to_le64((unsigned long)packet
);
4939 * Make sure there are no stale data in WB over this area, which
4940 * might get written into the memory while the e1000 also writes
4941 * into the same memory area.
4943 invalidate_dcache_range((unsigned long)packet
,
4944 (unsigned long)packet
+ 4096);
4945 /* Dump the DMA descriptor into RAM. */
4946 flush_start
= ((unsigned long)rd
) & ~(ARCH_DMA_MINALIGN
- 1);
4947 flush_end
= flush_start
+ roundup(sizeof(*rd
), ARCH_DMA_MINALIGN
);
4948 flush_dcache_range(flush_start
, flush_end
);
4950 E1000_WRITE_REG(hw
, RDT
, rx_tail
);
4954 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4955 * @adapter: board private structure
4957 * Configure the Tx unit of the MAC after a reset.
4961 e1000_configure_tx(struct e1000_hw
*hw
)
4964 unsigned long tipg
, tarc
;
4965 uint32_t ipgr1
, ipgr2
;
4967 E1000_WRITE_REG(hw
, TDBAL
, (unsigned long)tx_base
);
4968 E1000_WRITE_REG(hw
, TDBAH
, 0);
4970 E1000_WRITE_REG(hw
, TDLEN
, 128);
4972 /* Setup the HW Tx Head and Tail descriptor pointers */
4973 E1000_WRITE_REG(hw
, TDH
, 0);
4974 E1000_WRITE_REG(hw
, TDT
, 0);
4977 /* Set the default values for the Tx Inter Packet Gap timer */
4978 if (hw
->mac_type
<= e1000_82547_rev_2
&&
4979 (hw
->media_type
== e1000_media_type_fiber
||
4980 hw
->media_type
== e1000_media_type_internal_serdes
))
4981 tipg
= DEFAULT_82543_TIPG_IPGT_FIBER
;
4983 tipg
= DEFAULT_82543_TIPG_IPGT_COPPER
;
4985 /* Set the default values for the Tx Inter Packet Gap timer */
4986 switch (hw
->mac_type
) {
4987 case e1000_82542_rev2_0
:
4988 case e1000_82542_rev2_1
:
4989 tipg
= DEFAULT_82542_TIPG_IPGT
;
4990 ipgr1
= DEFAULT_82542_TIPG_IPGR1
;
4991 ipgr2
= DEFAULT_82542_TIPG_IPGR2
;
4993 case e1000_80003es2lan
:
4994 ipgr1
= DEFAULT_82543_TIPG_IPGR1
;
4995 ipgr2
= DEFAULT_80003ES2LAN_TIPG_IPGR2
;
4998 ipgr1
= DEFAULT_82543_TIPG_IPGR1
;
4999 ipgr2
= DEFAULT_82543_TIPG_IPGR2
;
5002 tipg
|= ipgr1
<< E1000_TIPG_IPGR1_SHIFT
;
5003 tipg
|= ipgr2
<< E1000_TIPG_IPGR2_SHIFT
;
5004 E1000_WRITE_REG(hw
, TIPG
, tipg
);
5005 /* Program the Transmit Control Register */
5006 tctl
= E1000_READ_REG(hw
, TCTL
);
5007 tctl
&= ~E1000_TCTL_CT
;
5008 tctl
|= E1000_TCTL_EN
| E1000_TCTL_PSP
|
5009 (E1000_COLLISION_THRESHOLD
<< E1000_CT_SHIFT
);
5011 if (hw
->mac_type
== e1000_82571
|| hw
->mac_type
== e1000_82572
) {
5012 tarc
= E1000_READ_REG(hw
, TARC0
);
5013 /* set the speed mode bit, we'll clear it if we're not at
5014 * gigabit link later */
5015 /* git bit can be set to 1*/
5016 } else if (hw
->mac_type
== e1000_80003es2lan
) {
5017 tarc
= E1000_READ_REG(hw
, TARC0
);
5019 E1000_WRITE_REG(hw
, TARC0
, tarc
);
5020 tarc
= E1000_READ_REG(hw
, TARC1
);
5022 E1000_WRITE_REG(hw
, TARC1
, tarc
);
5026 e1000_config_collision_dist(hw
);
5027 /* Setup Transmit Descriptor Settings for eop descriptor */
5028 hw
->txd_cmd
= E1000_TXD_CMD_EOP
| E1000_TXD_CMD_IFCS
;
5030 /* Need to set up RS bit */
5031 if (hw
->mac_type
< e1000_82543
)
5032 hw
->txd_cmd
|= E1000_TXD_CMD_RPS
;
5034 hw
->txd_cmd
|= E1000_TXD_CMD_RS
;
5037 if (hw
->mac_type
== e1000_igb
) {
5038 E1000_WRITE_REG(hw
, TCTL_EXT
, 0x42 << 10);
5040 uint32_t reg_txdctl
= E1000_READ_REG(hw
, TXDCTL
);
5041 reg_txdctl
|= 1 << 25;
5042 E1000_WRITE_REG(hw
, TXDCTL
, reg_txdctl
);
5048 E1000_WRITE_REG(hw
, TCTL
, tctl
);
5054 * e1000_setup_rctl - configure the receive control register
5055 * @adapter: Board private structure
5058 e1000_setup_rctl(struct e1000_hw
*hw
)
5062 rctl
= E1000_READ_REG(hw
, RCTL
);
5064 rctl
&= ~(3 << E1000_RCTL_MO_SHIFT
);
5066 rctl
|= E1000_RCTL_EN
| E1000_RCTL_BAM
| E1000_RCTL_LBM_NO
5067 | E1000_RCTL_RDMTS_HALF
; /* |
5068 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5070 if (hw
->tbi_compatibility_on
== 1)
5071 rctl
|= E1000_RCTL_SBP
;
5073 rctl
&= ~E1000_RCTL_SBP
;
5075 rctl
&= ~(E1000_RCTL_SZ_4096
);
5076 rctl
|= E1000_RCTL_SZ_2048
;
5077 rctl
&= ~(E1000_RCTL_BSEX
| E1000_RCTL_LPE
);
5078 E1000_WRITE_REG(hw
, RCTL
, rctl
);
5082 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5083 * @adapter: board private structure
5085 * Configure the Rx unit of the MAC after a reset.
5088 e1000_configure_rx(struct e1000_hw
*hw
)
5090 unsigned long rctl
, ctrl_ext
;
5092 /* make sure receives are disabled while setting up the descriptors */
5093 rctl
= E1000_READ_REG(hw
, RCTL
);
5094 E1000_WRITE_REG(hw
, RCTL
, rctl
& ~E1000_RCTL_EN
);
5095 if (hw
->mac_type
>= e1000_82540
) {
5096 /* Set the interrupt throttling rate. Value is calculated
5097 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5098 #define MAX_INTS_PER_SEC 8000
5099 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5100 E1000_WRITE_REG(hw
, ITR
, DEFAULT_ITR
);
5103 if (hw
->mac_type
>= e1000_82571
) {
5104 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
5105 /* Reset delay timers after every interrupt */
5106 ctrl_ext
|= E1000_CTRL_EXT_INT_TIMER_CLR
;
5107 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
5108 E1000_WRITE_FLUSH(hw
);
5110 /* Setup the Base and Length of the Rx Descriptor Ring */
5111 E1000_WRITE_REG(hw
, RDBAL
, (unsigned long)rx_base
);
5112 E1000_WRITE_REG(hw
, RDBAH
, 0);
5114 E1000_WRITE_REG(hw
, RDLEN
, 128);
5116 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5117 E1000_WRITE_REG(hw
, RDH
, 0);
5118 E1000_WRITE_REG(hw
, RDT
, 0);
5119 /* Enable Receives */
5121 if (hw
->mac_type
== e1000_igb
) {
5123 uint32_t reg_rxdctl
= E1000_READ_REG(hw
, RXDCTL
);
5124 reg_rxdctl
|= 1 << 25;
5125 E1000_WRITE_REG(hw
, RXDCTL
, reg_rxdctl
);
5129 E1000_WRITE_REG(hw
, RCTL
, rctl
);
5134 /**************************************************************************
5135 POLL - Wait for a frame
5136 ***************************************************************************/
5138 e1000_poll(struct eth_device
*nic
)
5140 struct e1000_hw
*hw
= nic
->priv
;
5141 struct e1000_rx_desc
*rd
;
5142 unsigned long inval_start
, inval_end
;
5145 /* return true if there's an ethernet packet ready to read */
5146 rd
= rx_base
+ rx_last
;
5148 /* Re-load the descriptor from RAM. */
5149 inval_start
= ((unsigned long)rd
) & ~(ARCH_DMA_MINALIGN
- 1);
5150 inval_end
= inval_start
+ roundup(sizeof(*rd
), ARCH_DMA_MINALIGN
);
5151 invalidate_dcache_range(inval_start
, inval_end
);
5153 if (!(le32_to_cpu(rd
->status
)) & E1000_RXD_STAT_DD
)
5155 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5156 /* Packet received, make sure the data are re-loaded from RAM. */
5157 len
= le32_to_cpu(rd
->length
);
5158 invalidate_dcache_range((unsigned long)packet
,
5159 (unsigned long)packet
+
5160 roundup(len
, ARCH_DMA_MINALIGN
));
5161 NetReceive((uchar
*)packet
, len
);
5166 /**************************************************************************
5167 TRANSMIT - Transmit a frame
5168 ***************************************************************************/
5169 static int e1000_transmit(struct eth_device
*nic
, void *txpacket
, int length
)
5171 void *nv_packet
= (void *)txpacket
;
5172 struct e1000_hw
*hw
= nic
->priv
;
5173 struct e1000_tx_desc
*txp
;
5175 unsigned long flush_start
, flush_end
;
5177 txp
= tx_base
+ tx_tail
;
5178 tx_tail
= (tx_tail
+ 1) % 8;
5180 txp
->buffer_addr
= cpu_to_le64(virt_to_bus(hw
->pdev
, nv_packet
));
5181 txp
->lower
.data
= cpu_to_le32(hw
->txd_cmd
| length
);
5182 txp
->upper
.data
= 0;
5184 /* Dump the packet into RAM so e1000 can pick them. */
5185 flush_dcache_range((unsigned long)nv_packet
,
5186 (unsigned long)nv_packet
+
5187 roundup(length
, ARCH_DMA_MINALIGN
));
5188 /* Dump the descriptor into RAM as well. */
5189 flush_start
= ((unsigned long)txp
) & ~(ARCH_DMA_MINALIGN
- 1);
5190 flush_end
= flush_start
+ roundup(sizeof(*txp
), ARCH_DMA_MINALIGN
);
5191 flush_dcache_range(flush_start
, flush_end
);
5193 E1000_WRITE_REG(hw
, TDT
, tx_tail
);
5195 E1000_WRITE_FLUSH(hw
);
5197 invalidate_dcache_range(flush_start
, flush_end
);
5198 if (le32_to_cpu(txp
->upper
.data
) & E1000_TXD_STAT_DD
)
5200 if (i
++ > TOUT_LOOP
) {
5201 DEBUGOUT("e1000: tx timeout\n");
5204 udelay(10); /* give the nic a chance to write to the register */
5211 e1000_reset(struct eth_device
*nic
)
5213 struct e1000_hw
*hw
= nic
->priv
;
5216 if (hw
->mac_type
>= e1000_82544
) {
5217 E1000_WRITE_REG(hw
, WUC
, 0);
5219 return e1000_init_hw(nic
);
5222 /**************************************************************************
5223 DISABLE - Turn off ethernet interface
5224 ***************************************************************************/
5226 e1000_disable(struct eth_device
*nic
)
5228 struct e1000_hw
*hw
= nic
->priv
;
5230 /* Turn off the ethernet interface */
5231 E1000_WRITE_REG(hw
, RCTL
, 0);
5232 E1000_WRITE_REG(hw
, TCTL
, 0);
5234 /* Clear the transmit ring */
5235 E1000_WRITE_REG(hw
, TDH
, 0);
5236 E1000_WRITE_REG(hw
, TDT
, 0);
5238 /* Clear the receive ring */
5239 E1000_WRITE_REG(hw
, RDH
, 0);
5240 E1000_WRITE_REG(hw
, RDT
, 0);
5242 /* put the card in its initial state */
5244 E1000_WRITE_REG(hw
, CTRL
, E1000_CTRL_RST
);
5250 /**************************************************************************
5251 INIT - set up ethernet interface(s)
5252 ***************************************************************************/
5254 e1000_init(struct eth_device
*nic
, bd_t
* bis
)
5256 struct e1000_hw
*hw
= nic
->priv
;
5259 ret_val
= e1000_reset(nic
);
5261 if ((ret_val
== -E1000_ERR_NOLINK
) ||
5262 (ret_val
== -E1000_ERR_TIMEOUT
)) {
5263 E1000_ERR(hw
->nic
, "Valid Link not detected\n");
5265 E1000_ERR(hw
->nic
, "Hardware Initialization Failed\n");
5269 e1000_configure_tx(hw
);
5270 e1000_setup_rctl(hw
);
5271 e1000_configure_rx(hw
);
5275 /******************************************************************************
5276 * Gets the current PCI bus type of hardware
5278 * hw - Struct containing variables accessed by shared code
5279 *****************************************************************************/
5280 void e1000_get_bus_type(struct e1000_hw
*hw
)
5284 switch (hw
->mac_type
) {
5285 case e1000_82542_rev2_0
:
5286 case e1000_82542_rev2_1
:
5287 hw
->bus_type
= e1000_bus_type_pci
;
5293 case e1000_80003es2lan
:
5296 hw
->bus_type
= e1000_bus_type_pci_express
;
5299 status
= E1000_READ_REG(hw
, STATUS
);
5300 hw
->bus_type
= (status
& E1000_STATUS_PCIX_MODE
) ?
5301 e1000_bus_type_pcix
: e1000_bus_type_pci
;
5306 /* A list of all registered e1000 devices */
5307 static LIST_HEAD(e1000_hw_list
);
5309 /**************************************************************************
5310 PROBE - Look for an adapter, this routine's visible to the outside
5311 You should omit the last argument struct pci_device * for a non-PCI NIC
5312 ***************************************************************************/
5314 e1000_initialize(bd_t
* bis
)
5321 /* Find and probe all the matching PCI devices */
5322 for (i
= 0; (devno
= pci_find_devices(e1000_supported
, i
)) >= 0; i
++) {
5326 * These will never get freed due to errors, this allows us to
5327 * perform SPI EEPROM programming from U-boot, for example.
5329 struct eth_device
*nic
= malloc(sizeof(*nic
));
5330 struct e1000_hw
*hw
= malloc(sizeof(*hw
));
5332 printf("e1000#%u: Out of Memory!\n", i
);
5338 /* Make sure all of the fields are initially zeroed */
5339 memset(nic
, 0, sizeof(*nic
));
5340 memset(hw
, 0, sizeof(*hw
));
5342 /* Assign the passed-in values */
5348 /* Generate a card name */
5349 sprintf(nic
->name
, "e1000#%u", hw
->cardnum
);
5351 /* Print a debug message with the IO base address */
5352 pci_read_config_dword(devno
, PCI_BASE_ADDRESS_0
, &val
);
5353 E1000_DBG(nic
, "iobase 0x%08x\n", val
& 0xfffffff0);
5355 /* Try to enable I/O accesses and bus-mastering */
5356 val
= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
5357 pci_write_config_dword(devno
, PCI_COMMAND
, val
);
5359 /* Make sure it worked */
5360 pci_read_config_dword(devno
, PCI_COMMAND
, &val
);
5361 if (!(val
& PCI_COMMAND_MEMORY
)) {
5362 E1000_ERR(nic
, "Can't enable I/O memory\n");
5365 if (!(val
& PCI_COMMAND_MASTER
)) {
5366 E1000_ERR(nic
, "Can't enable bus-mastering\n");
5370 /* Are these variables needed? */
5371 hw
->fc
= e1000_fc_default
;
5372 hw
->original_fc
= e1000_fc_default
;
5373 hw
->autoneg_failed
= 0;
5375 hw
->get_link_status
= true;
5376 #ifndef CONFIG_E1000_NO_NVM
5377 hw
->eeprom_semaphore_present
= true;
5379 hw
->hw_addr
= pci_map_bar(devno
, PCI_BASE_ADDRESS_0
,
5381 hw
->mac_type
= e1000_undefined
;
5383 /* MAC and Phy settings */
5384 if (e1000_sw_init(nic
) < 0) {
5385 E1000_ERR(nic
, "Software init failed\n");
5388 if (e1000_check_phy_reset_block(hw
))
5389 E1000_ERR(nic
, "PHY Reset is blocked!\n");
5391 /* Basic init was OK, reset the hardware and allow SPI access */
5393 list_add_tail(&hw
->list_node
, &e1000_hw_list
);
5395 #ifndef CONFIG_E1000_NO_NVM
5396 /* Validate the EEPROM and get chipset information */
5397 #if !defined(CONFIG_MVBC_1G)
5398 if (e1000_init_eeprom_params(hw
)) {
5399 E1000_ERR(nic
, "EEPROM is invalid!\n");
5402 if ((E1000_READ_REG(hw
, I210_EECD
) & E1000_EECD_FLUPD
) &&
5403 e1000_validate_eeprom_checksum(hw
))
5406 e1000_read_mac_addr(nic
);
5408 e1000_get_bus_type(hw
);
5410 #ifndef CONFIG_E1000_NO_NVM
5411 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5412 nic
->enetaddr
[0], nic
->enetaddr
[1], nic
->enetaddr
[2],
5413 nic
->enetaddr
[3], nic
->enetaddr
[4], nic
->enetaddr
[5]);
5415 memset(nic
->enetaddr
, 0, 6);
5416 printf("e1000: no NVM\n");
5419 /* Set up the function pointers and register the device */
5420 nic
->init
= e1000_init
;
5421 nic
->recv
= e1000_poll
;
5422 nic
->send
= e1000_transmit
;
5423 nic
->halt
= e1000_disable
;
5430 struct e1000_hw
*e1000_find_card(unsigned int cardnum
)
5432 struct e1000_hw
*hw
;
5434 list_for_each_entry(hw
, &e1000_hw_list
, list_node
)
5435 if (hw
->cardnum
== cardnum
)
5441 #ifdef CONFIG_CMD_E1000
5442 static int do_e1000(cmd_tbl_t
*cmdtp
, int flag
,
5443 int argc
, char * const argv
[])
5445 struct e1000_hw
*hw
;
5452 /* Make sure we can find the requested e1000 card */
5453 hw
= e1000_find_card(simple_strtoul(argv
[1], NULL
, 10));
5455 printf("e1000: ERROR: No such device: e1000#%s\n", argv
[1]);
5459 if (!strcmp(argv
[2], "print-mac-address")) {
5460 unsigned char *mac
= hw
->nic
->enetaddr
;
5461 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5462 mac
[0], mac
[1], mac
[2], mac
[3], mac
[4], mac
[5]);
5466 #ifdef CONFIG_E1000_SPI
5467 /* Handle the "SPI" subcommand */
5468 if (!strcmp(argv
[2], "spi"))
5469 return do_e1000_spi(cmdtp
, hw
, argc
- 3, argv
+ 3);
5477 e1000
, 7, 0, do_e1000
,
5478 "Intel e1000 controller management",
5479 /* */"<card#> print-mac-address\n"
5480 #ifdef CONFIG_E1000_SPI
5481 "e1000 <card#> spi show [<offset> [<length>]]\n"
5482 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5483 "e1000 <card#> spi program <addr> <offset> <length>\n"
5484 "e1000 <card#> spi checksum [update]\n"
5486 " - Manage the Intel E1000 PCI device"
5488 #endif /* not CONFIG_CMD_E1000 */