drivers/net/eepro100.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <malloc.h>
  26 #include <net.h>
  27 #include <netdev.h>
  28 #include <asm/io.h>
  29 #include <pci.h>
  30 #include <miiphy.h>
  31
  32 #undef DEBUG
  33
  34         /* Ethernet chip registers.
  35          */
  36 #define SCBStatus               0       /* Rx/Command Unit Status *Word* */
  37 #define SCBIntAckByte           1       /* Rx/Command Unit STAT/ACK byte */
  38 #define SCBCmd                  2       /* Rx/Command Unit Command *Word* */
  39 #define SCBIntrCtlByte          3       /* Rx/Command Unit Intr.Control Byte */
  40 #define SCBPointer              4       /* General purpose pointer. */
  41 #define SCBPort                 8       /* Misc. commands and operands. */
  42 #define SCBflash                12      /* Flash memory control. */
  43 #define SCBeeprom               14      /* EEPROM memory control. */
  44 #define SCBCtrlMDI              16      /* MDI interface control. */
  45 #define SCBEarlyRx              20      /* Early receive byte count. */
  46 #define SCBGenControl           28      /* 82559 General Control Register */
  47 #define SCBGenStatus            29      /* 82559 General Status register */
  48
  49         /* 82559 SCB status word defnitions
  50          */
  51 #define SCB_STATUS_CX           0x8000  /* CU finished command (transmit) */
  52 #define SCB_STATUS_FR           0x4000  /* frame received */
  53 #define SCB_STATUS_CNA          0x2000  /* CU left active state */
  54 #define SCB_STATUS_RNR          0x1000  /* receiver left ready state */
  55 #define SCB_STATUS_MDI          0x0800  /* MDI read/write cycle done */
  56 #define SCB_STATUS_SWI          0x0400  /* software generated interrupt */
  57 #define SCB_STATUS_FCP          0x0100  /* flow control pause interrupt */
  58
  59 #define SCB_INTACK_MASK         0xFD00  /* all the above */
  60
  61 #define SCB_INTACK_TX           (SCB_STATUS_CX | SCB_STATUS_CNA)
  62 #define SCB_INTACK_RX           (SCB_STATUS_FR | SCB_STATUS_RNR)
  63
  64         /* System control block commands
  65          */
  66 /* CU Commands */
  67 #define CU_NOP                  0x0000
  68 #define CU_START                0x0010
  69 #define CU_RESUME               0x0020
  70 #define CU_STATSADDR            0x0040  /* Load Dump Statistics ctrs addr */
  71 #define CU_SHOWSTATS            0x0050  /* Dump statistics counters. */
  72 #define CU_ADDR_LOAD            0x0060  /* Base address to add to CU commands */
  73 #define CU_DUMPSTATS            0x0070  /* Dump then reset stats counters. */
  74
  75 /* RUC Commands */
  76 #define RUC_NOP                 0x0000
  77 #define RUC_START               0x0001
  78 #define RUC_RESUME              0x0002
  79 #define RUC_ABORT               0x0004
  80 #define RUC_ADDR_LOAD           0x0006  /* (seems not to clear on acceptance) */
  81 #define RUC_RESUMENR            0x0007
  82
  83 #define CU_CMD_MASK             0x00f0
  84 #define RU_CMD_MASK             0x0007
  85
  86 #define SCB_M                   0x0100  /* 0 = enable interrupt, 1 = disable */
  87 #define SCB_SWI                 0x0200  /* 1 - cause device to interrupt */
  88
  89 #define CU_STATUS_MASK          0x00C0
  90 #define RU_STATUS_MASK          0x003C
  91
  92 #define RU_STATUS_IDLE          (0<<2)
  93 #define RU_STATUS_SUS           (1<<2)
  94 #define RU_STATUS_NORES         (2<<2)
  95 #define RU_STATUS_READY         (4<<2)
  96 #define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))
  97 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
  98 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
  99
 100         /* 82559 Port interface commands.
 101          */
 102 #define I82559_RESET            0x00000000      /* Software reset */
 103 #define I82559_SELFTEST         0x00000001      /* 82559 Selftest command */
 104 #define I82559_SELECTIVE_RESET  0x00000002
 105 #define I82559_DUMP             0x00000003
 106 #define I82559_DUMP_WAKEUP      0x00000007
 107
 108         /* 82559 Eeprom interface.
 109          */
 110 #define EE_SHIFT_CLK            0x01    /* EEPROM shift clock. */
 111 #define EE_CS                   0x02    /* EEPROM chip select. */
 112 #define EE_DATA_WRITE           0x04    /* EEPROM chip data in. */
 113 #define EE_WRITE_0              0x01
 114 #define EE_WRITE_1              0x05
 115 #define EE_DATA_READ            0x08    /* EEPROM chip data out. */
 116 #define EE_ENB                  (0x4800 | EE_CS)
 117 #define EE_CMD_BITS             3
 118 #define EE_DATA_BITS            16
 119
 120         /* The EEPROM commands include the alway-set leading bit.
 121          */
 122 #define EE_EWENB_CMD            (4 << addr_len)
 123 #define EE_WRITE_CMD            (5 << addr_len)
 124 #define EE_READ_CMD             (6 << addr_len)
 125 #define EE_ERASE_CMD            (7 << addr_len)
 126
 127         /* Receive frame descriptors.
 128          */
 129 struct RxFD {
 130         volatile u16 status;
 131         volatile u16 control;
 132         volatile u32 link;              /* struct RxFD * */
 133         volatile u32 rx_buf_addr;       /* void * */
 134         volatile u32 count;
 135
 136         volatile u8 data[PKTSIZE_ALIGN];
 137 };
 138
 139 #define RFD_STATUS_C            0x8000  /* completion of received frame */
 140 #define RFD_STATUS_OK           0x2000  /* frame received with no errors */
 141
 142 #define RFD_CONTROL_EL          0x8000  /* 1=last RFD in RFA */
 143 #define RFD_CONTROL_S           0x4000  /* 1=suspend RU after receiving frame */
 144 #define RFD_CONTROL_H           0x0010  /* 1=RFD is a header RFD */
 145 #define RFD_CONTROL_SF          0x0008  /* 0=simplified, 1=flexible mode */
 146
 147 #define RFD_COUNT_MASK          0x3fff
 148 #define RFD_COUNT_F             0x4000
 149 #define RFD_COUNT_EOF           0x8000
 150
 151 #define RFD_RX_CRC              0x0800  /* crc error */
 152 #define RFD_RX_ALIGNMENT        0x0400  /* alignment error */
 153 #define RFD_RX_RESOURCE         0x0200  /* out of space, no resources */
 154 #define RFD_RX_DMA_OVER         0x0100  /* DMA overrun */
 155 #define RFD_RX_SHORT            0x0080  /* short frame error */
 156 #define RFD_RX_LENGTH           0x0020
 157 #define RFD_RX_ERROR            0x0010  /* receive error */
 158 #define RFD_RX_NO_ADR_MATCH     0x0004  /* no address match */
 159 #define RFD_RX_IA_MATCH         0x0002  /* individual address does not match */
 160 #define RFD_RX_TCO              0x0001  /* TCO indication */
 161
 162         /* Transmit frame descriptors
 163          */
 164 struct TxFD {                           /* Transmit frame descriptor set. */
 165         volatile u16 status;
 166         volatile u16 command;
 167         volatile u32 link;              /* void * */
 168         volatile u32 tx_desc_addr;      /* Always points to the tx_buf_addr element. */
 169         volatile s32 count;
 170
 171         volatile u32 tx_buf_addr0;      /* void *, frame to be transmitted.  */
 172         volatile s32 tx_buf_size0;      /* Length of Tx frame. */
 173         volatile u32 tx_buf_addr1;      /* void *, frame to be transmitted.  */
 174         volatile s32 tx_buf_size1;      /* Length of Tx frame. */
 175 };
 176
 177 #define TxCB_CMD_TRANSMIT       0x0004  /* transmit command */
 178 #define TxCB_CMD_SF             0x0008  /* 0=simplified, 1=flexible mode */
 179 #define TxCB_CMD_NC             0x0010  /* 0=CRC insert by controller */
 180 #define TxCB_CMD_I              0x2000  /* generate interrupt on completion */
 181 #define TxCB_CMD_S              0x4000  /* suspend on completion */
 182 #define TxCB_CMD_EL             0x8000  /* last command block in CBL */
 183
 184 #define TxCB_COUNT_MASK         0x3fff
 185 #define TxCB_COUNT_EOF          0x8000
 186
 187         /* The Speedo3 Rx and Tx frame/buffer descriptors.
 188          */
 189 struct descriptor {                     /* A generic descriptor. */
 190         volatile u16 status;
 191         volatile u16 command;
 192         volatile u32 link;              /* struct descriptor *  */
 193
 194         unsigned char params[0];
 195 };
 196
 197 #define CONFIG_SYS_CMD_EL               0x8000
 198 #define CONFIG_SYS_CMD_SUSPEND          0x4000
 199 #define CONFIG_SYS_CMD_INT              0x2000
 200 #define CONFIG_SYS_CMD_IAS              0x0001  /* individual address setup */
 201 #define CONFIG_SYS_CMD_CONFIGURE        0x0002  /* configure */
 202
 203 #define CONFIG_SYS_STATUS_C             0x8000
 204 #define CONFIG_SYS_STATUS_OK            0x2000
 205
 206         /* Misc.
 207          */
 208 #define NUM_RX_DESC             PKTBUFSRX
 209 #define NUM_TX_DESC             1       /* Number of TX descriptors   */
 210
 211 #define TOUT_LOOP               1000000
 212
 213 #define ETH_ALEN                6
 214
 215 static struct RxFD rx_ring[NUM_RX_DESC];        /* RX descriptor ring         */
 216 static struct TxFD tx_ring[NUM_TX_DESC];        /* TX descriptor ring         */
 217 static int rx_next;                     /* RX descriptor ring pointer */
 218 static int tx_next;                     /* TX descriptor ring pointer */
 219 static int tx_threshold;
 220
 221 /*
 222  * The parameters for a CmdConfigure operation.
 223  * There are so many options that it would be difficult to document
 224  * each bit. We mostly use the default or recommended settings.
 225  */
 226 static const char i82557_config_cmd[] = {
 227         22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1,    /* 1=Use MII  0=Use AUI */
 228         0, 0x2E, 0, 0x60, 0,
 229         0xf2, 0x48, 0, 0x40, 0xf2, 0x80,        /* 0x40=Force full-duplex */
 230         0x3f, 0x05,
 231 };
 232 static const char i82558_config_cmd[] = {
 233         22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1,    /* 1=Use MII  0=Use AUI */
 234         0, 0x2E, 0, 0x60, 0x08, 0x88,
 235         0x68, 0, 0x40, 0xf2, 0x84,              /* Disable FC */
 236         0x31, 0x05,
 237 };
 238
 239 static void init_rx_ring (struct eth_device *dev);
 240 static void purge_tx_ring (struct eth_device *dev);
 241
 242 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
 243
 244 static int eepro100_init (struct eth_device *dev, bd_t * bis);
 245 static int eepro100_send (struct eth_device *dev, volatile void *packet,
 246                                                   int length);
 247 static int eepro100_recv (struct eth_device *dev);
 248 static void eepro100_halt (struct eth_device *dev);
 249
 250 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
 251 #define bus_to_phys(a) (a)
 252 #define phys_to_bus(a) (a)
 253 #else
 254 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)dev->priv, a)
 255 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)dev->priv, a)
 256 #endif
 257
 258 static inline int INW (struct eth_device *dev, u_long addr)
 259 {
 260         return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
 261 }
 262
 263 static inline void OUTW (struct eth_device *dev, int command, u_long addr)
 264 {
 265         *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
 266 }
 267
 268 static inline void OUTL (struct eth_device *dev, int command, u_long addr)
 269 {
 270         *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
 271 }
 272
 273 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 274 static inline int INL (struct eth_device *dev, u_long addr)
 275 {
 276         return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
 277 }
 278
 279 static int get_phyreg (struct eth_device *dev, unsigned char addr,
 280                 unsigned char reg, unsigned short *value)
 281 {
 282         int cmd;
 283         int timeout = 50;
 284
 285         /* read requested data */
 286         cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
 287         OUTL (dev, cmd, SCBCtrlMDI);
 288
 289         do {
 290                 udelay(1000);
 291                 cmd = INL (dev, SCBCtrlMDI);
 292         } while (!(cmd & (1 << 28)) && (--timeout));
 293
 294         if (timeout == 0)
 295                 return -1;
 296
 297         *value = (unsigned short) (cmd & 0xffff);
 298
 299         return 0;
 300 }
 301
 302 static int set_phyreg (struct eth_device *dev, unsigned char addr,
 303                 unsigned char reg, unsigned short value)
 304 {
 305         int cmd;
 306         int timeout = 50;
 307
 308         /* write requested data */
 309         cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
 310         OUTL (dev, cmd | value, SCBCtrlMDI);
 311
 312         while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
 313                 udelay(1000);
 314
 315         if (timeout == 0)
 316                 return -1;
 317
 318         return 0;
 319 }
 320
 321 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
 322  * Do this by checking model value field from ID2 register.
 323  */
 324 static struct eth_device* verify_phyaddr (const char *devname,
 325                                                 unsigned char addr)
 326 {
 327         struct eth_device *dev;
 328         unsigned short value;
 329         unsigned char model;
 330
 331         dev = eth_get_dev_by_name(devname);
 332         if (dev == NULL) {
 333                 printf("%s: no such device\n", devname);
 334                 return NULL;
 335         }
 336
 337         /* read id2 register */
 338         if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
 339                 printf("%s: mii read timeout!\n", devname);
 340                 return NULL;
 341         }
 342
 343         /* get model */
 344         model = (unsigned char)((value >> 4) & 0x003f);
 345
 346         if (model == 0) {
 347                 printf("%s: no PHY at address %d\n", devname, addr);
 348                 return NULL;
 349         }
 350
 351         return dev;
 352 }
 353
 354 static int eepro100_miiphy_read(const char *devname, unsigned char addr,
 355                 unsigned char reg, unsigned short *value)
 356 {
 357         struct eth_device *dev;
 358
 359         dev = verify_phyaddr(devname, addr);
 360         if (dev == NULL)
 361                 return -1;
 362
 363         if (get_phyreg(dev, addr, reg, value) != 0) {
 364                 printf("%s: mii read timeout!\n", devname);
 365                 return -1;
 366         }
 367
 368         return 0;
 369 }
 370
 371 static int eepro100_miiphy_write(const char *devname, unsigned char addr,
 372                 unsigned char reg, unsigned short value)
 373 {
 374         struct eth_device *dev;
 375
 376         dev = verify_phyaddr(devname, addr);
 377         if (dev == NULL)
 378                 return -1;
 379
 380         if (set_phyreg(dev, addr, reg, value) != 0) {
 381                 printf("%s: mii write timeout!\n", devname);
 382                 return -1;
 383         }
 384
 385         return 0;
 386 }
 387
 388 #endif
 389
 390 /* Wait for the chip get the command.
 391 */
 392 static int wait_for_eepro100 (struct eth_device *dev)
 393 {
 394         int i;
 395
 396         for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
 397                 if (i >= TOUT_LOOP) {
 398                         return 0;
 399                 }
 400         }
 401
 402         return 1;
 403 }
 404
 405 static struct pci_device_id supported[] = {
 406         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
 407         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
 408         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
 409         {}
 410 };
 411
 412 int eepro100_initialize (bd_t * bis)
 413 {
 414         pci_dev_t devno;
 415         int card_number = 0;
 416         struct eth_device *dev;
 417         u32 iobase, status;
 418         int idx = 0;
 419
 420         while (1) {
 421                 /* Find PCI device
 422                  */
 423                 if ((devno = pci_find_devices (supported, idx++)) < 0) {
 424                         break;
 425                 }
 426
 427                 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
 428                 iobase &= ~0xf;
 429
 430 #ifdef DEBUG
 431                 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
 432                                 iobase);
 433 #endif
 434
 435                 pci_write_config_dword (devno,
 436                                         PCI_COMMAND,
 437                                         PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 438
 439                 /* Check if I/O accesses and Bus Mastering are enabled.
 440                  */
 441                 pci_read_config_dword (devno, PCI_COMMAND, &status);
 442                 if (!(status & PCI_COMMAND_MEMORY)) {
 443                         printf ("Error: Can not enable MEM access.\n");
 444                         continue;
 445                 }
 446
 447                 if (!(status & PCI_COMMAND_MASTER)) {
 448                         printf ("Error: Can not enable Bus Mastering.\n");
 449                         continue;
 450                 }
 451
 452                 dev = (struct eth_device *) malloc (sizeof *dev);
 453
 454                 sprintf (dev->name, "i82559#%d", card_number);
 455                 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
 456                 dev->iobase = bus_to_phys (iobase);
 457                 dev->init = eepro100_init;
 458                 dev->halt = eepro100_halt;
 459                 dev->send = eepro100_send;
 460                 dev->recv = eepro100_recv;
 461
 462                 eth_register (dev);
 463
 464 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
 465                 /* register mii command access routines */
 466                 miiphy_register(dev->name,
 467                                 eepro100_miiphy_read, eepro100_miiphy_write);
 468 #endif
 469
 470                 card_number++;
 471
 472                 /* Set the latency timer for value.
 473                  */
 474                 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
 475
 476                 udelay (10 * 1000);
 477
 478                 read_hw_addr (dev, bis);
 479         }
 480
 481         return card_number;
 482 }
 483
 484
 485 static int eepro100_init (struct eth_device *dev, bd_t * bis)
 486 {
 487         int i, status = -1;
 488         int tx_cur;
 489         struct descriptor *ias_cmd, *cfg_cmd;
 490
 491         /* Reset the ethernet controller
 492          */
 493         OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
 494         udelay (20);
 495
 496         OUTL (dev, I82559_RESET, SCBPort);
 497         udelay (20);
 498
 499         if (!wait_for_eepro100 (dev)) {
 500                 printf ("Error: Can not reset ethernet controller.\n");
 501                 goto Done;
 502         }
 503         OUTL (dev, 0, SCBPointer);
 504         OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
 505
 506         if (!wait_for_eepro100 (dev)) {
 507                 printf ("Error: Can not reset ethernet controller.\n");
 508                 goto Done;
 509         }
 510         OUTL (dev, 0, SCBPointer);
 511         OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
 512
 513         /* Initialize Rx and Tx rings.
 514          */
 515         init_rx_ring (dev);
 516         purge_tx_ring (dev);
 517
 518         /* Tell the adapter where the RX ring is located.
 519          */
 520         if (!wait_for_eepro100 (dev)) {
 521                 printf ("Error: Can not reset ethernet controller.\n");
 522                 goto Done;
 523         }
 524
 525         OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
 526         OUTW (dev, SCB_M | RUC_START, SCBCmd);
 527
 528         /* Send the Configure frame */
 529         tx_cur = tx_next;
 530         tx_next = ((tx_next + 1) % NUM_TX_DESC);
 531
 532         cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
 533         cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
 534         cfg_cmd->status = 0;
 535         cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 536
 537         memcpy (cfg_cmd->params, i82558_config_cmd,
 538                         sizeof (i82558_config_cmd));
 539
 540         if (!wait_for_eepro100 (dev)) {
 541                 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
 542                 goto Done;
 543         }
 544
 545         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 546         OUTW (dev, SCB_M | CU_START, SCBCmd);
 547
 548         for (i = 0;
 549              !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 550              i++) {
 551                 if (i >= TOUT_LOOP) {
 552                         printf ("%s: Tx error buffer not ready\n", dev->name);
 553                         goto Done;
 554                 }
 555         }
 556
 557         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 558                 printf ("TX error status = 0x%08X\n",
 559                         le16_to_cpu (tx_ring[tx_cur].status));
 560                 goto Done;
 561         }
 562
 563         /* Send the Individual Address Setup frame
 564          */
 565         tx_cur = tx_next;
 566         tx_next = ((tx_next + 1) % NUM_TX_DESC);
 567
 568         ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
 569         ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
 570         ias_cmd->status = 0;
 571         ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 572
 573         memcpy (ias_cmd->params, dev->enetaddr, 6);
 574
 575         /* Tell the adapter where the TX ring is located.
 576          */
 577         if (!wait_for_eepro100 (dev)) {
 578                 printf ("Error: Can not reset ethernet controller.\n");
 579                 goto Done;
 580         }
 581
 582         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 583         OUTW (dev, SCB_M | CU_START, SCBCmd);
 584
 585         for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 586                  i++) {
 587                 if (i >= TOUT_LOOP) {
 588                         printf ("%s: Tx error buffer not ready\n",
 589                                 dev->name);
 590                         goto Done;
 591                 }
 592         }
 593
 594         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 595                 printf ("TX error status = 0x%08X\n",
 596                         le16_to_cpu (tx_ring[tx_cur].status));
 597                 goto Done;
 598         }
 599
 600         status = 0;
 601
 602   Done:
 603         return status;
 604 }
 605
 606 static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
 607 {
 608         int i, status = -1;
 609         int tx_cur;
 610
 611         if (length <= 0) {
 612                 printf ("%s: bad packet size: %d\n", dev->name, length);
 613                 goto Done;
 614         }
 615
 616         tx_cur = tx_next;
 617         tx_next = (tx_next + 1) % NUM_TX_DESC;
 618
 619         tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
 620                                                 TxCB_CMD_SF     |
 621                                                 TxCB_CMD_S      |
 622                                                 TxCB_CMD_EL );
 623         tx_ring[tx_cur].status = 0;
 624         tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
 625         tx_ring[tx_cur].link =
 626                 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
 627         tx_ring[tx_cur].tx_desc_addr =
 628                 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
 629         tx_ring[tx_cur].tx_buf_addr0 =
 630                 cpu_to_le32 (phys_to_bus ((u_long) packet));
 631         tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
 632
 633         if (!wait_for_eepro100 (dev)) {
 634                 printf ("%s: Tx error ethernet controller not ready.\n",
 635                                 dev->name);
 636                 goto Done;
 637         }
 638
 639         /* Send the packet.
 640          */
 641         OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
 642         OUTW (dev, SCB_M | CU_START, SCBCmd);
 643
 644         for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
 645                  i++) {
 646                 if (i >= TOUT_LOOP) {
 647                         printf ("%s: Tx error buffer not ready\n", dev->name);
 648                         goto Done;
 649                 }
 650         }
 651
 652         if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
 653                 printf ("TX error status = 0x%08X\n",
 654                         le16_to_cpu (tx_ring[tx_cur].status));
 655                 goto Done;
 656         }
 657
 658         status = length;
 659
 660   Done:
 661         return status;
 662 }
 663
 664 static int eepro100_recv (struct eth_device *dev)
 665 {
 666         u16 status, stat;
 667         int rx_prev, length = 0;
 668
 669         stat = INW (dev, SCBStatus);
 670         OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
 671
 672         for (;;) {
 673                 status = le16_to_cpu (rx_ring[rx_next].status);
 674
 675                 if (!(status & RFD_STATUS_C)) {
 676                         break;
 677                 }
 678
 679                 /* Valid frame status.
 680                  */
 681                 if ((status & RFD_STATUS_OK)) {
 682                         /* A valid frame received.
 683                          */
 684                         length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
 685
 686                         /* Pass the packet up to the protocol
 687                          * layers.
 688                          */
 689                         NetReceive (rx_ring[rx_next].data, length);
 690                 } else {
 691                         /* There was an error.
 692                          */
 693                         printf ("RX error status = 0x%08X\n", status);
 694                 }
 695
 696                 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
 697                 rx_ring[rx_next].status = 0;
 698                 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
 699
 700                 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
 701                 rx_ring[rx_prev].control = 0;
 702
 703                 /* Update entry information.
 704                  */
 705                 rx_next = (rx_next + 1) % NUM_RX_DESC;
 706         }
 707
 708         if (stat & SCB_STATUS_RNR) {
 709
 710                 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
 711
 712                 /* Reinitialize Rx ring.
 713                  */
 714                 init_rx_ring (dev);
 715
 716                 if (!wait_for_eepro100 (dev)) {
 717                         printf ("Error: Can not restart ethernet controller.\n");
 718                         goto Done;
 719                 }
 720
 721                 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
 722                 OUTW (dev, SCB_M | RUC_START, SCBCmd);
 723         }
 724
 725   Done:
 726         return length;
 727 }
 728
 729 static void eepro100_halt (struct eth_device *dev)
 730 {
 731         /* Reset the ethernet controller
 732          */
 733         OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
 734         udelay (20);
 735
 736         OUTL (dev, I82559_RESET, SCBPort);
 737         udelay (20);
 738
 739         if (!wait_for_eepro100 (dev)) {
 740                 printf ("Error: Can not reset ethernet controller.\n");
 741                 goto Done;
 742         }
 743         OUTL (dev, 0, SCBPointer);
 744         OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
 745
 746         if (!wait_for_eepro100 (dev)) {
 747                 printf ("Error: Can not reset ethernet controller.\n");
 748                 goto Done;
 749         }
 750         OUTL (dev, 0, SCBPointer);
 751         OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
 752
 753   Done:
 754         return;
 755 }
 756
 757         /* SROM Read.
 758          */
 759 static int read_eeprom (struct eth_device *dev, int location, int addr_len)
 760 {
 761         unsigned short retval = 0;
 762         int read_cmd = location | EE_READ_CMD;
 763         int i;
 764
 765         OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
 766         OUTW (dev, EE_ENB, SCBeeprom);
 767
 768         /* Shift the read command bits out. */
 769         for (i = 12; i >= 0; i--) {
 770                 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 771
 772                 OUTW (dev, EE_ENB | dataval, SCBeeprom);
 773                 udelay (1);
 774                 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 775                 udelay (1);
 776         }
 777         OUTW (dev, EE_ENB, SCBeeprom);
 778
 779         for (i = 15; i >= 0; i--) {
 780                 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
 781                 udelay (1);
 782                 retval = (retval << 1) |
 783                                 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
 784                 OUTW (dev, EE_ENB, SCBeeprom);
 785                 udelay (1);
 786         }
 787
 788         /* Terminate the EEPROM access. */
 789         OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
 790         return retval;
 791 }
 792
 793 #ifdef CONFIG_EEPRO100_SROM_WRITE
 794 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
 795 {
 796     unsigned short dataval;
 797     int enable_cmd = 0x3f | EE_EWENB_CMD;
 798     int write_cmd  = location | EE_WRITE_CMD;
 799     int i;
 800     unsigned long datalong, tmplong;
 801
 802     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 803     udelay(1);
 804     OUTW(dev, EE_ENB, SCBeeprom);
 805
 806     /* Shift the enable command bits out. */
 807     for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
 808     {
 809         dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 810         OUTW(dev, EE_ENB | dataval, SCBeeprom);
 811         udelay(1);
 812         OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 813         udelay(1);
 814     }
 815
 816     OUTW(dev, EE_ENB, SCBeeprom);
 817     udelay(1);
 818     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 819     udelay(1);
 820     OUTW(dev, EE_ENB, SCBeeprom);
 821
 822
 823     /* Shift the write command bits out. */
 824     for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
 825     {
 826         dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 827         OUTW(dev, EE_ENB | dataval, SCBeeprom);
 828         udelay(1);
 829         OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 830         udelay(1);
 831     }
 832
 833     /* Write the data */
 834     datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
 835
 836     for (i = 0; i< EE_DATA_BITS; i++)
 837     {
 838     /* Extract and move data bit to bit DI */
 839     dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
 840
 841     OUTW(dev, EE_ENB | dataval, SCBeeprom);
 842     udelay(1);
 843     OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
 844     udelay(1);
 845     OUTW(dev, EE_ENB | dataval, SCBeeprom);
 846     udelay(1);
 847
 848     datalong = datalong << 1;   /* Adjust significant data bit*/
 849     }
 850
 851     /* Finish up command  (toggle CS) */
 852     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 853     udelay(1);                  /* delay for more than 250 ns */
 854     OUTW(dev, EE_ENB, SCBeeprom);
 855
 856     /* Wait for programming ready (D0 = 1) */
 857     tmplong = 10;
 858     do
 859     {
 860         dataval = INW(dev, SCBeeprom);
 861         if (dataval & EE_DATA_READ)
 862             break;
 863         udelay(10000);
 864     }
 865     while (-- tmplong);
 866
 867     if (tmplong == 0)
 868     {
 869         printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
 870         return -1;
 871     }
 872
 873     /* Terminate the EEPROM access. */
 874     OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
 875
 876     return 0;
 877 }
 878 #endif
 879
 880 static void init_rx_ring (struct eth_device *dev)
 881 {
 882         int i;
 883
 884         for (i = 0; i < NUM_RX_DESC; i++) {
 885                 rx_ring[i].status = 0;
 886                 rx_ring[i].control =
 887                                 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
 888                 rx_ring[i].link =
 889                                 cpu_to_le32 (phys_to_bus
 890                                                          ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
 891                 rx_ring[i].rx_buf_addr = 0xffffffff;
 892                 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
 893         }
 894
 895         rx_next = 0;
 896 }
 897
 898 static void purge_tx_ring (struct eth_device *dev)
 899 {
 900         int i;
 901
 902         tx_next = 0;
 903         tx_threshold = 0x01208000;
 904
 905         for (i = 0; i < NUM_TX_DESC; i++) {
 906                 tx_ring[i].status = 0;
 907                 tx_ring[i].command = 0;
 908                 tx_ring[i].link = 0;
 909                 tx_ring[i].tx_desc_addr = 0;
 910                 tx_ring[i].count = 0;
 911
 912                 tx_ring[i].tx_buf_addr0 = 0;
 913                 tx_ring[i].tx_buf_size0 = 0;
 914                 tx_ring[i].tx_buf_addr1 = 0;
 915                 tx_ring[i].tx_buf_size1 = 0;
 916         }
 917 }
 918
 919 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
 920 {
 921         u16 eeprom[0x40];
 922         u16 sum = 0;
 923         int i, j;
 924         int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
 925
 926         for (j = 0, i = 0; i < 0x40; i++) {
 927                 u16 value = read_eeprom (dev, i, addr_len);
 928
 929                 eeprom[i] = value;
 930                 sum += value;
 931                 if (i < 3) {
 932                         dev->enetaddr[j++] = value;
 933                         dev->enetaddr[j++] = value >> 8;
 934                 }
 935         }
 936
 937         if (sum != 0xBABA) {
 938                 memset (dev->enetaddr, 0, ETH_ALEN);
 939 #ifdef DEBUG
 940                 printf ("%s: Invalid EEPROM checksum %#4.4x, "
 941                         "check settings before activating this device!\n",
 942                         dev->name, sum);
 943 #endif
 944         }
 945 }