3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
18 /* Ethernet chip registers.
20 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
21 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
22 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
23 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
24 #define SCBPointer 4 /* General purpose pointer. */
25 #define SCBPort 8 /* Misc. commands and operands. */
26 #define SCBflash 12 /* Flash memory control. */
27 #define SCBeeprom 14 /* EEPROM memory control. */
28 #define SCBCtrlMDI 16 /* MDI interface control. */
29 #define SCBEarlyRx 20 /* Early receive byte count. */
30 #define SCBGenControl 28 /* 82559 General Control Register */
31 #define SCBGenStatus 29 /* 82559 General Status register */
33 /* 82559 SCB status word defnitions
35 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
36 #define SCB_STATUS_FR 0x4000 /* frame received */
37 #define SCB_STATUS_CNA 0x2000 /* CU left active state */
38 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
39 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
40 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
41 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
43 #define SCB_INTACK_MASK 0xFD00 /* all the above */
45 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
46 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
48 /* System control block commands
52 #define CU_START 0x0010
53 #define CU_RESUME 0x0020
54 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
55 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
56 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
57 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
60 #define RUC_NOP 0x0000
61 #define RUC_START 0x0001
62 #define RUC_RESUME 0x0002
63 #define RUC_ABORT 0x0004
64 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
65 #define RUC_RESUMENR 0x0007
67 #define CU_CMD_MASK 0x00f0
68 #define RU_CMD_MASK 0x0007
70 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
71 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
73 #define CU_STATUS_MASK 0x00C0
74 #define RU_STATUS_MASK 0x003C
76 #define RU_STATUS_IDLE (0<<2)
77 #define RU_STATUS_SUS (1<<2)
78 #define RU_STATUS_NORES (2<<2)
79 #define RU_STATUS_READY (4<<2)
80 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
81 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
82 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
84 /* 82559 Port interface commands.
86 #define I82559_RESET 0x00000000 /* Software reset */
87 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
88 #define I82559_SELECTIVE_RESET 0x00000002
89 #define I82559_DUMP 0x00000003
90 #define I82559_DUMP_WAKEUP 0x00000007
92 /* 82559 Eeprom interface.
94 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
95 #define EE_CS 0x02 /* EEPROM chip select. */
96 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
97 #define EE_WRITE_0 0x01
98 #define EE_WRITE_1 0x05
99 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
100 #define EE_ENB (0x4800 | EE_CS)
101 #define EE_CMD_BITS 3
102 #define EE_DATA_BITS 16
104 /* The EEPROM commands include the alway-set leading bit.
106 #define EE_EWENB_CMD (4 << addr_len)
107 #define EE_WRITE_CMD (5 << addr_len)
108 #define EE_READ_CMD (6 << addr_len)
109 #define EE_ERASE_CMD (7 << addr_len)
111 /* Receive frame descriptors.
115 volatile u16 control
;
116 volatile u32 link
; /* struct RxFD * */
117 volatile u32 rx_buf_addr
; /* void * */
120 volatile u8 data
[PKTSIZE_ALIGN
];
123 #define RFD_STATUS_C 0x8000 /* completion of received frame */
124 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
126 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
127 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
128 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
129 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
131 #define RFD_COUNT_MASK 0x3fff
132 #define RFD_COUNT_F 0x4000
133 #define RFD_COUNT_EOF 0x8000
135 #define RFD_RX_CRC 0x0800 /* crc error */
136 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
137 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
138 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
139 #define RFD_RX_SHORT 0x0080 /* short frame error */
140 #define RFD_RX_LENGTH 0x0020
141 #define RFD_RX_ERROR 0x0010 /* receive error */
142 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
143 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
144 #define RFD_RX_TCO 0x0001 /* TCO indication */
146 /* Transmit frame descriptors
148 struct TxFD
{ /* Transmit frame descriptor set. */
150 volatile u16 command
;
151 volatile u32 link
; /* void * */
152 volatile u32 tx_desc_addr
; /* Always points to the tx_buf_addr element. */
155 volatile u32 tx_buf_addr0
; /* void *, frame to be transmitted. */
156 volatile s32 tx_buf_size0
; /* Length of Tx frame. */
157 volatile u32 tx_buf_addr1
; /* void *, frame to be transmitted. */
158 volatile s32 tx_buf_size1
; /* Length of Tx frame. */
161 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
162 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
163 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
164 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
165 #define TxCB_CMD_S 0x4000 /* suspend on completion */
166 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
168 #define TxCB_COUNT_MASK 0x3fff
169 #define TxCB_COUNT_EOF 0x8000
171 /* The Speedo3 Rx and Tx frame/buffer descriptors.
173 struct descriptor
{ /* A generic descriptor. */
175 volatile u16 command
;
176 volatile u32 link
; /* struct descriptor * */
178 unsigned char params
[0];
181 #define CONFIG_SYS_CMD_EL 0x8000
182 #define CONFIG_SYS_CMD_SUSPEND 0x4000
183 #define CONFIG_SYS_CMD_INT 0x2000
184 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
185 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
187 #define CONFIG_SYS_STATUS_C 0x8000
188 #define CONFIG_SYS_STATUS_OK 0x2000
192 #define NUM_RX_DESC PKTBUFSRX
193 #define NUM_TX_DESC 1 /* Number of TX descriptors */
195 #define TOUT_LOOP 1000000
199 static struct RxFD rx_ring
[NUM_RX_DESC
]; /* RX descriptor ring */
200 static struct TxFD tx_ring
[NUM_TX_DESC
]; /* TX descriptor ring */
201 static int rx_next
; /* RX descriptor ring pointer */
202 static int tx_next
; /* TX descriptor ring pointer */
203 static int tx_threshold
;
206 * The parameters for a CmdConfigure operation.
207 * There are so many options that it would be difficult to document
208 * each bit. We mostly use the default or recommended settings.
210 static const char i82557_config_cmd
[] = {
211 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
213 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
216 static const char i82558_config_cmd
[] = {
217 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
218 0, 0x2E, 0, 0x60, 0x08, 0x88,
219 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
223 static void init_rx_ring (struct eth_device
*dev
);
224 static void purge_tx_ring (struct eth_device
*dev
);
226 static void read_hw_addr (struct eth_device
*dev
, bd_t
* bis
);
228 static int eepro100_init (struct eth_device
*dev
, bd_t
* bis
);
229 static int eepro100_send(struct eth_device
*dev
, void *packet
, int length
);
230 static int eepro100_recv (struct eth_device
*dev
);
231 static void eepro100_halt (struct eth_device
*dev
);
233 #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
234 #define bus_to_phys(a) (a)
235 #define phys_to_bus(a) (a)
237 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
238 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
241 static inline int INW (struct eth_device
*dev
, u_long addr
)
243 return le16_to_cpu (*(volatile u16
*) (addr
+ dev
->iobase
));
246 static inline void OUTW (struct eth_device
*dev
, int command
, u_long addr
)
248 *(volatile u16
*) ((addr
+ dev
->iobase
)) = cpu_to_le16 (command
);
251 static inline void OUTL (struct eth_device
*dev
, int command
, u_long addr
)
253 *(volatile u32
*) ((addr
+ dev
->iobase
)) = cpu_to_le32 (command
);
256 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
257 static inline int INL (struct eth_device
*dev
, u_long addr
)
259 return le32_to_cpu (*(volatile u32
*) (addr
+ dev
->iobase
));
262 static int get_phyreg (struct eth_device
*dev
, unsigned char addr
,
263 unsigned char reg
, unsigned short *value
)
268 /* read requested data */
269 cmd
= (2 << 26) | ((addr
& 0x1f) << 21) | ((reg
& 0x1f) << 16);
270 OUTL (dev
, cmd
, SCBCtrlMDI
);
274 cmd
= INL (dev
, SCBCtrlMDI
);
275 } while (!(cmd
& (1 << 28)) && (--timeout
));
280 *value
= (unsigned short) (cmd
& 0xffff);
285 static int set_phyreg (struct eth_device
*dev
, unsigned char addr
,
286 unsigned char reg
, unsigned short value
)
291 /* write requested data */
292 cmd
= (1 << 26) | ((addr
& 0x1f) << 21) | ((reg
& 0x1f) << 16);
293 OUTL (dev
, cmd
| value
, SCBCtrlMDI
);
295 while (!(INL (dev
, SCBCtrlMDI
) & (1 << 28)) && (--timeout
))
304 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
305 * Do this by checking model value field from ID2 register.
307 static struct eth_device
* verify_phyaddr (const char *devname
,
310 struct eth_device
*dev
;
311 unsigned short value
;
314 dev
= eth_get_dev_by_name(devname
);
316 printf("%s: no such device\n", devname
);
320 /* read id2 register */
321 if (get_phyreg(dev
, addr
, MII_PHYSID2
, &value
) != 0) {
322 printf("%s: mii read timeout!\n", devname
);
327 model
= (unsigned char)((value
>> 4) & 0x003f);
330 printf("%s: no PHY at address %d\n", devname
, addr
);
337 static int eepro100_miiphy_read(const char *devname
, unsigned char addr
,
338 unsigned char reg
, unsigned short *value
)
340 struct eth_device
*dev
;
342 dev
= verify_phyaddr(devname
, addr
);
346 if (get_phyreg(dev
, addr
, reg
, value
) != 0) {
347 printf("%s: mii read timeout!\n", devname
);
354 static int eepro100_miiphy_write(const char *devname
, unsigned char addr
,
355 unsigned char reg
, unsigned short value
)
357 struct eth_device
*dev
;
359 dev
= verify_phyaddr(devname
, addr
);
363 if (set_phyreg(dev
, addr
, reg
, value
) != 0) {
364 printf("%s: mii write timeout!\n", devname
);
373 /* Wait for the chip get the command.
375 static int wait_for_eepro100 (struct eth_device
*dev
)
379 for (i
= 0; INW (dev
, SCBCmd
) & (CU_CMD_MASK
| RU_CMD_MASK
); i
++) {
380 if (i
>= TOUT_LOOP
) {
388 static struct pci_device_id supported
[] = {
389 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82557
},
390 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82559
},
391 {PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82559ER
},
395 int eepro100_initialize (bd_t
* bis
)
399 struct eth_device
*dev
;
406 if ((devno
= pci_find_devices (supported
, idx
++)) < 0) {
410 pci_read_config_dword (devno
, PCI_BASE_ADDRESS_0
, &iobase
);
414 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
418 pci_write_config_dword (devno
,
420 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
422 /* Check if I/O accesses and Bus Mastering are enabled.
424 pci_read_config_dword (devno
, PCI_COMMAND
, &status
);
425 if (!(status
& PCI_COMMAND_MEMORY
)) {
426 printf ("Error: Can not enable MEM access.\n");
430 if (!(status
& PCI_COMMAND_MASTER
)) {
431 printf ("Error: Can not enable Bus Mastering.\n");
435 dev
= (struct eth_device
*) malloc (sizeof *dev
);
437 printf("eepro100: Can not allocate memory\n");
440 memset(dev
, 0, sizeof(*dev
));
442 sprintf (dev
->name
, "i82559#%d", card_number
);
443 dev
->priv
= (void *) devno
; /* this have to come before bus_to_phys() */
444 dev
->iobase
= bus_to_phys (iobase
);
445 dev
->init
= eepro100_init
;
446 dev
->halt
= eepro100_halt
;
447 dev
->send
= eepro100_send
;
448 dev
->recv
= eepro100_recv
;
452 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
453 /* register mii command access routines */
454 miiphy_register(dev
->name
,
455 eepro100_miiphy_read
, eepro100_miiphy_write
);
460 /* Set the latency timer for value.
462 pci_write_config_byte (devno
, PCI_LATENCY_TIMER
, 0x20);
466 read_hw_addr (dev
, bis
);
473 static int eepro100_init (struct eth_device
*dev
, bd_t
* bis
)
477 struct descriptor
*ias_cmd
, *cfg_cmd
;
479 /* Reset the ethernet controller
481 OUTL (dev
, I82559_SELECTIVE_RESET
, SCBPort
);
484 OUTL (dev
, I82559_RESET
, SCBPort
);
487 if (!wait_for_eepro100 (dev
)) {
488 printf ("Error: Can not reset ethernet controller.\n");
491 OUTL (dev
, 0, SCBPointer
);
492 OUTW (dev
, SCB_M
| RUC_ADDR_LOAD
, SCBCmd
);
494 if (!wait_for_eepro100 (dev
)) {
495 printf ("Error: Can not reset ethernet controller.\n");
498 OUTL (dev
, 0, SCBPointer
);
499 OUTW (dev
, SCB_M
| CU_ADDR_LOAD
, SCBCmd
);
501 /* Initialize Rx and Tx rings.
506 /* Tell the adapter where the RX ring is located.
508 if (!wait_for_eepro100 (dev
)) {
509 printf ("Error: Can not reset ethernet controller.\n");
513 OUTL (dev
, phys_to_bus ((u32
) & rx_ring
[rx_next
]), SCBPointer
);
514 OUTW (dev
, SCB_M
| RUC_START
, SCBCmd
);
516 /* Send the Configure frame */
518 tx_next
= ((tx_next
+ 1) % NUM_TX_DESC
);
520 cfg_cmd
= (struct descriptor
*) &tx_ring
[tx_cur
];
521 cfg_cmd
->command
= cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND
| CONFIG_SYS_CMD_CONFIGURE
));
523 cfg_cmd
->link
= cpu_to_le32 (phys_to_bus ((u32
) & tx_ring
[tx_next
]));
525 memcpy (cfg_cmd
->params
, i82558_config_cmd
,
526 sizeof (i82558_config_cmd
));
528 if (!wait_for_eepro100 (dev
)) {
529 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
533 OUTL (dev
, phys_to_bus ((u32
) & tx_ring
[tx_cur
]), SCBPointer
);
534 OUTW (dev
, SCB_M
| CU_START
, SCBCmd
);
537 !(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_C
);
539 if (i
>= TOUT_LOOP
) {
540 printf ("%s: Tx error buffer not ready\n", dev
->name
);
545 if (!(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_OK
)) {
546 printf ("TX error status = 0x%08X\n",
547 le16_to_cpu (tx_ring
[tx_cur
].status
));
551 /* Send the Individual Address Setup frame
554 tx_next
= ((tx_next
+ 1) % NUM_TX_DESC
);
556 ias_cmd
= (struct descriptor
*) &tx_ring
[tx_cur
];
557 ias_cmd
->command
= cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND
| CONFIG_SYS_CMD_IAS
));
559 ias_cmd
->link
= cpu_to_le32 (phys_to_bus ((u32
) & tx_ring
[tx_next
]));
561 memcpy (ias_cmd
->params
, dev
->enetaddr
, 6);
563 /* Tell the adapter where the TX ring is located.
565 if (!wait_for_eepro100 (dev
)) {
566 printf ("Error: Can not reset ethernet controller.\n");
570 OUTL (dev
, phys_to_bus ((u32
) & tx_ring
[tx_cur
]), SCBPointer
);
571 OUTW (dev
, SCB_M
| CU_START
, SCBCmd
);
573 for (i
= 0; !(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_C
);
575 if (i
>= TOUT_LOOP
) {
576 printf ("%s: Tx error buffer not ready\n",
582 if (!(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_OK
)) {
583 printf ("TX error status = 0x%08X\n",
584 le16_to_cpu (tx_ring
[tx_cur
].status
));
594 static int eepro100_send(struct eth_device
*dev
, void *packet
, int length
)
600 printf ("%s: bad packet size: %d\n", dev
->name
, length
);
605 tx_next
= (tx_next
+ 1) % NUM_TX_DESC
;
607 tx_ring
[tx_cur
].command
= cpu_to_le16 ( TxCB_CMD_TRANSMIT
|
611 tx_ring
[tx_cur
].status
= 0;
612 tx_ring
[tx_cur
].count
= cpu_to_le32 (tx_threshold
);
613 tx_ring
[tx_cur
].link
=
614 cpu_to_le32 (phys_to_bus ((u32
) & tx_ring
[tx_next
]));
615 tx_ring
[tx_cur
].tx_desc_addr
=
616 cpu_to_le32 (phys_to_bus ((u32
) & tx_ring
[tx_cur
].tx_buf_addr0
));
617 tx_ring
[tx_cur
].tx_buf_addr0
=
618 cpu_to_le32 (phys_to_bus ((u_long
) packet
));
619 tx_ring
[tx_cur
].tx_buf_size0
= cpu_to_le32 (length
);
621 if (!wait_for_eepro100 (dev
)) {
622 printf ("%s: Tx error ethernet controller not ready.\n",
629 OUTL (dev
, phys_to_bus ((u32
) & tx_ring
[tx_cur
]), SCBPointer
);
630 OUTW (dev
, SCB_M
| CU_START
, SCBCmd
);
632 for (i
= 0; !(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_C
);
634 if (i
>= TOUT_LOOP
) {
635 printf ("%s: Tx error buffer not ready\n", dev
->name
);
640 if (!(le16_to_cpu (tx_ring
[tx_cur
].status
) & CONFIG_SYS_STATUS_OK
)) {
641 printf ("TX error status = 0x%08X\n",
642 le16_to_cpu (tx_ring
[tx_cur
].status
));
652 static int eepro100_recv (struct eth_device
*dev
)
655 int rx_prev
, length
= 0;
657 stat
= INW (dev
, SCBStatus
);
658 OUTW (dev
, stat
& SCB_STATUS_RNR
, SCBStatus
);
661 status
= le16_to_cpu (rx_ring
[rx_next
].status
);
663 if (!(status
& RFD_STATUS_C
)) {
667 /* Valid frame status.
669 if ((status
& RFD_STATUS_OK
)) {
670 /* A valid frame received.
672 length
= le32_to_cpu (rx_ring
[rx_next
].count
) & 0x3fff;
674 /* Pass the packet up to the protocol
677 NetReceive((u8
*)rx_ring
[rx_next
].data
, length
);
679 /* There was an error.
681 printf ("RX error status = 0x%08X\n", status
);
684 rx_ring
[rx_next
].control
= cpu_to_le16 (RFD_CONTROL_S
);
685 rx_ring
[rx_next
].status
= 0;
686 rx_ring
[rx_next
].count
= cpu_to_le32 (PKTSIZE_ALIGN
<< 16);
688 rx_prev
= (rx_next
+ NUM_RX_DESC
- 1) % NUM_RX_DESC
;
689 rx_ring
[rx_prev
].control
= 0;
691 /* Update entry information.
693 rx_next
= (rx_next
+ 1) % NUM_RX_DESC
;
696 if (stat
& SCB_STATUS_RNR
) {
698 printf ("%s: Receiver is not ready, restart it !\n", dev
->name
);
700 /* Reinitialize Rx ring.
704 if (!wait_for_eepro100 (dev
)) {
705 printf ("Error: Can not restart ethernet controller.\n");
709 OUTL (dev
, phys_to_bus ((u32
) & rx_ring
[rx_next
]), SCBPointer
);
710 OUTW (dev
, SCB_M
| RUC_START
, SCBCmd
);
717 static void eepro100_halt (struct eth_device
*dev
)
719 /* Reset the ethernet controller
721 OUTL (dev
, I82559_SELECTIVE_RESET
, SCBPort
);
724 OUTL (dev
, I82559_RESET
, SCBPort
);
727 if (!wait_for_eepro100 (dev
)) {
728 printf ("Error: Can not reset ethernet controller.\n");
731 OUTL (dev
, 0, SCBPointer
);
732 OUTW (dev
, SCB_M
| RUC_ADDR_LOAD
, SCBCmd
);
734 if (!wait_for_eepro100 (dev
)) {
735 printf ("Error: Can not reset ethernet controller.\n");
738 OUTL (dev
, 0, SCBPointer
);
739 OUTW (dev
, SCB_M
| CU_ADDR_LOAD
, SCBCmd
);
747 static int read_eeprom (struct eth_device
*dev
, int location
, int addr_len
)
749 unsigned short retval
= 0;
750 int read_cmd
= location
| EE_READ_CMD
;
753 OUTW (dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
754 OUTW (dev
, EE_ENB
, SCBeeprom
);
756 /* Shift the read command bits out. */
757 for (i
= 12; i
>= 0; i
--) {
758 short dataval
= (read_cmd
& (1 << i
)) ? EE_DATA_WRITE
: 0;
760 OUTW (dev
, EE_ENB
| dataval
, SCBeeprom
);
762 OUTW (dev
, EE_ENB
| dataval
| EE_SHIFT_CLK
, SCBeeprom
);
765 OUTW (dev
, EE_ENB
, SCBeeprom
);
767 for (i
= 15; i
>= 0; i
--) {
768 OUTW (dev
, EE_ENB
| EE_SHIFT_CLK
, SCBeeprom
);
770 retval
= (retval
<< 1) |
771 ((INW (dev
, SCBeeprom
) & EE_DATA_READ
) ? 1 : 0);
772 OUTW (dev
, EE_ENB
, SCBeeprom
);
776 /* Terminate the EEPROM access. */
777 OUTW (dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
781 #ifdef CONFIG_EEPRO100_SROM_WRITE
782 int eepro100_write_eeprom (struct eth_device
* dev
, int location
, int addr_len
, unsigned short data
)
784 unsigned short dataval
;
785 int enable_cmd
= 0x3f | EE_EWENB_CMD
;
786 int write_cmd
= location
| EE_WRITE_CMD
;
788 unsigned long datalong
, tmplong
;
790 OUTW(dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
792 OUTW(dev
, EE_ENB
, SCBeeprom
);
794 /* Shift the enable command bits out. */
795 for (i
= (addr_len
+EE_CMD_BITS
-1); i
>= 0; i
--)
797 dataval
= (enable_cmd
& (1 << i
)) ? EE_DATA_WRITE
: 0;
798 OUTW(dev
, EE_ENB
| dataval
, SCBeeprom
);
800 OUTW(dev
, EE_ENB
| dataval
| EE_SHIFT_CLK
, SCBeeprom
);
804 OUTW(dev
, EE_ENB
, SCBeeprom
);
806 OUTW(dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
808 OUTW(dev
, EE_ENB
, SCBeeprom
);
811 /* Shift the write command bits out. */
812 for (i
= (addr_len
+EE_CMD_BITS
-1); i
>= 0; i
--)
814 dataval
= (write_cmd
& (1 << i
)) ? EE_DATA_WRITE
: 0;
815 OUTW(dev
, EE_ENB
| dataval
, SCBeeprom
);
817 OUTW(dev
, EE_ENB
| dataval
| EE_SHIFT_CLK
, SCBeeprom
);
822 datalong
= (unsigned long) ((((data
) & 0x00ff) << 8) | ( (data
) >> 8));
824 for (i
= 0; i
< EE_DATA_BITS
; i
++)
826 /* Extract and move data bit to bit DI */
827 dataval
= ((datalong
& 0x8000)>>13) ? EE_DATA_WRITE
: 0;
829 OUTW(dev
, EE_ENB
| dataval
, SCBeeprom
);
831 OUTW(dev
, EE_ENB
| dataval
| EE_SHIFT_CLK
, SCBeeprom
);
833 OUTW(dev
, EE_ENB
| dataval
, SCBeeprom
);
836 datalong
= datalong
<< 1; /* Adjust significant data bit*/
839 /* Finish up command (toggle CS) */
840 OUTW(dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
841 udelay(1); /* delay for more than 250 ns */
842 OUTW(dev
, EE_ENB
, SCBeeprom
);
844 /* Wait for programming ready (D0 = 1) */
848 dataval
= INW(dev
, SCBeeprom
);
849 if (dataval
& EE_DATA_READ
)
857 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
861 /* Terminate the EEPROM access. */
862 OUTW(dev
, EE_ENB
& ~EE_CS
, SCBeeprom
);
868 static void init_rx_ring (struct eth_device
*dev
)
872 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
873 rx_ring
[i
].status
= 0;
875 (i
== NUM_RX_DESC
- 1) ? cpu_to_le16 (RFD_CONTROL_S
) : 0;
877 cpu_to_le32 (phys_to_bus
878 ((u32
) & rx_ring
[(i
+ 1) % NUM_RX_DESC
]));
879 rx_ring
[i
].rx_buf_addr
= 0xffffffff;
880 rx_ring
[i
].count
= cpu_to_le32 (PKTSIZE_ALIGN
<< 16);
886 static void purge_tx_ring (struct eth_device
*dev
)
891 tx_threshold
= 0x01208000;
893 for (i
= 0; i
< NUM_TX_DESC
; i
++) {
894 tx_ring
[i
].status
= 0;
895 tx_ring
[i
].command
= 0;
897 tx_ring
[i
].tx_desc_addr
= 0;
898 tx_ring
[i
].count
= 0;
900 tx_ring
[i
].tx_buf_addr0
= 0;
901 tx_ring
[i
].tx_buf_size0
= 0;
902 tx_ring
[i
].tx_buf_addr1
= 0;
903 tx_ring
[i
].tx_buf_size1
= 0;
907 static void read_hw_addr (struct eth_device
*dev
, bd_t
* bis
)
911 int addr_len
= read_eeprom (dev
, 0, 6) == 0xffff ? 8 : 6;
913 for (j
= 0, i
= 0; i
< 0x40; i
++) {
914 u16 value
= read_eeprom (dev
, i
, addr_len
);
918 dev
->enetaddr
[j
++] = value
;
919 dev
->enetaddr
[j
++] = value
>> 8;
924 memset (dev
->enetaddr
, 0, ETH_ALEN
);
926 printf ("%s: Invalid EEPROM checksum %#4.4x, "
927 "check settings before activating this device!\n",