]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/ep93xx_eth.c
2 * Cirrus Logic EP93xx ethernet MAC / MII driver.
4 * Copyright (C) 2010, 2009
5 * Matthias Kaehlcke <matthias@kaehlcke.net>
7 * Copyright (C) 2004, 2005
8 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
10 * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
13 * (C) Copyright 2002 2003
14 * Adam Bezanson, Network Audio Technologies, Inc.
15 * <bezanson@netaudiotech.com>
17 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/ep93xx.h>
26 #include <linux/types.h>
27 #include "ep93xx_eth.h"
29 #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
30 #define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
32 /* ep93xx_miiphy ops forward declarations */
33 static int ep93xx_miiphy_read(struct mii_dev
*bus
, int addr
, int devad
,
35 static int ep93xx_miiphy_write(struct mii_dev
*bus
, int addr
, int devad
,
38 #if defined(EP93XX_MAC_DEBUG)
40 * Dump ep93xx_mac values to the terminal.
42 static void dump_dev(struct eth_device
*dev
)
44 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
47 printf("\ndump_dev()\n");
48 printf(" rx_dq.base %p\n", priv
->rx_dq
.base
);
49 printf(" rx_dq.current %p\n", priv
->rx_dq
.current
);
50 printf(" rx_dq.end %p\n", priv
->rx_dq
.end
);
51 printf(" rx_sq.base %p\n", priv
->rx_sq
.base
);
52 printf(" rx_sq.current %p\n", priv
->rx_sq
.current
);
53 printf(" rx_sq.end %p\n", priv
->rx_sq
.end
);
55 for (i
= 0; i
< NUMRXDESC
; i
++)
56 printf(" rx_buffer[%2.d] %p\n", i
, net_rx_packets
[i
]);
58 printf(" tx_dq.base %p\n", priv
->tx_dq
.base
);
59 printf(" tx_dq.current %p\n", priv
->tx_dq
.current
);
60 printf(" tx_dq.end %p\n", priv
->tx_dq
.end
);
61 printf(" tx_sq.base %p\n", priv
->tx_sq
.base
);
62 printf(" tx_sq.current %p\n", priv
->tx_sq
.current
);
63 printf(" tx_sq.end %p\n", priv
->tx_sq
.end
);
67 * Dump all RX status queue entries to the terminal.
69 static void dump_rx_status_queue(struct eth_device
*dev
)
71 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
74 printf("\ndump_rx_status_queue()\n");
75 printf(" descriptor address word1 word2\n");
76 for (i
= 0; i
< NUMRXDESC
; i
++) {
77 printf(" [ %p ] %08X %08X\n",
79 (priv
->rx_sq
.base
+ i
)->word1
,
80 (priv
->rx_sq
.base
+ i
)->word2
);
85 * Dump all RX descriptor queue entries to the terminal.
87 static void dump_rx_descriptor_queue(struct eth_device
*dev
)
89 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
92 printf("\ndump_rx_descriptor_queue()\n");
93 printf(" descriptor address word1 word2\n");
94 for (i
= 0; i
< NUMRXDESC
; i
++) {
95 printf(" [ %p ] %08X %08X\n",
97 (priv
->rx_dq
.base
+ i
)->word1
,
98 (priv
->rx_dq
.base
+ i
)->word2
);
103 * Dump all TX descriptor queue entries to the terminal.
105 static void dump_tx_descriptor_queue(struct eth_device
*dev
)
107 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
110 printf("\ndump_tx_descriptor_queue()\n");
111 printf(" descriptor address word1 word2\n");
112 for (i
= 0; i
< NUMTXDESC
; i
++) {
113 printf(" [ %p ] %08X %08X\n",
114 priv
->tx_dq
.base
+ i
,
115 (priv
->tx_dq
.base
+ i
)->word1
,
116 (priv
->tx_dq
.base
+ i
)->word2
);
121 * Dump all TX status queue entries to the terminal.
123 static void dump_tx_status_queue(struct eth_device
*dev
)
125 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
128 printf("\ndump_tx_status_queue()\n");
129 printf(" descriptor address word1\n");
130 for (i
= 0; i
< NUMTXDESC
; i
++) {
131 printf(" [ %p ] %08X\n",
132 priv
->rx_sq
.base
+ i
,
133 (priv
->rx_sq
.base
+ i
)->word1
);
138 #define dump_rx_descriptor_queue(x)
139 #define dump_rx_status_queue(x)
140 #define dump_tx_descriptor_queue(x)
141 #define dump_tx_status_queue(x)
142 #endif /* defined(EP93XX_MAC_DEBUG) */
145 * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
148 static void ep93xx_mac_reset(struct eth_device
*dev
)
150 struct mac_regs
*mac
= GET_REGS(dev
);
153 debug("+ep93xx_mac_reset");
155 value
= readl(&mac
->selfctl
);
156 value
|= SELFCTL_RESET
;
157 writel(value
, &mac
->selfctl
);
159 while (readl(&mac
->selfctl
) & SELFCTL_RESET
)
162 debug("-ep93xx_mac_reset");
165 /* Eth device open */
166 static int ep93xx_eth_open(struct eth_device
*dev
, bd_t
*bd
)
168 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
169 struct mac_regs
*mac
= GET_REGS(dev
);
170 uchar
*mac_addr
= dev
->enetaddr
;
173 debug("+ep93xx_eth_open");
176 ep93xx_mac_reset(dev
);
178 /* Reset the descriptor queues' current and end address values */
179 priv
->tx_dq
.current
= priv
->tx_dq
.base
;
180 priv
->tx_dq
.end
= (priv
->tx_dq
.base
+ NUMTXDESC
);
182 priv
->tx_sq
.current
= priv
->tx_sq
.base
;
183 priv
->tx_sq
.end
= (priv
->tx_sq
.base
+ NUMTXDESC
);
185 priv
->rx_dq
.current
= priv
->rx_dq
.base
;
186 priv
->rx_dq
.end
= (priv
->rx_dq
.base
+ NUMRXDESC
);
188 priv
->rx_sq
.current
= priv
->rx_sq
.base
;
189 priv
->rx_sq
.end
= (priv
->rx_sq
.base
+ NUMRXDESC
);
192 * Set the transmit descriptor and status queues' base address,
193 * current address, and length registers. Set the maximum frame
194 * length and threshold. Enable the transmit descriptor processor.
196 writel((uint32_t)priv
->tx_dq
.base
, &mac
->txdq
.badd
);
197 writel((uint32_t)priv
->tx_dq
.base
, &mac
->txdq
.curadd
);
198 writel(sizeof(struct tx_descriptor
) * NUMTXDESC
, &mac
->txdq
.blen
);
200 writel((uint32_t)priv
->tx_sq
.base
, &mac
->txstsq
.badd
);
201 writel((uint32_t)priv
->tx_sq
.base
, &mac
->txstsq
.curadd
);
202 writel(sizeof(struct tx_status
) * NUMTXDESC
, &mac
->txstsq
.blen
);
204 writel(0x00040000, &mac
->txdthrshld
);
205 writel(0x00040000, &mac
->txststhrshld
);
207 writel((TXSTARTMAX
<< 0) | (PKTSIZE_ALIGN
<< 16), &mac
->maxfrmlen
);
208 writel(BMCTL_TXEN
, &mac
->bmctl
);
211 * Set the receive descriptor and status queues' base address,
212 * current address, and length registers. Enable the receive
213 * descriptor processor.
215 writel((uint32_t)priv
->rx_dq
.base
, &mac
->rxdq
.badd
);
216 writel((uint32_t)priv
->rx_dq
.base
, &mac
->rxdq
.curadd
);
217 writel(sizeof(struct rx_descriptor
) * NUMRXDESC
, &mac
->rxdq
.blen
);
219 writel((uint32_t)priv
->rx_sq
.base
, &mac
->rxstsq
.badd
);
220 writel((uint32_t)priv
->rx_sq
.base
, &mac
->rxstsq
.curadd
);
221 writel(sizeof(struct rx_status
) * NUMRXDESC
, &mac
->rxstsq
.blen
);
223 writel(0x00040000, &mac
->rxdthrshld
);
225 writel(BMCTL_RXEN
, &mac
->bmctl
);
227 writel(0x00040000, &mac
->rxststhrshld
);
229 /* Wait until the receive descriptor processor is active */
230 while (!(readl(&mac
->bmsts
) & BMSTS_RXACT
))
234 * Initialize the RX descriptor queue. Clear the TX descriptor queue.
235 * Clear the RX and TX status queues. Enqueue the RX descriptor and
236 * status entries to the MAC.
238 for (i
= 0; i
< NUMRXDESC
; i
++) {
239 /* set buffer address */
240 (priv
->rx_dq
.base
+ i
)->word1
= (uint32_t)net_rx_packets
[i
];
242 /* set buffer length, clear buffer index and NSOF */
243 (priv
->rx_dq
.base
+ i
)->word2
= PKTSIZE_ALIGN
;
246 memset(priv
->tx_dq
.base
, 0,
247 (sizeof(struct tx_descriptor
) * NUMTXDESC
));
248 memset(priv
->rx_sq
.base
, 0,
249 (sizeof(struct rx_status
) * NUMRXDESC
));
250 memset(priv
->tx_sq
.base
, 0,
251 (sizeof(struct tx_status
) * NUMTXDESC
));
253 writel(NUMRXDESC
, &mac
->rxdqenq
);
254 writel(NUMRXDESC
, &mac
->rxstsqenq
);
256 /* Set the primary MAC address */
257 writel(AFP_IAPRIMARY
, &mac
->afp
);
258 writel(mac_addr
[0] | (mac_addr
[1] << 8) |
259 (mac_addr
[2] << 16) | (mac_addr
[3] << 24),
261 writel(mac_addr
[4] | (mac_addr
[5] << 8), &mac
->indad_upper
);
263 /* Turn on RX and TX */
264 writel(RXCTL_IA0
| RXCTL_BA
| RXCTL_SRXON
|
265 RXCTL_RCRCA
| RXCTL_MA
, &mac
->rxctl
);
266 writel(TXCTL_STXON
, &mac
->txctl
);
268 /* Dump data structures if we're debugging */
270 dump_rx_descriptor_queue(dev
);
271 dump_rx_status_queue(dev
);
272 dump_tx_descriptor_queue(dev
);
273 dump_tx_status_queue(dev
);
275 debug("-ep93xx_eth_open");
281 * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
284 static void ep93xx_eth_close(struct eth_device
*dev
)
286 struct mac_regs
*mac
= GET_REGS(dev
);
288 debug("+ep93xx_eth_close");
290 writel(0x00000000, &mac
->rxctl
);
291 writel(0x00000000, &mac
->txctl
);
293 debug("-ep93xx_eth_close");
297 * Copy a frame of data from the MAC into the protocol layer for further
300 static int ep93xx_eth_rcv_packet(struct eth_device
*dev
)
302 struct mac_regs
*mac
= GET_REGS(dev
);
303 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
306 debug("+ep93xx_eth_rcv_packet");
308 if (RX_STATUS_RFP(priv
->rx_sq
.current
)) {
309 if (RX_STATUS_RWE(priv
->rx_sq
.current
)) {
311 * We have a good frame. Extract the frame's length
312 * from the current rx_status_queue entry, and copy
313 * the frame's data into net_rx_packets[] of the
314 * protocol stack. We track the total number of
315 * bytes in the frame (nbytes_frame) which will be
316 * used when we pass the data off to the protocol
317 * layer via net_process_received_packet().
319 len
= RX_STATUS_FRAME_LEN(priv
->rx_sq
.current
);
321 net_process_received_packet(
322 (uchar
*)priv
->rx_dq
.current
->word1
, len
);
324 debug("reporting %d bytes...\n", len
);
326 /* Do we have an erroneous packet? */
327 pr_err("packet rx error, status %08X %08X",
328 priv
->rx_sq
.current
->word1
,
329 priv
->rx_sq
.current
->word2
);
330 dump_rx_descriptor_queue(dev
);
331 dump_rx_status_queue(dev
);
335 * Clear the associated status queue entry, and
336 * increment our current pointers to the next RX
337 * descriptor and status queue entries (making sure
340 memset((void *)priv
->rx_sq
.current
, 0,
341 sizeof(struct rx_status
));
343 priv
->rx_sq
.current
++;
344 if (priv
->rx_sq
.current
>= priv
->rx_sq
.end
)
345 priv
->rx_sq
.current
= priv
->rx_sq
.base
;
347 priv
->rx_dq
.current
++;
348 if (priv
->rx_dq
.current
>= priv
->rx_dq
.end
)
349 priv
->rx_dq
.current
= priv
->rx_dq
.base
;
352 * Finally, return the RX descriptor and status entries
353 * back to the MAC engine, and loop again, checking for
354 * more descriptors to process.
356 writel(1, &mac
->rxdqenq
);
357 writel(1, &mac
->rxstsqenq
);
362 debug("-ep93xx_eth_rcv_packet %d", len
);
367 * Send a block of data via ethernet.
369 static int ep93xx_eth_send_packet(struct eth_device
*dev
,
370 void * const packet
, int const length
)
372 struct mac_regs
*mac
= GET_REGS(dev
);
373 struct ep93xx_priv
*priv
= GET_PRIV(dev
);
376 debug("+ep93xx_eth_send_packet");
378 /* Parameter check */
379 BUG_ON(packet
== NULL
);
382 * Initialize the TX descriptor queue with the new packet's info.
383 * Clear the associated status queue entry. Enqueue the packet
384 * to the MAC for transmission.
387 /* set buffer address */
388 priv
->tx_dq
.current
->word1
= (uint32_t)packet
;
390 /* set buffer length and EOF bit */
391 priv
->tx_dq
.current
->word2
= length
| TX_DESC_EOF
;
393 /* clear tx status */
394 priv
->tx_sq
.current
->word1
= 0;
396 /* enqueue the TX descriptor */
397 writel(1, &mac
->txdqenq
);
399 /* wait for the frame to become processed */
400 while (!TX_STATUS_TXFP(priv
->tx_sq
.current
))
403 if (!TX_STATUS_TXWE(priv
->tx_sq
.current
)) {
404 pr_err("packet tx error, status %08X",
405 priv
->tx_sq
.current
->word1
);
406 dump_tx_descriptor_queue(dev
);
407 dump_tx_status_queue(dev
);
409 /* TODO: Add better error handling? */
417 debug("-ep93xx_eth_send_packet %d", ret
);
421 #if defined(CONFIG_MII)
422 int ep93xx_miiphy_initialize(bd_t
* const bd
)
425 struct mii_dev
*mdiodev
= mdio_alloc();
428 strncpy(mdiodev
->name
, "ep93xx_eth0", MDIO_NAME_LEN
);
429 mdiodev
->read
= ep93xx_miiphy_read
;
430 mdiodev
->write
= ep93xx_miiphy_write
;
432 retval
= mdio_register(mdiodev
);
440 * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
441 * allocated, if necessary, for the TX and RX descriptor and status queues,
442 * as well as for received packets. The EP93XX MAC hardware is initialized.
443 * Transmit and receive operations are enabled.
445 int ep93xx_eth_initialize(u8 dev_num
, int base_addr
)
448 struct eth_device
*dev
;
449 struct ep93xx_priv
*priv
;
451 debug("+ep93xx_eth_initialize");
453 priv
= malloc(sizeof(*priv
));
455 pr_err("malloc() failed");
456 goto eth_init_failed_0
;
458 memset(priv
, 0, sizeof(*priv
));
460 priv
->regs
= (struct mac_regs
*)base_addr
;
462 priv
->tx_dq
.base
= calloc(NUMTXDESC
,
463 sizeof(struct tx_descriptor
));
464 if (priv
->tx_dq
.base
== NULL
) {
465 pr_err("calloc() failed");
466 goto eth_init_failed_1
;
469 priv
->tx_sq
.base
= calloc(NUMTXDESC
,
470 sizeof(struct tx_status
));
471 if (priv
->tx_sq
.base
== NULL
) {
472 pr_err("calloc() failed");
473 goto eth_init_failed_2
;
476 priv
->rx_dq
.base
= calloc(NUMRXDESC
,
477 sizeof(struct rx_descriptor
));
478 if (priv
->rx_dq
.base
== NULL
) {
479 pr_err("calloc() failed");
480 goto eth_init_failed_3
;
483 priv
->rx_sq
.base
= calloc(NUMRXDESC
,
484 sizeof(struct rx_status
));
485 if (priv
->rx_sq
.base
== NULL
) {
486 pr_err("calloc() failed");
487 goto eth_init_failed_4
;
490 dev
= malloc(sizeof *dev
);
492 pr_err("malloc() failed");
493 goto eth_init_failed_5
;
495 memset(dev
, 0, sizeof *dev
);
497 dev
->iobase
= base_addr
;
499 dev
->init
= ep93xx_eth_open
;
500 dev
->halt
= ep93xx_eth_close
;
501 dev
->send
= ep93xx_eth_send_packet
;
502 dev
->recv
= ep93xx_eth_rcv_packet
;
504 sprintf(dev
->name
, "ep93xx_eth-%hu", dev_num
);
513 free(priv
->rx_sq
.base
);
517 free(priv
->rx_dq
.base
);
521 free(priv
->tx_sq
.base
);
525 free(priv
->tx_dq
.base
);
536 debug("-ep93xx_eth_initialize %d", ret
);
540 #if defined(CONFIG_MII)
543 * Maximum MII address we support
545 #define MII_ADDRESS_MAX 31
548 * Maximum MII register address we support
550 #define MII_REGISTER_MAX 31
553 * Read a 16-bit value from an MII register.
555 static int ep93xx_miiphy_read(struct mii_dev
*bus
, int addr
, int devad
,
558 unsigned short value
= 0;
559 struct mac_regs
*mac
= (struct mac_regs
*)MAC_BASE
;
563 debug("+ep93xx_miiphy_read");
565 /* Parameter checks */
566 BUG_ON(bus
->name
== NULL
);
567 BUG_ON(addr
> MII_ADDRESS_MAX
);
568 BUG_ON(reg
> MII_REGISTER_MAX
);
571 * Save the current SelfCTL register value. Set MAC to suppress
572 * preamble bits. Wait for any previous MII command to complete
573 * before issuing the new command.
575 self_ctl
= readl(&mac
->selfctl
);
576 #if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
577 writel(self_ctl
& ~(1 << 8), &mac
->selfctl
);
578 #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
580 while (readl(&mac
->miists
) & MIISTS_BUSY
)
584 * Issue the MII 'read' command. Wait for the command to complete.
585 * Read the MII data value.
587 writel(MIICMD_OPCODE_READ
| ((uint32_t)addr
<< 5) | (uint32_t)reg
,
589 while (readl(&mac
->miists
) & MIISTS_BUSY
)
592 value
= (unsigned short)readl(&mac
->miidata
);
594 /* Restore the saved SelfCTL value and return. */
595 writel(self_ctl
, &mac
->selfctl
);
600 debug("-ep93xx_miiphy_read");
607 * Write a 16-bit value to an MII register.
609 static int ep93xx_miiphy_write(struct mii_dev
*bus
, int addr
, int devad
,
612 struct mac_regs
*mac
= (struct mac_regs
*)MAC_BASE
;
616 debug("+ep93xx_miiphy_write");
618 /* Parameter checks */
619 BUG_ON(bus
->name
== NULL
);
620 BUG_ON(addr
> MII_ADDRESS_MAX
);
621 BUG_ON(reg
> MII_REGISTER_MAX
);
624 * Save the current SelfCTL register value. Set MAC to suppress
625 * preamble bits. Wait for any previous MII command to complete
626 * before issuing the new command.
628 self_ctl
= readl(&mac
->selfctl
);
629 #if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
630 writel(self_ctl
& ~(1 << 8), &mac
->selfctl
);
631 #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
633 while (readl(&mac
->miists
) & MIISTS_BUSY
)
636 /* Issue the MII 'write' command. Wait for the command to complete. */
637 writel((uint32_t)value
, &mac
->miidata
);
638 writel(MIICMD_OPCODE_WRITE
| ((uint32_t)addr
<< 5) | (uint32_t)reg
,
640 while (readl(&mac
->miists
) & MIISTS_BUSY
)
643 /* Restore the saved SelfCTL value and return. */
644 writel(self_ctl
, &mac
->selfctl
);
649 debug("-ep93xx_miiphy_write");
652 #endif /* defined(CONFIG_MII) */